ASoC: rsnd: remove RSND_REG_ from rsnd_reg
Current rsnd is using RSND_REG_xxx for register naming, and using RSND_REG_##f style macro for read/write. The biggest reason why it uses this style is that we can avoid non-existing register access. But, its demerit is sequential register access code will be very ugly. Current rsnd driver is well tested, so, let's remove RSND_REG_ from rsnd_reg, and cleanup sequential register access code. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
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0a26d6df4f
commit
b7169ddea2
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@ -249,28 +249,8 @@ int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
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out = out << shift;
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mask = 0x0f1f << shift;
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switch (id / 2) {
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case 0:
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rsnd_mod_bset(adg_mod, SRCIN_TIMSEL0, mask, in);
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rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL0, mask, out);
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break;
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case 1:
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rsnd_mod_bset(adg_mod, SRCIN_TIMSEL1, mask, in);
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rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL1, mask, out);
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break;
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case 2:
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rsnd_mod_bset(adg_mod, SRCIN_TIMSEL2, mask, in);
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rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL2, mask, out);
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break;
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case 3:
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rsnd_mod_bset(adg_mod, SRCIN_TIMSEL3, mask, in);
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rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL3, mask, out);
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break;
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case 4:
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rsnd_mod_bset(adg_mod, SRCIN_TIMSEL4, mask, in);
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rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL4, mask, out);
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break;
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}
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rsnd_mod_bset(adg_mod, SRCIN_TIMSEL(id / 2), mask, in);
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rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL(id / 2), mask, out);
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if (en)
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rsnd_mod_bset(adg_mod, DIV_EN, en, en);
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@ -299,17 +279,7 @@ static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
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if (id == 8)
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return;
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switch (id / 4) {
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case 0:
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rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL0, mask, val);
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break;
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case 1:
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rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL1, mask, val);
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break;
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case 2:
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rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL2, mask, val);
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break;
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}
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rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL(id / 4), mask, val);
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dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val);
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}
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@ -72,10 +72,7 @@
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struct rsnd_ctu {
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struct rsnd_mod mod;
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struct rsnd_kctrl_cfg_m pass;
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struct rsnd_kctrl_cfg_m sv0;
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struct rsnd_kctrl_cfg_m sv1;
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struct rsnd_kctrl_cfg_m sv2;
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struct rsnd_kctrl_cfg_m sv3;
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struct rsnd_kctrl_cfg_m sv[4];
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struct rsnd_kctrl_cfg_s reset;
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int channels;
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u32 flags;
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@ -120,7 +117,7 @@ static void rsnd_ctu_value_init(struct rsnd_dai_stream *io,
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struct rsnd_ctu *ctu = rsnd_mod_to_ctu(mod);
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u32 cpmdr = 0;
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u32 scmdr = 0;
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int i;
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int i, j;
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for (i = 0; i < RSND_MAX_CHANNELS; i++) {
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u32 val = rsnd_kctrl_valm(ctu->pass, i);
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@ -139,45 +136,13 @@ static void rsnd_ctu_value_init(struct rsnd_dai_stream *io,
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rsnd_mod_write(mod, CTU_SCMDR, scmdr);
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if (scmdr > 0) {
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rsnd_mod_write(mod, CTU_SV00R, rsnd_kctrl_valm(ctu->sv0, 0));
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rsnd_mod_write(mod, CTU_SV01R, rsnd_kctrl_valm(ctu->sv0, 1));
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rsnd_mod_write(mod, CTU_SV02R, rsnd_kctrl_valm(ctu->sv0, 2));
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rsnd_mod_write(mod, CTU_SV03R, rsnd_kctrl_valm(ctu->sv0, 3));
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rsnd_mod_write(mod, CTU_SV04R, rsnd_kctrl_valm(ctu->sv0, 4));
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rsnd_mod_write(mod, CTU_SV05R, rsnd_kctrl_valm(ctu->sv0, 5));
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rsnd_mod_write(mod, CTU_SV06R, rsnd_kctrl_valm(ctu->sv0, 6));
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rsnd_mod_write(mod, CTU_SV07R, rsnd_kctrl_valm(ctu->sv0, 7));
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}
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if (scmdr > 1) {
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rsnd_mod_write(mod, CTU_SV10R, rsnd_kctrl_valm(ctu->sv1, 0));
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rsnd_mod_write(mod, CTU_SV11R, rsnd_kctrl_valm(ctu->sv1, 1));
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rsnd_mod_write(mod, CTU_SV12R, rsnd_kctrl_valm(ctu->sv1, 2));
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rsnd_mod_write(mod, CTU_SV13R, rsnd_kctrl_valm(ctu->sv1, 3));
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rsnd_mod_write(mod, CTU_SV14R, rsnd_kctrl_valm(ctu->sv1, 4));
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rsnd_mod_write(mod, CTU_SV15R, rsnd_kctrl_valm(ctu->sv1, 5));
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rsnd_mod_write(mod, CTU_SV16R, rsnd_kctrl_valm(ctu->sv1, 6));
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rsnd_mod_write(mod, CTU_SV17R, rsnd_kctrl_valm(ctu->sv1, 7));
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}
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if (scmdr > 2) {
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rsnd_mod_write(mod, CTU_SV20R, rsnd_kctrl_valm(ctu->sv2, 0));
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rsnd_mod_write(mod, CTU_SV21R, rsnd_kctrl_valm(ctu->sv2, 1));
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rsnd_mod_write(mod, CTU_SV22R, rsnd_kctrl_valm(ctu->sv2, 2));
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rsnd_mod_write(mod, CTU_SV23R, rsnd_kctrl_valm(ctu->sv2, 3));
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rsnd_mod_write(mod, CTU_SV24R, rsnd_kctrl_valm(ctu->sv2, 4));
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rsnd_mod_write(mod, CTU_SV25R, rsnd_kctrl_valm(ctu->sv2, 5));
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rsnd_mod_write(mod, CTU_SV26R, rsnd_kctrl_valm(ctu->sv2, 6));
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rsnd_mod_write(mod, CTU_SV27R, rsnd_kctrl_valm(ctu->sv2, 7));
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}
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if (scmdr > 3) {
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rsnd_mod_write(mod, CTU_SV30R, rsnd_kctrl_valm(ctu->sv3, 0));
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rsnd_mod_write(mod, CTU_SV31R, rsnd_kctrl_valm(ctu->sv3, 1));
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rsnd_mod_write(mod, CTU_SV32R, rsnd_kctrl_valm(ctu->sv3, 2));
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rsnd_mod_write(mod, CTU_SV33R, rsnd_kctrl_valm(ctu->sv3, 3));
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rsnd_mod_write(mod, CTU_SV34R, rsnd_kctrl_valm(ctu->sv3, 4));
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rsnd_mod_write(mod, CTU_SV35R, rsnd_kctrl_valm(ctu->sv3, 5));
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rsnd_mod_write(mod, CTU_SV36R, rsnd_kctrl_valm(ctu->sv3, 6));
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rsnd_mod_write(mod, CTU_SV37R, rsnd_kctrl_valm(ctu->sv3, 7));
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for (i = 0; i < 4; i++) {
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if (i >= scmdr)
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break;
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for (j = 0; j < RSND_MAX_CHANNELS; j++)
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rsnd_mod_write(mod, CTU_SVxxR(i, j), rsnd_kctrl_valm(ctu->sv[i], j));
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}
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rsnd_mod_write(mod, CTU_CTUIR, 0);
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@ -194,10 +159,10 @@ static void rsnd_ctu_value_reset(struct rsnd_dai_stream *io,
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for (i = 0; i < RSND_MAX_CHANNELS; i++) {
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rsnd_kctrl_valm(ctu->pass, i) = 0;
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rsnd_kctrl_valm(ctu->sv0, i) = 0;
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rsnd_kctrl_valm(ctu->sv1, i) = 0;
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rsnd_kctrl_valm(ctu->sv2, i) = 0;
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rsnd_kctrl_valm(ctu->sv3, i) = 0;
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rsnd_kctrl_valm(ctu->sv[0], i) = 0;
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rsnd_kctrl_valm(ctu->sv[1], i) = 0;
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rsnd_kctrl_valm(ctu->sv[2], i) = 0;
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rsnd_kctrl_valm(ctu->sv[3], i) = 0;
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}
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rsnd_kctrl_vals(ctu->reset) = 0;
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}
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@ -247,7 +212,7 @@ static int rsnd_ctu_pcm_new(struct rsnd_mod *mod,
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ret = rsnd_kctrl_new_m(mod, io, rtd, "CTU SV0",
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rsnd_kctrl_accept_anytime,
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NULL,
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&ctu->sv0, RSND_MAX_CHANNELS,
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&ctu->sv[0], RSND_MAX_CHANNELS,
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0x00FFFFFF);
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if (ret < 0)
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return ret;
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@ -256,7 +221,7 @@ static int rsnd_ctu_pcm_new(struct rsnd_mod *mod,
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ret = rsnd_kctrl_new_m(mod, io, rtd, "CTU SV1",
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rsnd_kctrl_accept_anytime,
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NULL,
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&ctu->sv1, RSND_MAX_CHANNELS,
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&ctu->sv[1], RSND_MAX_CHANNELS,
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0x00FFFFFF);
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if (ret < 0)
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return ret;
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@ -265,7 +230,7 @@ static int rsnd_ctu_pcm_new(struct rsnd_mod *mod,
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ret = rsnd_kctrl_new_m(mod, io, rtd, "CTU SV2",
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rsnd_kctrl_accept_anytime,
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NULL,
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&ctu->sv2, RSND_MAX_CHANNELS,
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&ctu->sv[2], RSND_MAX_CHANNELS,
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0x00FFFFFF);
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if (ret < 0)
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return ret;
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@ -274,7 +239,7 @@ static int rsnd_ctu_pcm_new(struct rsnd_mod *mod,
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ret = rsnd_kctrl_new_m(mod, io, rtd, "CTU SV3",
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rsnd_kctrl_accept_anytime,
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NULL,
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&ctu->sv3, RSND_MAX_CHANNELS,
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&ctu->sv[3], RSND_MAX_CHANNELS,
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0x00FFFFFF);
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if (ret < 0)
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return ret;
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@ -89,14 +89,8 @@ static void rsnd_dvc_volume_parameter(struct rsnd_dai_stream *io,
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val[i] = rsnd_kctrl_valm(dvc->volume, i);
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/* Enable Digital Volume */
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rsnd_mod_write(mod, DVC_VOL0R, val[0]);
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rsnd_mod_write(mod, DVC_VOL1R, val[1]);
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rsnd_mod_write(mod, DVC_VOL2R, val[2]);
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rsnd_mod_write(mod, DVC_VOL3R, val[3]);
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rsnd_mod_write(mod, DVC_VOL4R, val[4]);
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rsnd_mod_write(mod, DVC_VOL5R, val[5]);
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rsnd_mod_write(mod, DVC_VOL6R, val[6]);
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rsnd_mod_write(mod, DVC_VOL7R, val[7]);
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for (i = 0; i < RSND_MAX_CHANNELS; i++)
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rsnd_mod_write(mod, DVC_VOLxR(i), val[i]);
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}
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static void rsnd_dvc_volume_init(struct rsnd_dai_stream *io,
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@ -26,8 +26,8 @@ struct rsnd_gen {
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struct regmap *regmap[RSND_BASE_MAX];
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/* RSND_REG_MAX base */
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struct regmap_field *regs[RSND_REG_MAX];
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const char *reg_name[RSND_REG_MAX];
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struct regmap_field *regs[REG_MAX];
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const char *reg_name[REG_MAX];
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};
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#define rsnd_priv_to_gen(p) ((struct rsnd_gen *)(p)->gen)
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@ -49,11 +49,11 @@ struct rsnd_regmap_field_conf {
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}
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/* single address mapping */
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#define RSND_GEN_S_REG(id, offset) \
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RSND_REG_SET(RSND_REG_##id, offset, 0, #id)
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RSND_REG_SET(id, offset, 0, #id)
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/* multi address mapping */
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#define RSND_GEN_M_REG(id, offset, _id_offset) \
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RSND_REG_SET(RSND_REG_##id, offset, _id_offset, #id)
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RSND_REG_SET(id, offset, _id_offset, #id)
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/*
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* basic function
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@ -79,9 +79,9 @@ static int rsnd_mod_id_cmd(struct rsnd_mod *mod)
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return rsnd_mod_id(mod);
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}
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u32 rsnd_read(struct rsnd_priv *priv,
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struct rsnd_mod *mod, enum rsnd_reg reg)
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u32 rsnd_mod_read(struct rsnd_mod *mod, enum rsnd_reg reg)
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{
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struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
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struct device *dev = rsnd_priv_to_dev(priv);
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struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
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u32 val;
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@ -98,10 +98,10 @@ u32 rsnd_read(struct rsnd_priv *priv,
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return val;
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}
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void rsnd_write(struct rsnd_priv *priv,
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struct rsnd_mod *mod,
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enum rsnd_reg reg, u32 data)
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void rsnd_mod_write(struct rsnd_mod *mod,
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enum rsnd_reg reg, u32 data)
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{
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struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
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struct device *dev = rsnd_priv_to_dev(priv);
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struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
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@ -115,9 +115,10 @@ void rsnd_write(struct rsnd_priv *priv,
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rsnd_reg_name(gen, reg), reg, data);
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}
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void rsnd_bset(struct rsnd_priv *priv, struct rsnd_mod *mod,
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enum rsnd_reg reg, u32 mask, u32 data)
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void rsnd_mod_bset(struct rsnd_mod *mod,
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enum rsnd_reg reg, u32 mask, u32 data)
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{
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struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
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struct device *dev = rsnd_priv_to_dev(priv);
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struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
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@ -42,165 +42,175 @@
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*/
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enum rsnd_reg {
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/* SCU (MIX/CTU/DVC) */
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RSND_REG_SRC_I_BUSIF_MODE,
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RSND_REG_SRC_O_BUSIF_MODE,
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RSND_REG_SRC_ROUTE_MODE0,
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RSND_REG_SRC_SWRSR,
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RSND_REG_SRC_SRCIR,
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RSND_REG_SRC_ADINR,
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RSND_REG_SRC_IFSCR,
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RSND_REG_SRC_IFSVR,
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RSND_REG_SRC_SRCCR,
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RSND_REG_SRC_CTRL,
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RSND_REG_SRC_BSDSR,
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RSND_REG_SRC_BSISR,
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RSND_REG_SRC_INT_ENABLE0,
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RSND_REG_SRC_BUSIF_DALIGN,
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RSND_REG_SRCIN_TIMSEL0,
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RSND_REG_SRCIN_TIMSEL1,
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RSND_REG_SRCIN_TIMSEL2,
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RSND_REG_SRCIN_TIMSEL3,
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RSND_REG_SRCIN_TIMSEL4,
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RSND_REG_SRCOUT_TIMSEL0,
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RSND_REG_SRCOUT_TIMSEL1,
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RSND_REG_SRCOUT_TIMSEL2,
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RSND_REG_SRCOUT_TIMSEL3,
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RSND_REG_SRCOUT_TIMSEL4,
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RSND_REG_SCU_SYS_STATUS0,
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RSND_REG_SCU_SYS_STATUS1,
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RSND_REG_SCU_SYS_INT_EN0,
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RSND_REG_SCU_SYS_INT_EN1,
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RSND_REG_CMD_CTRL,
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RSND_REG_CMD_BUSIF_MODE,
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RSND_REG_CMD_BUSIF_DALIGN,
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RSND_REG_CMD_ROUTE_SLCT,
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RSND_REG_CMDOUT_TIMSEL,
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RSND_REG_CTU_SWRSR,
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RSND_REG_CTU_CTUIR,
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RSND_REG_CTU_ADINR,
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RSND_REG_CTU_CPMDR,
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RSND_REG_CTU_SCMDR,
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RSND_REG_CTU_SV00R,
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RSND_REG_CTU_SV01R,
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RSND_REG_CTU_SV02R,
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RSND_REG_CTU_SV03R,
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RSND_REG_CTU_SV04R,
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RSND_REG_CTU_SV05R,
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RSND_REG_CTU_SV06R,
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RSND_REG_CTU_SV07R,
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RSND_REG_CTU_SV10R,
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RSND_REG_CTU_SV11R,
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RSND_REG_CTU_SV12R,
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RSND_REG_CTU_SV13R,
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RSND_REG_CTU_SV14R,
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RSND_REG_CTU_SV15R,
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RSND_REG_CTU_SV16R,
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RSND_REG_CTU_SV17R,
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RSND_REG_CTU_SV20R,
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RSND_REG_CTU_SV21R,
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RSND_REG_CTU_SV22R,
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RSND_REG_CTU_SV23R,
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RSND_REG_CTU_SV24R,
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RSND_REG_CTU_SV25R,
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RSND_REG_CTU_SV26R,
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RSND_REG_CTU_SV27R,
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RSND_REG_CTU_SV30R,
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RSND_REG_CTU_SV31R,
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RSND_REG_CTU_SV32R,
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RSND_REG_CTU_SV33R,
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RSND_REG_CTU_SV34R,
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RSND_REG_CTU_SV35R,
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RSND_REG_CTU_SV36R,
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RSND_REG_CTU_SV37R,
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RSND_REG_MIX_SWRSR,
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RSND_REG_MIX_MIXIR,
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RSND_REG_MIX_ADINR,
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RSND_REG_MIX_MIXMR,
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RSND_REG_MIX_MVPDR,
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RSND_REG_MIX_MDBAR,
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RSND_REG_MIX_MDBBR,
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RSND_REG_MIX_MDBCR,
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RSND_REG_MIX_MDBDR,
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RSND_REG_MIX_MDBER,
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RSND_REG_DVC_SWRSR,
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RSND_REG_DVC_DVUIR,
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RSND_REG_DVC_ADINR,
|
||||
RSND_REG_DVC_DVUCR,
|
||||
RSND_REG_DVC_ZCMCR,
|
||||
RSND_REG_DVC_VOL0R,
|
||||
RSND_REG_DVC_VOL1R,
|
||||
RSND_REG_DVC_VOL2R,
|
||||
RSND_REG_DVC_VOL3R,
|
||||
RSND_REG_DVC_VOL4R,
|
||||
RSND_REG_DVC_VOL5R,
|
||||
RSND_REG_DVC_VOL6R,
|
||||
RSND_REG_DVC_VOL7R,
|
||||
RSND_REG_DVC_DVUER,
|
||||
RSND_REG_DVC_VRCTR,
|
||||
RSND_REG_DVC_VRPDR,
|
||||
RSND_REG_DVC_VRDBR,
|
||||
SRC_I_BUSIF_MODE,
|
||||
SRC_O_BUSIF_MODE,
|
||||
SRC_ROUTE_MODE0,
|
||||
SRC_SWRSR,
|
||||
SRC_SRCIR,
|
||||
SRC_ADINR,
|
||||
SRC_IFSCR,
|
||||
SRC_IFSVR,
|
||||
SRC_SRCCR,
|
||||
SRC_CTRL,
|
||||
SRC_BSDSR,
|
||||
SRC_BSISR,
|
||||
SRC_INT_ENABLE0,
|
||||
SRC_BUSIF_DALIGN,
|
||||
SRCIN_TIMSEL0,
|
||||
SRCIN_TIMSEL1,
|
||||
SRCIN_TIMSEL2,
|
||||
SRCIN_TIMSEL3,
|
||||
SRCIN_TIMSEL4,
|
||||
SRCOUT_TIMSEL0,
|
||||
SRCOUT_TIMSEL1,
|
||||
SRCOUT_TIMSEL2,
|
||||
SRCOUT_TIMSEL3,
|
||||
SRCOUT_TIMSEL4,
|
||||
SCU_SYS_STATUS0,
|
||||
SCU_SYS_STATUS1,
|
||||
SCU_SYS_INT_EN0,
|
||||
SCU_SYS_INT_EN1,
|
||||
CMD_CTRL,
|
||||
CMD_BUSIF_MODE,
|
||||
CMD_BUSIF_DALIGN,
|
||||
CMD_ROUTE_SLCT,
|
||||
CMDOUT_TIMSEL,
|
||||
CTU_SWRSR,
|
||||
CTU_CTUIR,
|
||||
CTU_ADINR,
|
||||
CTU_CPMDR,
|
||||
CTU_SCMDR,
|
||||
CTU_SV00R,
|
||||
CTU_SV01R,
|
||||
CTU_SV02R,
|
||||
CTU_SV03R,
|
||||
CTU_SV04R,
|
||||
CTU_SV05R,
|
||||
CTU_SV06R,
|
||||
CTU_SV07R,
|
||||
CTU_SV10R,
|
||||
CTU_SV11R,
|
||||
CTU_SV12R,
|
||||
CTU_SV13R,
|
||||
CTU_SV14R,
|
||||
CTU_SV15R,
|
||||
CTU_SV16R,
|
||||
CTU_SV17R,
|
||||
CTU_SV20R,
|
||||
CTU_SV21R,
|
||||
CTU_SV22R,
|
||||
CTU_SV23R,
|
||||
CTU_SV24R,
|
||||
CTU_SV25R,
|
||||
CTU_SV26R,
|
||||
CTU_SV27R,
|
||||
CTU_SV30R,
|
||||
CTU_SV31R,
|
||||
CTU_SV32R,
|
||||
CTU_SV33R,
|
||||
CTU_SV34R,
|
||||
CTU_SV35R,
|
||||
CTU_SV36R,
|
||||
CTU_SV37R,
|
||||
MIX_SWRSR,
|
||||
MIX_MIXIR,
|
||||
MIX_ADINR,
|
||||
MIX_MIXMR,
|
||||
MIX_MVPDR,
|
||||
MIX_MDBAR,
|
||||
MIX_MDBBR,
|
||||
MIX_MDBCR,
|
||||
MIX_MDBDR,
|
||||
MIX_MDBER,
|
||||
DVC_SWRSR,
|
||||
DVC_DVUIR,
|
||||
DVC_ADINR,
|
||||
DVC_DVUCR,
|
||||
DVC_ZCMCR,
|
||||
DVC_VOL0R,
|
||||
DVC_VOL1R,
|
||||
DVC_VOL2R,
|
||||
DVC_VOL3R,
|
||||
DVC_VOL4R,
|
||||
DVC_VOL5R,
|
||||
DVC_VOL6R,
|
||||
DVC_VOL7R,
|
||||
DVC_DVUER,
|
||||
DVC_VRCTR,
|
||||
DVC_VRPDR,
|
||||
DVC_VRDBR,
|
||||
|
||||
/* ADG */
|
||||
RSND_REG_BRRA,
|
||||
RSND_REG_BRRB,
|
||||
RSND_REG_BRGCKR,
|
||||
RSND_REG_DIV_EN,
|
||||
RSND_REG_AUDIO_CLK_SEL0,
|
||||
RSND_REG_AUDIO_CLK_SEL1,
|
||||
RSND_REG_AUDIO_CLK_SEL2,
|
||||
BRRA,
|
||||
BRRB,
|
||||
BRGCKR,
|
||||
DIV_EN,
|
||||
AUDIO_CLK_SEL0,
|
||||
AUDIO_CLK_SEL1,
|
||||
AUDIO_CLK_SEL2,
|
||||
|
||||
/* SSIU */
|
||||
RSND_REG_SSI_MODE,
|
||||
RSND_REG_SSI_MODE0,
|
||||
RSND_REG_SSI_MODE1,
|
||||
RSND_REG_SSI_MODE2,
|
||||
RSND_REG_SSI_CONTROL,
|
||||
RSND_REG_SSI_CTRL,
|
||||
RSND_REG_SSI_BUSIF0_MODE,
|
||||
RSND_REG_SSI_BUSIF0_ADINR,
|
||||
RSND_REG_SSI_BUSIF0_DALIGN,
|
||||
RSND_REG_SSI_BUSIF1_MODE,
|
||||
RSND_REG_SSI_BUSIF1_ADINR,
|
||||
RSND_REG_SSI_BUSIF1_DALIGN,
|
||||
RSND_REG_SSI_BUSIF2_MODE,
|
||||
RSND_REG_SSI_BUSIF2_ADINR,
|
||||
RSND_REG_SSI_BUSIF2_DALIGN,
|
||||
RSND_REG_SSI_BUSIF3_MODE,
|
||||
RSND_REG_SSI_BUSIF3_ADINR,
|
||||
RSND_REG_SSI_BUSIF3_DALIGN,
|
||||
RSND_REG_SSI_BUSIF4_MODE,
|
||||
RSND_REG_SSI_BUSIF4_ADINR,
|
||||
RSND_REG_SSI_BUSIF4_DALIGN,
|
||||
RSND_REG_SSI_BUSIF5_MODE,
|
||||
RSND_REG_SSI_BUSIF5_ADINR,
|
||||
RSND_REG_SSI_BUSIF5_DALIGN,
|
||||
RSND_REG_SSI_BUSIF6_MODE,
|
||||
RSND_REG_SSI_BUSIF6_ADINR,
|
||||
RSND_REG_SSI_BUSIF6_DALIGN,
|
||||
RSND_REG_SSI_BUSIF7_MODE,
|
||||
RSND_REG_SSI_BUSIF7_ADINR,
|
||||
RSND_REG_SSI_BUSIF7_DALIGN,
|
||||
RSND_REG_SSI_INT_ENABLE,
|
||||
RSND_REG_SSI_SYS_STATUS0,
|
||||
RSND_REG_SSI_SYS_STATUS1,
|
||||
RSND_REG_SSI_SYS_STATUS2,
|
||||
RSND_REG_SSI_SYS_STATUS3,
|
||||
RSND_REG_SSI_SYS_STATUS4,
|
||||
RSND_REG_SSI_SYS_STATUS5,
|
||||
RSND_REG_SSI_SYS_STATUS6,
|
||||
RSND_REG_SSI_SYS_STATUS7,
|
||||
RSND_REG_HDMI0_SEL,
|
||||
RSND_REG_HDMI1_SEL,
|
||||
SSI_MODE,
|
||||
SSI_MODE0,
|
||||
SSI_MODE1,
|
||||
SSI_MODE2,
|
||||
SSI_CONTROL,
|
||||
SSI_CTRL,
|
||||
SSI_BUSIF0_MODE,
|
||||
SSI_BUSIF1_MODE,
|
||||
SSI_BUSIF2_MODE,
|
||||
SSI_BUSIF3_MODE,
|
||||
SSI_BUSIF4_MODE,
|
||||
SSI_BUSIF5_MODE,
|
||||
SSI_BUSIF6_MODE,
|
||||
SSI_BUSIF7_MODE,
|
||||
SSI_BUSIF0_ADINR,
|
||||
SSI_BUSIF1_ADINR,
|
||||
SSI_BUSIF2_ADINR,
|
||||
SSI_BUSIF3_ADINR,
|
||||
SSI_BUSIF4_ADINR,
|
||||
SSI_BUSIF5_ADINR,
|
||||
SSI_BUSIF6_ADINR,
|
||||
SSI_BUSIF7_ADINR,
|
||||
SSI_BUSIF0_DALIGN,
|
||||
SSI_BUSIF1_DALIGN,
|
||||
SSI_BUSIF2_DALIGN,
|
||||
SSI_BUSIF3_DALIGN,
|
||||
SSI_BUSIF4_DALIGN,
|
||||
SSI_BUSIF5_DALIGN,
|
||||
SSI_BUSIF6_DALIGN,
|
||||
SSI_BUSIF7_DALIGN,
|
||||
SSI_INT_ENABLE,
|
||||
SSI_SYS_STATUS0,
|
||||
SSI_SYS_STATUS1,
|
||||
SSI_SYS_STATUS2,
|
||||
SSI_SYS_STATUS3,
|
||||
SSI_SYS_STATUS4,
|
||||
SSI_SYS_STATUS5,
|
||||
SSI_SYS_STATUS6,
|
||||
SSI_SYS_STATUS7,
|
||||
HDMI0_SEL,
|
||||
HDMI1_SEL,
|
||||
|
||||
/* SSI */
|
||||
RSND_REG_SSICR,
|
||||
RSND_REG_SSISR,
|
||||
RSND_REG_SSITDR,
|
||||
RSND_REG_SSIRDR,
|
||||
RSND_REG_SSIWSR,
|
||||
SSICR,
|
||||
SSISR,
|
||||
SSITDR,
|
||||
SSIRDR,
|
||||
SSIWSR,
|
||||
|
||||
RSND_REG_MAX,
|
||||
REG_MAX,
|
||||
};
|
||||
#define SRCIN_TIMSEL(i) (SRCIN_TIMSEL0 + (i))
|
||||
#define SRCOUT_TIMSEL(i) (SRCOUT_TIMSEL0 + (i))
|
||||
#define CTU_SVxxR(i, j) (CTU_SV00R + (i * 8) + (j))
|
||||
#define DVC_VOLxR(i) (DVC_VOL0R + (i))
|
||||
#define AUDIO_CLK_SEL(i) (AUDIO_CLK_SEL0 + (i))
|
||||
#define SSI_BUSIF_MODE(i) (SSI_BUSIF0_MODE + (i))
|
||||
#define SSI_BUSIF_ADINR(i) (SSI_BUSIF0_ADINR + (i))
|
||||
#define SSI_BUSIF_DALIGN(i) (SSI_BUSIF0_DALIGN + (i))
|
||||
#define SSI_SYS_STATUS(i) (SSI_SYS_STATUS0 + (i))
|
||||
|
||||
|
||||
struct rsnd_priv;
|
||||
struct rsnd_mod;
|
||||
|
@ -210,20 +220,9 @@ struct rsnd_dai_stream;
|
|||
/*
|
||||
* R-Car basic functions
|
||||
*/
|
||||
#define rsnd_mod_read(m, r) \
|
||||
rsnd_read(rsnd_mod_to_priv(m), m, RSND_REG_##r)
|
||||
#define rsnd_mod_write(m, r, d) \
|
||||
rsnd_write(rsnd_mod_to_priv(m), m, RSND_REG_##r, d)
|
||||
#define rsnd_mod_bset(m, r, s, d) \
|
||||
rsnd_bset(rsnd_mod_to_priv(m), m, RSND_REG_##r, s, d)
|
||||
|
||||
u32 rsnd_read(struct rsnd_priv *priv, struct rsnd_mod *mod, enum rsnd_reg reg);
|
||||
void rsnd_write(struct rsnd_priv *priv, struct rsnd_mod *mod,
|
||||
enum rsnd_reg reg, u32 data);
|
||||
void rsnd_force_write(struct rsnd_priv *priv, struct rsnd_mod *mod,
|
||||
enum rsnd_reg reg, u32 data);
|
||||
void rsnd_bset(struct rsnd_priv *priv, struct rsnd_mod *mod, enum rsnd_reg reg,
|
||||
u32 mask, u32 data);
|
||||
u32 rsnd_mod_read(struct rsnd_mod *mod, enum rsnd_reg reg);
|
||||
void rsnd_mod_write(struct rsnd_mod *mod, enum rsnd_reg reg, u32 data);
|
||||
void rsnd_mod_bset(struct rsnd_mod *mod, enum rsnd_reg reg, u32 mask, u32 data);
|
||||
u32 rsnd_get_adinr_bit(struct rsnd_mod *mod, struct rsnd_dai_stream *io);
|
||||
u32 rsnd_get_dalign(struct rsnd_mod *mod, struct rsnd_dai_stream *io);
|
||||
u32 rsnd_get_busif_shift(struct rsnd_dai_stream *io, struct rsnd_mod *mod);
|
||||
|
|
|
@ -65,6 +65,7 @@ static int rsnd_ssiu_init(struct rsnd_mod *mod,
|
|||
int id = rsnd_mod_id(mod);
|
||||
u32 mask1, val1;
|
||||
u32 mask2, val2;
|
||||
int i;
|
||||
|
||||
/* clear status */
|
||||
switch (id) {
|
||||
|
@ -73,16 +74,12 @@ static int rsnd_ssiu_init(struct rsnd_mod *mod,
|
|||
case 2:
|
||||
case 3:
|
||||
case 4:
|
||||
rsnd_mod_write(mod, SSI_SYS_STATUS0, 0xf << (id * 4));
|
||||
rsnd_mod_write(mod, SSI_SYS_STATUS2, 0xf << (id * 4));
|
||||
rsnd_mod_write(mod, SSI_SYS_STATUS4, 0xf << (id * 4));
|
||||
rsnd_mod_write(mod, SSI_SYS_STATUS6, 0xf << (id * 4));
|
||||
for (i = 0; i < 4; i++)
|
||||
rsnd_mod_write(mod, SSI_SYS_STATUS(i * 2), 0xf << (id * 4));
|
||||
break;
|
||||
case 9:
|
||||
rsnd_mod_write(mod, SSI_SYS_STATUS1, 0xf << 4);
|
||||
rsnd_mod_write(mod, SSI_SYS_STATUS3, 0xf << 4);
|
||||
rsnd_mod_write(mod, SSI_SYS_STATUS5, 0xf << 4);
|
||||
rsnd_mod_write(mod, SSI_SYS_STATUS7, 0xf << 4);
|
||||
for (i = 0; i < 4; i++)
|
||||
rsnd_mod_write(mod, SSI_SYS_STATUS((i * 2) + 1), 0xf << (id * 4));
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -198,43 +195,15 @@ static int rsnd_ssiu_init_gen2(struct rsnd_mod *mod,
|
|||
id, busif);
|
||||
}
|
||||
|
||||
#define RSND_WRITE_BUSIF(i) \
|
||||
rsnd_mod_write(mod, SSI_BUSIF##i##_ADINR, \
|
||||
rsnd_get_adinr_bit(mod, io) | \
|
||||
(rsnd_io_is_play(io) ? \
|
||||
rsnd_runtime_channel_after_ctu(io) : \
|
||||
rsnd_runtime_channel_original(io))); \
|
||||
rsnd_mod_write(mod, SSI_BUSIF##i##_MODE, \
|
||||
rsnd_get_busif_shift(io, mod) | 1); \
|
||||
rsnd_mod_write(mod, SSI_BUSIF##i##_DALIGN, \
|
||||
rsnd_get_dalign(mod, io))
|
||||
|
||||
switch (busif) {
|
||||
case 0:
|
||||
RSND_WRITE_BUSIF(0);
|
||||
break;
|
||||
case 1:
|
||||
RSND_WRITE_BUSIF(1);
|
||||
break;
|
||||
case 2:
|
||||
RSND_WRITE_BUSIF(2);
|
||||
break;
|
||||
case 3:
|
||||
RSND_WRITE_BUSIF(3);
|
||||
break;
|
||||
case 4:
|
||||
RSND_WRITE_BUSIF(4);
|
||||
break;
|
||||
case 5:
|
||||
RSND_WRITE_BUSIF(5);
|
||||
break;
|
||||
case 6:
|
||||
RSND_WRITE_BUSIF(6);
|
||||
break;
|
||||
case 7:
|
||||
RSND_WRITE_BUSIF(7);
|
||||
break;
|
||||
}
|
||||
rsnd_mod_write(mod, SSI_BUSIF_ADINR(busif),
|
||||
rsnd_get_adinr_bit(mod, io) |
|
||||
(rsnd_io_is_play(io) ?
|
||||
rsnd_runtime_channel_after_ctu(io) :
|
||||
rsnd_runtime_channel_original(io)));
|
||||
rsnd_mod_write(mod, SSI_BUSIF_MODE(busif),
|
||||
rsnd_get_busif_shift(io, mod) | 1);
|
||||
rsnd_mod_write(mod, SSI_BUSIF_DALIGN(busif),
|
||||
rsnd_get_dalign(mod, io));
|
||||
}
|
||||
|
||||
if (has_hdmi0 || has_hdmi1) {
|
||||
|
|
Loading…
Reference in New Issue