drm/nouveau/clk: switch to subdev printk macros
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
a699a85add
commit
b907649e7b
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@ -76,8 +76,10 @@ nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust,
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static int
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nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
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{
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struct nvkm_therm *therm = nvkm_therm(clk);
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struct nvkm_volt *volt = nvkm_volt(clk);
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struct nvkm_subdev *subdev = &clk->subdev;
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struct nvkm_device *device = subdev->device;
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struct nvkm_therm *therm = device->therm;
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struct nvkm_volt *volt = device->volt;
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struct nvkm_cstate *cstate;
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int ret;
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@ -90,7 +92,7 @@ nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
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if (therm) {
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ret = nvkm_therm_cstate(therm, pstate->fanspeed, +1);
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if (ret && ret != -ENODEV) {
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nv_error(clk, "failed to raise fan speed: %d\n", ret);
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nvkm_error(subdev, "failed to raise fan speed: %d\n", ret);
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return ret;
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}
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}
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@ -98,7 +100,7 @@ nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
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if (volt) {
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ret = volt->set_id(volt, cstate->voltage, +1);
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if (ret && ret != -ENODEV) {
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nv_error(clk, "failed to raise voltage: %d\n", ret);
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nvkm_error(subdev, "failed to raise voltage: %d\n", ret);
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return ret;
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}
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}
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@ -112,13 +114,13 @@ nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
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if (volt) {
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ret = volt->set_id(volt, cstate->voltage, -1);
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if (ret && ret != -ENODEV)
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nv_error(clk, "failed to lower voltage: %d\n", ret);
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nvkm_error(subdev, "failed to lower voltage: %d\n", ret);
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}
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if (therm) {
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ret = nvkm_therm_cstate(therm, pstate->fanspeed, -1);
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if (ret && ret != -ENODEV)
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nv_error(clk, "failed to lower fan speed: %d\n", ret);
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nvkm_error(subdev, "failed to lower fan speed: %d\n", ret);
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}
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return ret;
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@ -171,7 +173,8 @@ nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate)
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static int
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nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei)
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{
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struct nvkm_fb *fb = nvkm_fb(clk);
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struct nvkm_subdev *subdev = &clk->subdev;
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struct nvkm_fb *fb = subdev->device->fb;
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struct nvkm_pstate *pstate;
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int ret, idx = 0;
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@ -180,7 +183,7 @@ nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei)
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break;
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}
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nv_debug(clk, "setting performance state %d\n", pstatei);
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nvkm_debug(subdev, "setting performance state %d\n", pstatei);
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clk->pstate = pstatei;
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if (fb->ram && fb->ram->calc) {
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@ -200,15 +203,16 @@ static void
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nvkm_pstate_work(struct work_struct *work)
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{
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struct nvkm_clk *clk = container_of(work, typeof(*clk), work);
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struct nvkm_subdev *subdev = &clk->subdev;
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int pstate;
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if (!atomic_xchg(&clk->waiting, 0))
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return;
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clk->pwrsrc = power_supply_is_system_supplied();
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nv_trace(clk, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n",
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clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc,
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clk->astate, clk->tstate, clk->dstate);
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nvkm_trace(subdev, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n",
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clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc,
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clk->astate, clk->tstate, clk->dstate);
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pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc;
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if (clk->state_nr && pstate != -1) {
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@ -219,12 +223,12 @@ nvkm_pstate_work(struct work_struct *work)
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pstate = clk->pstate = -1;
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}
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nv_trace(clk, "-> %d\n", pstate);
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nvkm_trace(subdev, "-> %d\n", pstate);
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if (pstate != clk->pstate) {
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int ret = nvkm_pstate_prog(clk, pstate);
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if (ret) {
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nv_error(clk, "error setting pstate %d: %d\n",
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pstate, ret);
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nvkm_error(subdev, "error setting pstate %d: %d\n",
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pstate, ret);
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}
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}
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@ -247,6 +251,7 @@ nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate)
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{
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struct nvkm_domain *clock = clk->domains - 1;
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struct nvkm_cstate *cstate;
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struct nvkm_subdev *subdev = &clk->subdev;
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char info[3][32] = { "", "", "" };
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char name[4] = "--";
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int i = -1;
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@ -260,12 +265,12 @@ nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate)
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if (hi == 0)
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continue;
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nv_debug(clk, "%02x: %10d KHz\n", clock->name, lo);
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nvkm_debug(subdev, "%02x: %10d KHz\n", clock->name, lo);
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list_for_each_entry(cstate, &pstate->list, head) {
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u32 freq = cstate->domain[clock->name];
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lo = min(lo, freq);
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hi = max(hi, freq);
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nv_debug(clk, "%10d KHz\n", freq);
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nvkm_debug(subdev, "%10d KHz\n", freq);
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}
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if (clock->mname && ++i < ARRAY_SIZE(info)) {
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@ -281,7 +286,7 @@ nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate)
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}
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}
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nv_info(clk, "%s: %s %s %s\n", name, info[0], info[1], info[2]);
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nvkm_debug(subdev, "%s: %s %s %s\n", name, info[0], info[1], info[2]);
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}
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static void
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@ -481,6 +486,7 @@ int
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_nvkm_clk_init(struct nvkm_object *object)
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{
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struct nvkm_clk *clk = (void *)object;
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struct nvkm_subdev *subdev = &clk->subdev;
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struct nvkm_domain *clock = clk->domains;
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int ret;
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@ -495,7 +501,7 @@ _nvkm_clk_init(struct nvkm_object *object)
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while (clock->name != nv_clk_src_max) {
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ret = clk->read(clk, clock->name);
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if (ret < 0) {
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nv_error(clk, "%02x freq unknown\n", clock->name);
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nvkm_error(subdev, "%02x freq unknown\n", clock->name);
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return ret;
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}
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clk->bstate.base.domain[clock->name] = ret;
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@ -149,7 +149,8 @@ static int
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gf100_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
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{
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struct gf100_clk *clk = container_of(obj, typeof(*clk), base);
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struct nvkm_device *device = clk->base.subdev.device;
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struct nvkm_subdev *subdev = &clk->base.subdev;
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struct nvkm_device *device = subdev->device;
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switch (src) {
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case nv_clk_src_crystal:
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@ -191,7 +192,7 @@ gf100_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
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case nv_clk_src_vdec:
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return read_clk(clk, 0x0e);
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default:
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nv_error(clk, "invalid clock source %d\n", src);
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nvkm_error(subdev, "invalid clock source %d\n", src);
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return -EINVAL;
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}
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}
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@ -188,7 +188,8 @@ static int
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gk104_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
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{
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struct gk104_clk *clk = container_of(obj, typeof(*clk), base);
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struct nvkm_device *device = clk->base.subdev.device;
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struct nvkm_subdev *subdev = &clk->base.subdev;
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struct nvkm_device *device = subdev->device;
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switch (src) {
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case nv_clk_src_crystal:
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@ -212,7 +213,7 @@ gk104_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
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case nv_clk_src_vdec:
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return read_clk(clk, 0x0e);
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default:
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nv_error(clk, "invalid clock source %d\n", src);
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nvkm_error(subdev, "invalid clock source %d\n", src);
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return -EINVAL;
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}
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}
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@ -151,6 +151,7 @@ gk20a_pllg_calc_rate(struct gk20a_clk *clk)
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static int
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gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate)
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{
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struct nvkm_subdev *subdev = &clk->base.subdev;
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u32 target_clk_f, ref_clk_f, target_freq;
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u32 min_vco_f, max_vco_f;
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u32 low_pl, high_pl, best_pl;
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@ -198,8 +199,8 @@ gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate)
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}
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}
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nv_debug(clk, "low_PL %d(div%d), high_PL %d(div%d)", low_pl,
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pl_to_div[low_pl], high_pl, pl_to_div[high_pl]);
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nvkm_debug(subdev, "low_PL %d(div%d), high_PL %d(div%d)", low_pl,
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pl_to_div[low_pl], high_pl, pl_to_div[high_pl]);
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/* Select lowest possible VCO */
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for (pl = low_pl; pl <= high_pl; pl++) {
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@ -249,8 +250,9 @@ gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate)
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WARN_ON(best_delta == ~0);
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if (best_delta != 0)
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nv_debug(clk, "no best match for target @ %dMHz on gpc_pll",
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target_clk_f);
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nvkm_debug(subdev,
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"no best match for target @ %dMHz on gpc_pll",
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target_clk_f);
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clk->m = best_m;
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clk->n = best_n;
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@ -258,15 +260,17 @@ gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate)
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target_freq = gk20a_pllg_calc_rate(clk) / MHZ;
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nv_debug(clk, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n",
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target_freq, clk->m, clk->n, clk->pl, pl_to_div[clk->pl]);
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nvkm_debug(subdev,
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"actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n",
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target_freq, clk->m, clk->n, clk->pl, pl_to_div[clk->pl]);
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return 0;
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}
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static int
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gk20a_pllg_slide(struct gk20a_clk *clk, u32 n)
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{
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struct nvkm_device *device = clk->base.subdev.device;
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struct nvkm_subdev *subdev = &clk->base.subdev;
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struct nvkm_device *device = subdev->device;
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u32 val;
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int ramp_timeout;
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@ -314,7 +318,7 @@ gk20a_pllg_slide(struct gk20a_clk *clk, u32 n)
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nvkm_rd32(device, GPCPLL_NDIV_SLOWDOWN);
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if (ramp_timeout <= 0) {
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nv_error(clk, "gpcpll dynamic ramp timeout\n");
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nvkm_error(subdev, "gpcpll dynamic ramp timeout\n");
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return -ETIMEDOUT;
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}
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@ -340,7 +344,8 @@ _gk20a_pllg_disable(struct gk20a_clk *clk)
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static int
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_gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide)
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{
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struct nvkm_device *device = clk->base.subdev.device;
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struct nvkm_subdev *subdev = &clk->base.subdev;
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struct nvkm_device *device = subdev->device;
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u32 val, cfg;
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u32 m_old, pl_old, n_lo;
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@ -387,8 +392,8 @@ _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide)
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_gk20a_pllg_disable(clk);
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nv_debug(clk, "%s: m=%d n=%d pl=%d\n", __func__, clk->m, clk->n,
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clk->pl);
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nvkm_debug(subdev, "%s: m=%d n=%d pl=%d\n", __func__,
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clk->m, clk->n, clk->pl);
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n_lo = DIV_ROUND_UP(clk->m * clk->params->min_vco,
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clk->parent_rate / MHZ);
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@ -567,7 +572,8 @@ static int
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gk20a_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
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{
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struct gk20a_clk *clk = container_of(obj, typeof(*clk), base);
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struct nvkm_device *device = clk->base.subdev.device;
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struct nvkm_subdev *subdev = &clk->base.subdev;
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struct nvkm_device *device = subdev->device;
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switch (src) {
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case nv_clk_src_crystal:
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@ -576,7 +582,7 @@ gk20a_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
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gk20a_pllg_read_mnp(clk);
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return gk20a_pllg_calc_rate(clk) / GK20A_CLK_GPC_MDIV;
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default:
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nv_error(clk, "invalid clock source %d\n", src);
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nvkm_error(subdev, "invalid clock source %d\n", src);
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return -EINVAL;
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}
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}
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@ -620,7 +626,8 @@ static int
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gk20a_clk_init(struct nvkm_object *object)
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{
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struct gk20a_clk *clk = (void *)object;
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struct nvkm_device *device = clk->base.subdev.device;
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struct nvkm_subdev *subdev = &clk->base.subdev;
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struct nvkm_device *device = subdev->device;
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int ret;
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nvkm_mask(device, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL);
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@ -631,7 +638,7 @@ gk20a_clk_init(struct nvkm_object *object)
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ret = gk20a_clk_prog(&clk->base);
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if (ret) {
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nv_error(clk, "cannot initialize clock\n");
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nvkm_error(subdev, "cannot initialize clock\n");
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return ret;
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}
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@ -665,7 +672,8 @@ gk20a_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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plat = nv_device_to_platform(nv_device(parent));
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clk->parent_rate = clk_get_rate(plat->gpu->clk);
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nv_info(clk, "parent clock rate: %d Mhz\n", clk->parent_rate / MHZ);
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nvkm_info(&clk->base.subdev, "parent clock rate: %d Mhz\n",
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clk->parent_rate / MHZ);
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clk->base.read = gk20a_clk_read;
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clk->base.calc = gk20a_clk_calc;
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@ -139,7 +139,8 @@ static int
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gt215_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
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{
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struct gt215_clk *clk = container_of(obj, typeof(*clk), base);
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struct nvkm_device *device = clk->base.subdev.device;
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struct nvkm_subdev *subdev = &clk->base.subdev;
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struct nvkm_device *device = subdev->device;
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u32 hsrc;
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switch (src) {
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@ -167,11 +168,11 @@ gt215_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
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case 3:
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return 277000;
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default:
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nv_error(clk, "unknown HOST clock source %d\n", hsrc);
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nvkm_error(subdev, "unknown HOST clock source %d\n", hsrc);
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return -EINVAL;
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}
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default:
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nv_error(clk, "invalid clock source %d\n", src);
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nvkm_error(subdev, "invalid clock source %d\n", src);
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return -EINVAL;
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}
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@ -80,7 +80,8 @@ static int
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mcp77_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
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{
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struct mcp77_clk *clk = container_of(obj, typeof(*clk), base);
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struct nvkm_device *device = clk->base.subdev.device;
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struct nvkm_subdev *subdev = &clk->base.subdev;
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struct nvkm_device *device = subdev->device;
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u32 mast = nvkm_rd32(device, 0x00c054);
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u32 P = 0;
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@ -155,7 +156,7 @@ mcp77_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
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break;
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}
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nv_debug(clk, "unknown clock source %d 0x%08x\n", src, mast);
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nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
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return 0;
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}
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@ -204,6 +205,7 @@ mcp77_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
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const int shader = cstate->domain[nv_clk_src_shader];
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const int core = cstate->domain[nv_clk_src_core];
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const int vdec = cstate->domain[nv_clk_src_vdec];
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struct nvkm_subdev *subdev = &clk->base.subdev;
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||||
u32 out = 0, clock = 0;
|
||||
int N, M, P1, P2 = 0;
|
||||
int divs = 0;
|
||||
|
|
@ -267,27 +269,27 @@ mcp77_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
|
|||
}
|
||||
|
||||
/* Print strategy! */
|
||||
nv_debug(clk, "nvpll: %08x %08x %08x\n",
|
||||
clk->ccoef, clk->cpost, clk->cctrl);
|
||||
nv_debug(clk, " spll: %08x %08x %08x\n",
|
||||
clk->scoef, clk->spost, clk->sctrl);
|
||||
nv_debug(clk, " vdiv: %08x\n", clk->vdiv);
|
||||
nvkm_debug(subdev, "nvpll: %08x %08x %08x\n",
|
||||
clk->ccoef, clk->cpost, clk->cctrl);
|
||||
nvkm_debug(subdev, " spll: %08x %08x %08x\n",
|
||||
clk->scoef, clk->spost, clk->sctrl);
|
||||
nvkm_debug(subdev, " vdiv: %08x\n", clk->vdiv);
|
||||
if (clk->csrc == nv_clk_src_hclkm4)
|
||||
nv_debug(clk, "core: hrefm4\n");
|
||||
nvkm_debug(subdev, "core: hrefm4\n");
|
||||
else
|
||||
nv_debug(clk, "core: nvpll\n");
|
||||
nvkm_debug(subdev, "core: nvpll\n");
|
||||
|
||||
if (clk->ssrc == nv_clk_src_hclkm4)
|
||||
nv_debug(clk, "shader: hrefm4\n");
|
||||
nvkm_debug(subdev, "shader: hrefm4\n");
|
||||
else if (clk->ssrc == nv_clk_src_core)
|
||||
nv_debug(clk, "shader: nvpll\n");
|
||||
nvkm_debug(subdev, "shader: nvpll\n");
|
||||
else
|
||||
nv_debug(clk, "shader: spll\n");
|
||||
nvkm_debug(subdev, "shader: spll\n");
|
||||
|
||||
if (clk->vsrc == nv_clk_src_hclkm4)
|
||||
nv_debug(clk, "vdec: 500MHz\n");
|
||||
nvkm_debug(subdev, "vdec: 500MHz\n");
|
||||
else
|
||||
nv_debug(clk, "vdec: core\n");
|
||||
nvkm_debug(subdev, "vdec: core\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -296,7 +298,8 @@ static int
|
|||
mcp77_clk_prog(struct nvkm_clk *obj)
|
||||
{
|
||||
struct mcp77_clk *clk = container_of(obj, typeof(*clk), base);
|
||||
struct nvkm_device *device = clk->base.subdev.device;
|
||||
struct nvkm_subdev *subdev = &clk->base.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
u32 pllmask = 0, mast;
|
||||
unsigned long flags;
|
||||
unsigned long *f = &flags;
|
||||
|
|
@ -324,7 +327,7 @@ mcp77_clk_prog(struct nvkm_clk *obj)
|
|||
mast |= 0x00000003;
|
||||
break;
|
||||
default:
|
||||
nv_warn(clk,"Reclocking failed: unknown core clock\n");
|
||||
nvkm_warn(subdev, "Reclocking failed: unknown core clock\n");
|
||||
goto resume;
|
||||
}
|
||||
|
||||
|
|
@ -345,7 +348,7 @@ mcp77_clk_prog(struct nvkm_clk *obj)
|
|||
mast |= 0x00000030;
|
||||
break;
|
||||
default:
|
||||
nv_warn(clk,"Reclocking failed: unknown sclk clock\n");
|
||||
nvkm_warn(subdev, "Reclocking failed: unknown sclk clock\n");
|
||||
goto resume;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -106,7 +106,8 @@ static int
|
|||
nv40_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
|
||||
{
|
||||
struct nv40_clk *clk = container_of(obj, typeof(*clk), base);
|
||||
struct nvkm_device *device = clk->base.subdev.device;
|
||||
struct nvkm_subdev *subdev = &clk->base.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
u32 mast = nvkm_rd32(device, 0x00c040);
|
||||
|
||||
switch (src) {
|
||||
|
|
@ -124,7 +125,7 @@ nv40_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
|
|||
break;
|
||||
}
|
||||
|
||||
nv_debug(clk, "unknown clock source %d 0x%08x\n", src, mast);
|
||||
nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -51,7 +51,8 @@ read_div(struct nv50_clk *clk)
|
|||
static u32
|
||||
read_pll_src(struct nv50_clk *clk, u32 base)
|
||||
{
|
||||
struct nvkm_device *device = clk->base.subdev.device;
|
||||
struct nvkm_subdev *subdev = &clk->base.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
u32 coef, ref = clk->base.read(&clk->base, nv_clk_src_crystal);
|
||||
u32 rsel = nvkm_rd32(device, 0x00e18c);
|
||||
int P, N, M, id;
|
||||
|
|
@ -65,7 +66,7 @@ read_pll_src(struct nv50_clk *clk, u32 base)
|
|||
case 0x4008: id = !!(rsel & 0x00000008); break;
|
||||
case 0x4030: id = 0; break;
|
||||
default:
|
||||
nv_error(clk, "ref: bad pll 0x%06x\n", base);
|
||||
nvkm_error(subdev, "ref: bad pll %06x\n", base);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -93,7 +94,7 @@ read_pll_src(struct nv50_clk *clk, u32 base)
|
|||
case 0x4028: rsel = (rsel & 0x00001800) >> 11; break;
|
||||
case 0x4030: rsel = 3; break;
|
||||
default:
|
||||
nv_error(clk, "ref: bad pll 0x%06x\n", base);
|
||||
nvkm_error(subdev, "ref: bad pll %06x\n", base);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -123,7 +124,8 @@ read_pll_src(struct nv50_clk *clk, u32 base)
|
|||
static u32
|
||||
read_pll_ref(struct nv50_clk *clk, u32 base)
|
||||
{
|
||||
struct nvkm_device *device = clk->base.subdev.device;
|
||||
struct nvkm_subdev *subdev = &clk->base.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
u32 src, mast = nvkm_rd32(device, 0x00c040);
|
||||
|
||||
switch (base) {
|
||||
|
|
@ -142,7 +144,7 @@ read_pll_ref(struct nv50_clk *clk, u32 base)
|
|||
case 0x00e810:
|
||||
return clk->base.read(&clk->base, nv_clk_src_crystal);
|
||||
default:
|
||||
nv_error(clk, "bad pll 0x%06x\n", base);
|
||||
nvkm_error(subdev, "bad pll %06x\n", base);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -190,7 +192,8 @@ static int
|
|||
nv50_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
|
||||
{
|
||||
struct nv50_clk *clk = container_of(obj, typeof(*clk), base);
|
||||
struct nvkm_device *device = clk->base.subdev.device;
|
||||
struct nvkm_subdev *subdev = &clk->base.subdev;
|
||||
struct nvkm_device *device = subdev->device;
|
||||
u32 mast = nvkm_rd32(device, 0x00c040);
|
||||
u32 P = 0;
|
||||
|
||||
|
|
@ -314,7 +317,7 @@ nv50_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
|
|||
break;
|
||||
}
|
||||
|
||||
nv_debug(clk, "unknown clock source %d 0x%08x\n", src, mast);
|
||||
nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -79,7 +79,7 @@ gt215_pll_calc(struct nvkm_subdev *subdev, struct nvbios_pll *info,
|
|||
}
|
||||
|
||||
if (unlikely(best_err == ~0)) {
|
||||
nv_error(subdev, "unable to find matching pll values\n");
|
||||
nvkm_error(subdev, "unable to find matching pll values\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -240,6 +240,6 @@ nv04_pll_calc(struct nvkm_subdev *subdev, struct nvbios_pll *info, u32 freq,
|
|||
}
|
||||
|
||||
if (!ret)
|
||||
nv_error(subdev, "unable to compute acceptable pll values\n");
|
||||
nvkm_error(subdev, "unable to compute acceptable pll values\n");
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue