pinctrl: cherryview: Pass irqchip when adding gpiochip
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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@ -149,6 +149,7 @@ struct chv_pin_context {
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* @chip: GPIO chip in this pin controller
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* @irqchip: IRQ chip in this pin controller
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* @regs: MMIO registers
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* @irq: Our parent irq
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* @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
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* offset (in GPIO number space)
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* @community: Community this pinctrl instance represents
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@ -165,6 +166,7 @@ struct chv_pinctrl {
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struct gpio_chip chip;
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struct irq_chip irqchip;
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void __iomem *regs;
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unsigned int irq;
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unsigned int intr_lines[16];
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const struct chv_community *community;
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u32 saved_intmask;
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@ -1617,26 +1619,8 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
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chip->add_pin_ranges = chv_gpio_add_pin_ranges;
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chip->parent = pctrl->dev;
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chip->base = -1;
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if (need_valid_mask)
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chip->irq.init_valid_mask = chv_init_irq_valid_mask;
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ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
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if (ret) {
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dev_err(pctrl->dev, "Failed to register gpiochip\n");
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return ret;
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}
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chv_gpio_irq_init_hw(chip);
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if (!need_valid_mask) {
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irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
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community->npins, NUMA_NO_NODE);
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if (irq_base < 0) {
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dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
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return irq_base;
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}
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}
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pctrl->irq = irq;
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pctrl->irqchip.name = "chv-gpio";
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pctrl->irqchip.irq_startup = chv_gpio_irq_startup;
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pctrl->irqchip.irq_ack = chv_gpio_irq_ack;
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@ -1645,10 +1629,27 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
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pctrl->irqchip.irq_set_type = chv_gpio_irq_type;
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pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;
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ret = gpiochip_irqchip_add(chip, &pctrl->irqchip, 0,
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handle_bad_irq, IRQ_TYPE_NONE);
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chip->irq.chip = &pctrl->irqchip;
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chip->irq.init_hw = chv_gpio_irq_init_hw;
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chip->irq.parent_handler = chv_gpio_irq_handler;
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chip->irq.num_parents = 1;
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chip->irq.parents = &pctrl->irq;
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chip->irq.default_type = IRQ_TYPE_NONE;
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chip->irq.handler = handle_bad_irq;
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if (need_valid_mask) {
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chip->irq.init_valid_mask = chv_init_irq_valid_mask;
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} else {
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irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
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community->npins, NUMA_NO_NODE);
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if (irq_base < 0) {
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dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
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return irq_base;
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}
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}
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ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
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if (ret) {
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dev_err(pctrl->dev, "failed to add IRQ chip\n");
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dev_err(pctrl->dev, "Failed to register gpiochip\n");
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return ret;
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}
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@ -1662,8 +1663,6 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
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}
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}
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gpiochip_set_chained_irqchip(chip, &pctrl->irqchip, irq,
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chv_gpio_irq_handler);
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return 0;
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}
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