Another round of 64-bit DT changes for the new Amlogic SoCs. These
include IR, SPI and ethernet MAC support for the new AXG family SoCs. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAlpQC6wACgkQWTcYmtP7 xmVazBAAh/riNhKvUEoHCa1TQ8f0ELfGkZ7ckOBtTEBE9DoQQXZ08jU+LwEEy1N3 /5Uby3lquAYZiJzMuXfaJ63V+07OzIDt9hYzFBToMPf2ZLxSyGS8ZTWsUveBRXep tAY8ETtK8u3tq1pQH0A5lGc84yR8MM74We91GwuCA4S6whYqVbO1dInSb0mVqX50 vVKChc+jUgXwy4zaazgSUKcjZmexSCF7zA9ZXnGM3wg3s4K3HhzLZwCm30GU30mC Of5uCT02cR+HkRC1fDfo3mY9oRr19krYz9hJIsMk3mnmQS0XeI+HJ1DX+5K8l4YP 2ayVueBCLvqG7a1T4MLV6Hb7B1//Ejz6dT6UfTSSQszKXA3FQKIER7vt4Hg9IcCW rH5hXnPCko5yfjMpym3yr4+97fi6U1iJccc+DYRs0dq1Wrth40BwZH6tCrQVHfOQ jY6c2Ha5GDPTHbsW39vb7JvsFGYN2wlmmC1ThqG4e9kF8l1ZW+m433dJOicWMk2m 55SqCkbmkboVy9bYC6Tgrx6/KAa6vqMK0oXHADSJgNeccEZZeiTttlVwAiF9b1/f 1umUwKSfRhAvtvHD+ynoZIQ64oEnWGeGyc5EEJIdY+q7T6csT2E+pi75+y4q6jI2 xMTuK5iwXNr7PF612Tmr5NMaB+59Abdshp9IXxsNDPJiNBTLagA= =lk2H -----END PGP SIGNATURE----- Merge tag 'amlogic-dt64-3' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt Another round of 64-bit DT changes for the new Amlogic SoCs. These include IR, SPI and ethernet MAC support for the new AXG family SoCs. * tag 'amlogic-dt64-3' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM64: dts: meson-axg: enable ethernet for A113D S400 board ARM64: dts: meson-axg: add ethernet mac controller ARM64: dts: meson-axg: add the SPICC controller ARM64: dts: meson-axg: enable IR controller arm64: dts: meson-axg: switch uart_ao clock to CLK81 clk: meson-axg: add clocks dt-bindings required header dt-bindings: clock: add compatible variant for the Meson-AXG Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
ba05173afe
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@ -5,8 +5,11 @@ controllers within the SoC.
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Required Properties:
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- compatible: should be "amlogic,gxbb-clkc" for GXBB SoC,
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or "amlogic,gxl-clkc" for GXL and GXM SoC.
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- compatible: should be:
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"amlogic,gxbb-clkc" for GXBB SoC,
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"amlogic,gxl-clkc" for GXL and GXM SoC,
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"amlogic,axg-clkc" for AXG SoC.
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- reg: physical base address of the clock controller and length of memory
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mapped region.
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@ -17,6 +17,19 @@ aliases {
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};
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};
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ðmac {
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status = "okay";
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phy-mode = "rgmii";
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pinctrl-0 = <ð_rgmii_y_pins>;
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pinctrl-names = "default";
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};
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&uart_AO {
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status = "okay";
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};
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&ir {
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status = "okay";
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pinctrl-0 = <&remote_input_ao_pins>;
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pinctrl-names = "default";
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};
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@ -7,6 +7,7 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/axg-clkc.h>
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/ {
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compatible = "amlogic,meson-axg";
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@ -140,6 +141,28 @@ reset: reset-controller@1004 {
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#reset-cells = <1>;
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};
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spicc0: spi@13000 {
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compatible = "amlogic,meson-axg-spicc";
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reg = <0x0 0x13000 0x0 0x3c>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkc CLKID_SPICC0>;
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clock-names = "core";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spicc1: spi@15000 {
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compatible = "amlogic,meson-axg-spicc";
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reg = <0x0 0x15000 0x0 0x3c>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkc CLKID_SPICC1>;
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clock-names = "core";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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uart_A: serial@24000 {
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compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
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reg = <0x0 0x24000 0x0 0x14>;
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@ -155,6 +178,19 @@ uart_B: serial@23000 {
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};
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};
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ethmac: ethernet@ff3f0000 {
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compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
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reg = <0x0 0xff3f0000 0x0 0x10000
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0x0 0xff634540 0x0 0x8>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "macirq";
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clocks = <&clkc CLKID_ETH>,
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<&clkc CLKID_FCLK_DIV2>,
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<&clkc CLKID_MPLL2>;
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clock-names = "stmmaceth", "clkin0", "clkin1";
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status = "disabled";
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};
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gic: interrupt-controller@ffc01000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xffc01000 0 0x1000>,
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@ -215,6 +251,46 @@ gpio: bank@480 {
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gpio-ranges = <&pinctrl_periphs 0 0 86>;
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};
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eth_rgmii_x_pins: eth-x-rgmii {
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mux {
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groups = "eth_mdio_x",
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"eth_mdc_x",
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"eth_rgmii_rx_clk_x",
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"eth_rx_dv_x",
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"eth_rxd0_x",
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"eth_rxd1_x",
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"eth_rxd2_rgmii",
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"eth_rxd3_rgmii",
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"eth_rgmii_tx_clk",
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"eth_txen_x",
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"eth_txd0_x",
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"eth_txd1_x",
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"eth_txd2_rgmii",
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"eth_txd3_rgmii";
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function = "eth";
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};
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};
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eth_rgmii_y_pins: eth-y-rgmii {
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mux {
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groups = "eth_mdio_y",
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"eth_mdc_y",
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"eth_rgmii_rx_clk_y",
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"eth_rx_dv_y",
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"eth_rxd0_y",
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"eth_rxd1_y",
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"eth_rxd2_rgmii",
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"eth_rxd3_rgmii",
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"eth_rgmii_tx_clk",
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"eth_txen_y",
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"eth_txd0_y",
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"eth_txd1_y",
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"eth_txd2_rgmii",
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"eth_txd3_rgmii";
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function = "eth";
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};
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};
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pwm_a_a_pins: pwm_a_a {
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mux {
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groups = "pwm_a_a";
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@ -298,6 +374,76 @@ mux {
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function = "pwm_d";
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};
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};
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spi0_pins: spi0 {
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mux {
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groups = "spi0_miso",
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"spi0_mosi",
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"spi0_clk";
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function = "spi0";
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};
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};
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spi0_ss0_pins: spi0_ss0 {
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mux {
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groups = "spi0_ss0";
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function = "spi0";
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};
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};
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spi0_ss1_pins: spi0_ss1 {
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mux {
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groups = "spi0_ss1";
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function = "spi0";
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};
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};
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spi0_ss2_pins: spi0_ss2 {
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mux {
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groups = "spi0_ss2";
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function = "spi0";
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};
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};
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spi1_a_pins: spi1_a {
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mux {
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groups = "spi1_miso_a",
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"spi1_mosi_a",
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"spi1_clk_a";
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function = "spi1";
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};
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};
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spi1_ss0_a_pins: spi1_ss0_a {
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mux {
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groups = "spi1_ss0_a";
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function = "spi1";
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};
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};
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spi1_ss1_pins: spi1_ss1 {
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mux {
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groups = "spi1_ss1";
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function = "spi1";
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};
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};
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spi1_x_pins: spi1_x {
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mux {
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groups = "spi1_miso_x",
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"spi1_mosi_x",
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"spi1_clk_x";
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function = "spi1";
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};
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};
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spi1_ss0_x_pins: spi1_ss0_x {
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mux {
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groups = "spi1_ss0_x";
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function = "spi1";
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};
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};
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};
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};
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@ -341,6 +487,13 @@ gpio_ao: bank@14 {
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_aobus 0 0 15>;
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};
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remote_input_ao_pins: remote_input_ao {
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mux {
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groups = "remote_input_ao";
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function = "remote_input_ao";
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};
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};
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};
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pwm_AO_ab: pwm@7000 {
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@ -361,7 +514,7 @@ uart_AO: serial@3000 {
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compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
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reg = <0x0 0x3000 0x0 0x18>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>, <&xtal>, <&xtal>;
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clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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status = "disabled";
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};
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@ -370,10 +523,17 @@ uart_AO_B: serial@4000 {
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compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
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reg = <0x0 0x4000 0x0 0x18>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>, <&xtal>, <&xtal>;
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clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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status = "disabled";
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};
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ir: ir@8000 {
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compatible = "amlogic,meson-gxbb-ir";
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reg = <0x0 0x8000 0x0 0x20>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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};
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};
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};
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@ -0,0 +1,71 @@
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/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Meson-AXG clock tree IDs
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*
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* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __AXG_CLKC_H
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#define __AXG_CLKC_H
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#define CLKID_SYS_PLL 0
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#define CLKID_FIXED_PLL 1
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#define CLKID_FCLK_DIV2 2
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#define CLKID_FCLK_DIV3 3
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#define CLKID_FCLK_DIV4 4
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#define CLKID_FCLK_DIV5 5
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#define CLKID_FCLK_DIV7 6
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#define CLKID_GP0_PLL 7
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#define CLKID_CLK81 10
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#define CLKID_MPLL0 11
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#define CLKID_MPLL1 12
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#define CLKID_MPLL2 13
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#define CLKID_MPLL3 14
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#define CLKID_DDR 15
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#define CLKID_AUDIO_LOCKER 16
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#define CLKID_MIPI_DSI_HOST 17
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#define CLKID_ISA 18
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#define CLKID_PL301 19
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#define CLKID_PERIPHS 20
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#define CLKID_SPICC0 21
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#define CLKID_I2C 22
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#define CLKID_RNG0 23
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#define CLKID_UART0 24
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#define CLKID_MIPI_DSI_PHY 25
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#define CLKID_SPICC1 26
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#define CLKID_PCIE_A 27
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#define CLKID_PCIE_B 28
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#define CLKID_HIU_IFACE 29
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#define CLKID_ASSIST_MISC 30
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#define CLKID_SD_EMMC_B 31
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#define CLKID_SD_EMMC_C 32
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#define CLKID_DMA 33
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#define CLKID_SPI 34
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#define CLKID_AUDIO 35
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#define CLKID_ETH 36
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#define CLKID_UART1 37
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#define CLKID_G2D 38
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#define CLKID_USB0 39
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#define CLKID_USB1 40
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#define CLKID_RESET 41
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#define CLKID_USB 42
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#define CLKID_AHB_ARB0 43
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#define CLKID_EFUSE 44
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#define CLKID_BOOT_ROM 45
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#define CLKID_AHB_DATA_BUS 46
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#define CLKID_AHB_CTRL_BUS 47
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#define CLKID_USB1_DDR_BRIDGE 48
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#define CLKID_USB0_DDR_BRIDGE 49
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#define CLKID_MMC_PCLK 50
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#define CLKID_VPU_INTR 51
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#define CLKID_SEC_AHB_AHB3_BRIDGE 52
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#define CLKID_GIC 53
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#define CLKID_AO_MEDIA_CPU 54
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#define CLKID_AO_AHB_SRAM 55
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#define CLKID_AO_AHB_BUS 56
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#define CLKID_AO_IFACE 57
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#define CLKID_AO_I2C 58
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#define CLKID_SD_EMMC_B_CLK0 59
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#define CLKID_SD_EMMC_C_CLK0 60
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#endif /* __AXG_CLKC_H */
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