perf/x86/intel: Factor out common code of PMI handler
The Arch Perfmon v4 PMI handler is substantially different than the older PMI handler. Instead of adding more and more ifs cleanly fork the new handler into a new function, with the main common code factored out into a common function. Fix complaint from checkpatch.pl by removing "false" from "static bool warned". No functional change. Based-on-code-from: Andi Kleen <ak@linux.intel.com> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: acme@kernel.org Link: http://lkml.kernel.org/r/1533712328-2834-1-git-send-email-kan.liang@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -2200,59 +2200,15 @@ static void intel_pmu_reset(void)
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local_irq_restore(flags);
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}
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/*
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* This handler is triggered by the local APIC, so the APIC IRQ handling
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* rules apply:
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*/
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static int intel_pmu_handle_irq(struct pt_regs *regs)
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static int handle_pmi_common(struct pt_regs *regs, u64 status)
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{
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struct perf_sample_data data;
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struct cpu_hw_events *cpuc;
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int bit, loops;
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u64 status;
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int handled;
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int pmu_enabled;
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cpuc = this_cpu_ptr(&cpu_hw_events);
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/*
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* Save the PMU state.
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* It needs to be restored when leaving the handler.
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*/
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pmu_enabled = cpuc->enabled;
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/*
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* No known reason to not always do late ACK,
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* but just in case do it opt-in.
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*/
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if (!x86_pmu.late_ack)
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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intel_bts_disable_local();
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cpuc->enabled = 0;
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__intel_pmu_disable_all();
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handled = intel_pmu_drain_bts_buffer();
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handled += intel_bts_interrupt();
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status = intel_pmu_get_status();
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if (!status)
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goto done;
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loops = 0;
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again:
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intel_pmu_lbr_read();
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intel_pmu_ack_status(status);
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if (++loops > 100) {
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static bool warned = false;
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if (!warned) {
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WARN(1, "perfevents: irq loop stuck!\n");
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perf_event_print_debug();
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warned = true;
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}
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intel_pmu_reset();
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goto done;
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}
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struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
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int bit;
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int handled = 0;
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inc_irq_stat(apic_perf_irqs);
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/*
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* Ignore a range of extra bits in status that do not indicate
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* overflow by themselves.
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@ -2261,7 +2217,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
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GLOBAL_STATUS_ASIF |
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GLOBAL_STATUS_LBRS_FROZEN);
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if (!status)
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goto done;
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return 0;
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/*
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* In case multiple PEBS events are sampled at the same time,
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* it is possible to have GLOBAL_STATUS bit 62 set indicating
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@ -2331,6 +2287,61 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
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x86_pmu_stop(event, 0);
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}
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return handled;
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}
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/*
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* This handler is triggered by the local APIC, so the APIC IRQ handling
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* rules apply:
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*/
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static int intel_pmu_handle_irq(struct pt_regs *regs)
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{
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struct cpu_hw_events *cpuc;
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int loops;
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u64 status;
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int handled;
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int pmu_enabled;
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cpuc = this_cpu_ptr(&cpu_hw_events);
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/*
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* Save the PMU state.
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* It needs to be restored when leaving the handler.
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*/
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pmu_enabled = cpuc->enabled;
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/*
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* No known reason to not always do late ACK,
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* but just in case do it opt-in.
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*/
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if (!x86_pmu.late_ack)
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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intel_bts_disable_local();
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cpuc->enabled = 0;
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__intel_pmu_disable_all();
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handled = intel_pmu_drain_bts_buffer();
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handled += intel_bts_interrupt();
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status = intel_pmu_get_status();
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if (!status)
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goto done;
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loops = 0;
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again:
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intel_pmu_lbr_read();
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intel_pmu_ack_status(status);
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if (++loops > 100) {
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static bool warned;
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if (!warned) {
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WARN(1, "perfevents: irq loop stuck!\n");
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perf_event_print_debug();
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warned = true;
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}
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intel_pmu_reset();
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goto done;
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}
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handled += handle_pmi_common(regs, status);
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/*
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* Repeat if there is more work to be done:
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*/
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