net: stmmac: dwmac-rk: add rk3366 & rk3399 specific data
Add constants and callback functions for the dwmac on rk3228/rk3229 socs. As can be seen, the base structure is the same, only registers and the bits in them moved slightly. Signed-off-by: Roger Chen <roger.chen@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Roger Chen
David S. Miller
parent
dd19bde367
commit
ba289af802
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@ -3,8 +3,12 @@ Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC)
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The device node has following properties.
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Required properties:
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- compatible: Can be one of "rockchip,rk3228-gmac", "rockchip,rk3288-gmac",
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"rockchip,rk3368-gmac"
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- compatible: should be "rockchip,<name>-gamc"
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"rockchip,rk3228-gmac": found on RK322x SoCs
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"rockchip,rk3288-gmac": found on RK3288 SoCs
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"rockchip,rk3366-gmac": found on RK3366 SoCs
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"rockchip,rk3368-gmac": found on RK3368 SoCs
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"rockchip,rk3399-gmac": found on RK3399 SoCs
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- reg: addresses and length of the register sets for the device.
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- interrupts: Should contain the GMAC interrupts.
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- interrupt-names: Should contain the interrupt names "macirq".
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@ -301,6 +301,118 @@ static const struct rk_gmac_ops rk3288_ops = {
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.set_rmii_speed = rk3288_set_rmii_speed,
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};
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#define RK3366_GRF_SOC_CON6 0x0418
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#define RK3366_GRF_SOC_CON7 0x041c
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/* RK3366_GRF_SOC_CON6 */
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#define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
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GRF_CLR_BIT(11))
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#define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
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GRF_BIT(11))
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#define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
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#define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
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#define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
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#define RK3366_GMAC_SPEED_100M GRF_BIT(7)
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#define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
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#define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
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#define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
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#define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
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#define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
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#define RK3366_GMAC_RMII_MODE GRF_BIT(6)
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#define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
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/* RK3366_GRF_SOC_CON7 */
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#define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
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#define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
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#define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
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#define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
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#define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
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#define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
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static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
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int tx_delay, int rx_delay)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
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return;
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}
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regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
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RK3366_GMAC_PHY_INTF_SEL_RGMII |
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RK3366_GMAC_RMII_MODE_CLR);
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regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
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RK3366_GMAC_RXCLK_DLY_ENABLE |
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RK3366_GMAC_TXCLK_DLY_ENABLE |
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RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
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RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
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}
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static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
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return;
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}
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regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
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RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
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}
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static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
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return;
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}
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if (speed == 10)
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regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
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RK3366_GMAC_CLK_2_5M);
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else if (speed == 100)
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regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
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RK3366_GMAC_CLK_25M);
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else if (speed == 1000)
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regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
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RK3366_GMAC_CLK_125M);
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else
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dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
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}
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static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
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return;
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}
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if (speed == 10) {
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regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
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RK3366_GMAC_RMII_CLK_2_5M |
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RK3366_GMAC_SPEED_10M);
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} else if (speed == 100) {
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regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
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RK3366_GMAC_RMII_CLK_25M |
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RK3366_GMAC_SPEED_100M);
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} else {
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dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
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}
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}
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static const struct rk_gmac_ops rk3366_ops = {
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.set_to_rgmii = rk3366_set_to_rgmii,
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.set_to_rmii = rk3366_set_to_rmii,
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.set_rgmii_speed = rk3366_set_rgmii_speed,
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.set_rmii_speed = rk3366_set_rmii_speed,
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};
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#define RK3368_GRF_SOC_CON15 0x043c
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#define RK3368_GRF_SOC_CON16 0x0440
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@ -413,6 +525,118 @@ static const struct rk_gmac_ops rk3368_ops = {
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.set_rmii_speed = rk3368_set_rmii_speed,
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};
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#define RK3399_GRF_SOC_CON5 0xc214
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#define RK3399_GRF_SOC_CON6 0xc218
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/* RK3399_GRF_SOC_CON5 */
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#define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
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GRF_CLR_BIT(11))
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#define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
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GRF_BIT(11))
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#define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
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#define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
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#define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
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#define RK3399_GMAC_SPEED_100M GRF_BIT(7)
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#define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
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#define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
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#define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
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#define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
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#define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
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#define RK3399_GMAC_RMII_MODE GRF_BIT(6)
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#define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
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/* RK3399_GRF_SOC_CON6 */
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#define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
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#define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
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#define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
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#define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
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#define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
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#define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
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static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
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int tx_delay, int rx_delay)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
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return;
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}
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regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
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RK3399_GMAC_PHY_INTF_SEL_RGMII |
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RK3399_GMAC_RMII_MODE_CLR);
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regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
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RK3399_GMAC_RXCLK_DLY_ENABLE |
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RK3399_GMAC_TXCLK_DLY_ENABLE |
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RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
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RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
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}
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static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
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return;
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}
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regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
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RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
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}
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static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
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return;
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}
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if (speed == 10)
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regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
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RK3399_GMAC_CLK_2_5M);
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else if (speed == 100)
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regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
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RK3399_GMAC_CLK_25M);
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else if (speed == 1000)
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regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
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RK3399_GMAC_CLK_125M);
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else
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dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
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}
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static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
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return;
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}
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if (speed == 10) {
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regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
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RK3399_GMAC_RMII_CLK_2_5M |
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RK3399_GMAC_SPEED_10M);
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} else if (speed == 100) {
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regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
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RK3399_GMAC_RMII_CLK_25M |
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RK3399_GMAC_SPEED_100M);
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} else {
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dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
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}
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}
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static const struct rk_gmac_ops rk3399_ops = {
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.set_to_rgmii = rk3399_set_to_rgmii,
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.set_to_rmii = rk3399_set_to_rmii,
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.set_rgmii_speed = rk3399_set_rgmii_speed,
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.set_rmii_speed = rk3399_set_rmii_speed,
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};
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static int gmac_clk_init(struct rk_priv_data *bsp_priv)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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@ -760,7 +984,9 @@ static int rk_gmac_probe(struct platform_device *pdev)
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static const struct of_device_id rk_gmac_dwmac_match[] = {
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{ .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
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{ .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
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{ .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
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{ .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
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{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
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{ }
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};
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MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
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