From 396a3529800af0817c6af2eb65c542588a1f7fb7 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 19 Sep 2016 10:43:17 +0200 Subject: [PATCH 01/29] pinctrl: bcm2835: add pull defines to dt bindings Also delete (unused) private enum from driver. The pull defines can be used instead if needed. Signed-off-by: Gerd Hoffmann Signed-off-by: Eric Anholt Acked-by: Linus Walleij Acked-by: Stefan Wahren --- drivers/pinctrl/bcm/pinctrl-bcm2835.c | 6 ------ include/dt-bindings/pinctrl/bcm2835.h | 5 +++++ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index fa77165fab2c..4cf612bcfdfa 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -76,12 +76,6 @@ enum bcm2835_pinconf_param { BCM2835_PINCONF_PARAM_PULL, }; -enum bcm2835_pinconf_pull { - BCM2835_PINCONFIG_PULL_NONE, - BCM2835_PINCONFIG_PULL_DOWN, - BCM2835_PINCONFIG_PULL_UP, -}; - #define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_)) #define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16) #define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff) diff --git a/include/dt-bindings/pinctrl/bcm2835.h b/include/dt-bindings/pinctrl/bcm2835.h index 6f0bc37af39c..e4e4fdf5d38f 100644 --- a/include/dt-bindings/pinctrl/bcm2835.h +++ b/include/dt-bindings/pinctrl/bcm2835.h @@ -24,4 +24,9 @@ #define BCM2835_FSEL_ALT2 6 #define BCM2835_FSEL_ALT3 7 +/* brcm,pull property */ +#define BCM2835_PUD_OFF 0 +#define BCM2835_PUD_DOWN 1 +#define BCM2835_PUD_UP 2 + #endif /* __DT_BINDINGS_PINCTRL_BCM2835_H__ */ From 21ff843931b2e5a9b628ac56fd0f2e4355890096 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 19 Sep 2016 10:43:18 +0200 Subject: [PATCH 02/29] ARM: dts: bcm283x: Define standard pinctrl groups in the gpio node. The BCM2835-ARM-Peripherals.pdf documentation specifies what the function selects do for the pins, and there are a bunch of obvious groupings to be made. With these created, we'll be able to replace bcm2835-rpi.dtsi's main "set all of these pins to alt0" with references to specific groups we want enabled. Also add pinctrl groups for emmc and sdhost. Based on patches by Eric Anholt, with fixups by Gerd Hoffmann. Signed-off-by: Gerd Hoffmann Signed-off-by: Eric Anholt Acked-by: Stefan Wahren --- arch/arm/boot/dts/bcm283x.dtsi | 203 +++++++++++++++++++++++++++++++++ 1 file changed, 203 insertions(+) diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index 46d46d894a44..2123d0eb1890 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -132,6 +132,209 @@ gpio: gpio@7e200000 { interrupt-controller; #interrupt-cells = <2>; + + /* Defines pin muxing groups according to + * BCM2835-ARM-Peripherals.pdf page 102. + * + * While each pin can have its mux selected + * for various functions individually, some + * groups only make sense to switch to a + * particular function together. + */ + dpi_gpio0: dpi_gpio0 { + brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 + 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27>; + brcm,function = ; + }; + emmc_gpio22: emmc_gpio22 { + brcm,pins = <22 23 24 25 26 27>; + brcm,function = ; + }; + emmc_gpio34: emmc_gpio34 { + brcm,pins = <34 35 36 37 38 39>; + brcm,function = ; + brcm,pull = ; + }; + emmc_gpio48: emmc_gpio48 { + brcm,pins = <48 49 50 51 52 53>; + brcm,function = ; + }; + + gpclk0_gpio4: gpclk0_gpio4 { + brcm,pins = <4>; + brcm,function = ; + }; + gpclk1_gpio5: gpclk1_gpio5 { + brcm,pins = <5>; + brcm,function = ; + }; + gpclk1_gpio42: gpclk1_gpio42 { + brcm,pins = <42>; + brcm,function = ; + }; + gpclk1_gpio44: gpclk1_gpio44 { + brcm,pins = <44>; + brcm,function = ; + }; + gpclk2_gpio6: gpclk2_gpio6 { + brcm,pins = <6>; + brcm,function = ; + }; + gpclk2_gpio43: gpclk2_gpio43 { + brcm,pins = <43>; + brcm,function = ; + }; + + i2c0_gpio0: i2c0_gpio0 { + brcm,pins = <0 1>; + brcm,function = ; + }; + i2c0_gpio32: i2c0_gpio32 { + brcm,pins = <32 34>; + brcm,function = ; + }; + i2c0_gpio44: i2c0_gpio44 { + brcm,pins = <44 45>; + brcm,function = ; + }; + i2c1_gpio2: i2c1_gpio2 { + brcm,pins = <2 3>; + brcm,function = ; + }; + i2c1_gpio44: i2c1_gpio44 { + brcm,pins = <44 45>; + brcm,function = ; + }; + i2c_slave_gpio18: i2c_slave_gpio18 { + brcm,pins = <18 19 20 21>; + brcm,function = ; + }; + + jtag_gpio4: jtag_gpio4 { + brcm,pins = <4 5 6 12 13>; + brcm,function = ; + }; + jtag_gpio22: jtag_gpio22 { + brcm,pins = <22 23 24 25 26 27>; + brcm,function = ; + }; + + pcm_gpio18: pcm_gpio18 { + brcm,pins = <18 19 20 21>; + brcm,function = ; + }; + pcm_gpio28: pcm_gpio28 { + brcm,pins = <28 29 30 31>; + brcm,function = ; + }; + + pwm0_gpio12: pwm0_gpio12 { + brcm,pins = <12>; + brcm,function = ; + }; + pwm0_gpio18: pwm0_gpio18 { + brcm,pins = <18>; + brcm,function = ; + }; + pwm0_gpio40: pwm0_gpio40 { + brcm,pins = <40>; + brcm,function = ; + }; + pwm1_gpio13: pwm1_gpio13 { + brcm,pins = <13>; + brcm,function = ; + }; + pwm1_gpio19: pwm1_gpio19 { + brcm,pins = <19>; + brcm,function = ; + }; + pwm1_gpio41: pwm1_gpio41 { + brcm,pins = <41>; + brcm,function = ; + }; + pwm1_gpio45: pwm1_gpio45 { + brcm,pins = <45>; + brcm,function = ; + }; + + sdhost_gpio48: sdhost_gpio48 { + brcm,pins = <48 49 50 51 52 53>; + brcm,function = ; + }; + + spi0_gpio7: spi0_gpio7 { + brcm,pins = <7 8 9 10 11>; + brcm,function = ; + }; + spi0_gpio35: spi0_gpio35 { + brcm,pins = <35 36 37 38 39>; + brcm,function = ; + }; + spi1_gpio16: spi1_gpio16 { + brcm,pins = <16 17 18 19 20 21>; + brcm,function = ; + }; + spi2_gpio40: spi2_gpio40 { + brcm,pins = <40 41 42 43 44 45>; + brcm,function = ; + }; + + uart0_gpio14: uart0_gpio14 { + brcm,pins = <14 15>; + brcm,function = ; + }; + /* Separate from the uart0_gpio14 group + * because it conflicts with spi1_gpio16, and + * people often run uart0 on the two pins + * without flow contrl. + */ + uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 { + brcm,pins = <16 17>; + brcm,function = ; + }; + uart0_gpio30: uart0_gpio30 { + brcm,pins = <30 31>; + brcm,function = ; + }; + uart0_ctsrts_gpio32: uart0_ctsrts_gpio32 { + brcm,pins = <32 33>; + brcm,function = ; + }; + + uart1_gpio14: uart1_gpio14 { + brcm,pins = <14 15>; + brcm,function = ; + }; + uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 { + brcm,pins = <16 17>; + brcm,function = ; + }; + uart1_gpio32: uart1_gpio32 { + brcm,pins = <32 33>; + brcm,function = ; + }; + uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 { + brcm,pins = <30 31>; + brcm,function = ; + }; + uart1_gpio36: uart1_gpio36 { + brcm,pins = <36 37 38 39>; + brcm,function = ; + }; + uart1_gpio40: uart1_gpio40 { + brcm,pins = <40 41>; + brcm,function = ; + }; + uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 { + brcm,pins = <42 43>; + brcm,function = ; + }; }; uart0: serial@7e201000 { From 14e0ea34058ce13794877206f05a6ab5034e147b Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 19 Sep 2016 10:43:19 +0200 Subject: [PATCH 03/29] ARM: dts: bcm283x: add pinctrl group to &pwm, drop pins from &gpio Signed-off-by: Gerd Hoffmann Signed-off-by: Eric Anholt Acked-by: Stefan Wahren --- arch/arm/boot/dts/bcm2835-rpi.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index e9b47b2bbc33..5663772fc460 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -39,7 +39,7 @@ gpioout: gpioout { }; alt0: alt0 { - brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>; + brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15>; brcm,function = ; }; @@ -69,6 +69,8 @@ &sdhci { }; &pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; status = "okay"; }; From e6e199712008374edb4de979e74ae5acb1f40845 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 19 Sep 2016 10:43:20 +0200 Subject: [PATCH 04/29] ARM: dts: bcm283x: add pinctrl group to &i2c0, drop pins from &gpio Signed-off-by: Gerd Hoffmann Signed-off-by: Eric Anholt Acked-by: Stefan Wahren --- arch/arm/boot/dts/bcm2835-rpi.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index 5663772fc460..096891fd7047 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -39,7 +39,7 @@ gpioout: gpioout { }; alt0: alt0 { - brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15>; + brcm,pins = <2 3 4 5 7 8 9 10 11 14 15>; brcm,function = ; }; @@ -50,6 +50,8 @@ alt3: alt3 { }; &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_gpio0>; status = "okay"; clock-frequency = <100000>; }; From 4eb65cbfa721db9d7bbe2f76e8b1909fa0320273 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 19 Sep 2016 10:43:21 +0200 Subject: [PATCH 05/29] ARM: dts: bcm283x: add pinctrl group to &i2c1, drop pins from &gpio Signed-off-by: Gerd Hoffmann Signed-off-by: Eric Anholt --- arch/arm/boot/dts/bcm2835-rpi.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index 096891fd7047..8b3ff38cc4ba 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -39,7 +39,7 @@ gpioout: gpioout { }; alt0: alt0 { - brcm,pins = <2 3 4 5 7 8 9 10 11 14 15>; + brcm,pins = <4 5 7 8 9 10 11 14 15>; brcm,function = ; }; @@ -57,6 +57,8 @@ &i2c0 { }; &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_gpio2>; status = "okay"; clock-frequency = <100000>; }; From f8bef3619bb219ed27dfe11cd20547e5b709650a Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 19 Sep 2016 10:43:22 +0200 Subject: [PATCH 06/29] ARM: dts: bcm283x: add pinctrl group to &sdhci, drop pins from &gpio Signed-off-by: Gerd Hoffmann Signed-off-by: Eric Anholt Acked-by: Stefan Wahren --- arch/arm/boot/dts/bcm2835-rpi.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index 8b3ff38cc4ba..7c63e667425f 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -44,7 +44,7 @@ alt0: alt0 { }; alt3: alt3 { - brcm,pins = <48 49 50 51 52 53>; + brcm,pins = <>; brcm,function = ; }; }; @@ -68,6 +68,8 @@ &i2c2 { }; &sdhci { + pinctrl-names = "default"; + pinctrl-0 = <&emmc_gpio48>; status = "okay"; bus-width = <4>; }; From a6d962aeb22fbf73c023334bdf55dc45c9fd7dba Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 19 Sep 2016 10:43:23 +0200 Subject: [PATCH 07/29] ARM: dts: bcm283x: drop alt3 from &gpio As the alt3 group has no pins left drop it from &gpio. Signed-off-by: Gerd Hoffmann Signed-off-by: Eric Anholt Acked-by: Stefan Wahren --- arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 2 +- arch/arm/boot/dts/bcm2835-rpi-a.dts | 2 +- arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 2 +- arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts | 2 +- arch/arm/boot/dts/bcm2835-rpi-b.dts | 2 +- arch/arm/boot/dts/bcm2835-rpi-zero.dts | 2 +- arch/arm/boot/dts/bcm2835-rpi.dtsi | 5 ----- arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 2 +- 8 files changed, 7 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts index f7f9db355d98..21507c922783 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts @@ -22,7 +22,7 @@ pwr { }; &gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; /* I2S interface */ i2s_alt0: i2s_alt0 { diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts index 8be102f5d826..5afba0900449 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts @@ -15,7 +15,7 @@ act { }; &gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>; + pinctrl-0 = <&gpioout &alt0 &i2s_alt2>; /* I2S interface */ i2s_alt2: i2s_alt2 { diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index 35cde65c975e..38f66aa244fe 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -23,7 +23,7 @@ pwr { }; &gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; /* I2S interface */ i2s_alt0: i2s_alt0 { diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts index 84df85ea6296..75e045aba7ce 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts @@ -16,7 +16,7 @@ act { }; &gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>; + pinctrl-0 = <&gpioout &alt0 &i2s_alt2>; /* I2S interface */ i2s_alt2: i2s_alt2 { diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index 8e626a80fe24..76a254b3219a 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -16,7 +16,7 @@ act { }; &gpio { - pinctrl-0 = <&gpioout &alt0 &alt3>; + pinctrl-0 = <&gpioout &alt0>; }; &hdmi { diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts index 60e359fafc5b..7c1c18048948 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts @@ -26,7 +26,7 @@ act { }; &gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; /* I2S interface */ i2s_alt0: i2s_alt0 { diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index 7c63e667425f..6ddf7dfe3f72 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -42,11 +42,6 @@ alt0: alt0 { brcm,pins = <4 5 7 8 9 10 11 14 15>; brcm,function = ; }; - - alt3: alt3 { - brcm,pins = <>; - brcm,function = ; - }; }; &i2c0 { diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index 39dccf62ac96..bf19e8cfb9e6 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -27,7 +27,7 @@ pwr { }; &gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; /* I2S interface */ i2s_alt0: i2s_alt0 { From 05b3c64d56370c836499c22ea83df68fe0083841 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Tue, 23 Aug 2016 08:40:32 +0200 Subject: [PATCH 08/29] ARM: BCM5301X: Add DT for Netgear R8500 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Netgear R8500 is another BCM47094 device, it just has three BCM4366 wireless chipsets. It's a very standard DT with mostly GPIO devices. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm47094-netgear-r8500.dts | 104 +++++++++++++++++++ 2 files changed, 105 insertions(+) create mode 100644 arch/arm/boot/dts/bcm47094-netgear-r8500.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index befcd2619902..93ec71e8bedf 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -87,6 +87,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4709-netgear-r7000.dtb \ bcm4709-netgear-r8000.dtb \ bcm47094-dlink-dir-885l.dtb \ + bcm47094-netgear-r8500.dtb \ bcm94708.dtb \ bcm94709.dtb \ bcm953012er.dtb \ diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts new file mode 100644 index 000000000000..10db4f8f2a44 --- /dev/null +++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2016 Rafał Miłecki + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + compatible = "netgear,r8500", "brcm,bcm47094", "brcm,bcm4708"; + model = "Netgear R8500"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + power0 { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + power1 { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + 5ghz-1 { + label = "bcm53xx:white:5ghz-1"; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + 5ghz-2 { + label = "bcm53xx:white:5ghz-2"; + gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + 2ghz { + label = "bcm53xx:white:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + usb2 { + label = "bcm53xx:white:usb2"; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + usb3 { + label = "bcm53xx:white:usb3"; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + brightness { + label = "Backlight"; + linux,code = ; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + + rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + status = "okay"; + clock-frequency = <125000000>; +}; From e90d2d51c41202ae6a99b4d5e1342482c1c8735b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Tue, 23 Aug 2016 07:37:43 +0200 Subject: [PATCH 09/29] ARM: BCM5301X: Add basic dts for BCM53573 based Tenda AC9 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BCM53573 seems to be low priced alternative for Northstar chipsts. It uses single core Cortex-A7 and doesn't have SDU or local (TWD) timer. It was also stripped out of independent SPI controller and 2 GMACs. DTS for Tenda AC9 isn't completed yet. It misses e.g. switch entry (we still need some b53 fixes) and probably some clocks. It adds support for basic features however and can be improved later. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/bcm47189-tenda-ac9.dts | 74 ++++++++++++ arch/arm/boot/dts/bcm53573.dtsi | 147 +++++++++++++++++++++++ 3 files changed, 223 insertions(+) create mode 100644 arch/arm/boot/dts/bcm47189-tenda-ac9.dts create mode 100644 arch/arm/boot/dts/bcm53573.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 93ec71e8bedf..103c2cf56f68 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -92,6 +92,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm94709.dtb \ bcm953012er.dtb \ bcm953012k.dtb +dtb-$(CONFIG_ARCH_BCM_53573) += \ + bcm47189-tenda-ac9.dtb dtb-$(CONFIG_ARCH_BCM_63XX) += \ bcm963138dvt.dtb dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts new file mode 100644 index 000000000000..4403ae8790c2 --- /dev/null +++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2016 Rafał Miłecki + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm53573.dtsi" + +/ { + compatible = "tenda,ac9", "brcm,bcm47189", "brcm,bcm53573"; + model = "Tenda AC9"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + usb { + label = "bcm53xx:blue:usb"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + wps { + label = "bcm53xx:blue:wps"; + gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + 5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + system { + label = "bcm53xx:blue:system"; + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi new file mode 100644 index 000000000000..efa07de50969 --- /dev/null +++ b/arch/arm/boot/dts/bcm53573.dtsi @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2016 Rafał Miłecki + * + * Licensed under the ISC license. + */ + +#include +#include +#include +#include +#include "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + chosen { + stdout-path = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + }; + + mpcore { + compatible = "simple-bus"; + ranges = <0x00000000 0x18310000 0x00008000>; + #address-cells = <1>; + #size-cells = <1>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x0100>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + alp: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <40000000>; + }; + }; + + axi@18000000 { + compatible = "brcm,bus-axi"; + reg = <0x18000000 0x1000>; + ranges = <0x00000000 0x18000000 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0x000fffff 0xffff>; + interrupt-map = + /* ChipCommon */ + <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + + /* IEEE 802.11 0 */ + <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + + /* PCIe Controller 0 */ + <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0x00002000 4 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0x00002000 5 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + + /* USB 2.0 Controller */ + <0x00004000 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 0 */ + <0x00005000 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + + /* IEEE 802.11 1 */ + <0x0000a000 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 1 */ + <0x0000b000 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + + chipcommon: chipcommon@0 { + compatible = "simple-bus"; + reg = <0x00000000 0x1000>; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + gpio-controller; + #gpio-cells = <2>; + + uart0: serial@0300 { + compatible = "ns16550a"; + reg = <0x0300 0x100>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&alp>; + status = "okay"; + }; + }; + + usb2: usb2@4000 { + reg = <0x4000 0x1000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + ehci: ehci@4000 { + compatible = "generic-ehci"; + reg = <0x4000 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + ohci: ohci@d000 { + #usb-cells = <0>; + + compatible = "generic-ohci"; + reg = <0xd000 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + gmac0: ethernet@5000 { + reg = <0x5000 0x1000>; + }; + + gmac1: ethernet@b000 { + reg = <0xb000 0x1000>; + }; + }; +}; From 329f98c1974e2323d9cc30964620e305113adac7 Mon Sep 17 00:00:00 2001 From: Kamal Dasu Date: Wed, 24 Aug 2016 18:04:27 -0400 Subject: [PATCH 10/29] ARM: dts: NSP: Add QSPI nodes to NSPI and bcm958625k DTSes Adding QSPI Device Tree node compatible with the new spi-bcm-qspi driver for the Broadcom Northstar Plus SoC DTSI and bcm958625k reference board. Signed-off-by: Kamal Dasu Signed-off-by: Yendapally Reddy Dhananjaya Reddy Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 31 ++++++++++++++++++++++++++++- arch/arm/boot/dts/bcm958625k.dts | 34 ++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 7c9e0fae9bb9..7502556143f0 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -160,7 +160,7 @@ periph_clk: periph_clk { axi { compatible = "simple-bus"; - ranges = <0x00000000 0x18000000 0x0011ba08>; + ranges = <0x00000000 0x18000000 0x0011c40a>; #address-cells = <1>; #size-cells = <1>; @@ -254,6 +254,35 @@ rng: rng@33000 { reg = <0x33000 0x14>; }; + qspi: qspi@27200 { + compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"; + reg = <0x027200 0x184>, + <0x027000 0x124>, + <0x11c408 0x004>, + <0x0273a0 0x01c>; + reg-names = "mspi", "bspi", "intr_regs", + "intr_status_reg"; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "spi_lr_fullness_reached", + "spi_lr_session_aborted", + "spi_lr_impatient", + "spi_lr_session_done", + "spi_lr_overhead", + "mspi_done", + "mspi_halted"; + clocks = <&iprocmed>; + clock-names = "iprocmed"; + num-cs = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + ccbtimer0: timer@34000 { compatible = "arm,sp804"; reg = <0x34000 0x1000>; diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index 05c5f98c8782..59d96fb91583 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -139,3 +139,37 @@ nand_sel: nand_sel { groups = "nand_grp"; }; }; + +&qspi { + bspi-sel = <0>; + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + reg = <0x0>; + spi-max-frequency = <12500000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x000a0000>; + }; + + partition@a0000 { + label = "env"; + reg = <0x000a0000 0x00060000>; + }; + + partition@100000 { + label = "system"; + reg = <0x00100000 0x00600000>; + }; + + partition@700000 { + label = "rootfs"; + reg = <0x00700000 0x01900000>; + }; + }; +}; From 54b902a4cd020cf0208d6cdb7e859adecdcd8216 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 21 Sep 2016 22:58:32 +0200 Subject: [PATCH 11/29] ARM: BCM5301X: Add separated DTS include file for BCM47094 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use it to store BCM47094 specific properties/values and avoid repeating them in device DTS files. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 3 +-- arch/arm/boot/dts/bcm47094-netgear-r8500.dts | 3 +-- arch/arm/boot/dts/bcm47094.dtsi | 11 +++++++++++ 3 files changed, 13 insertions(+), 4 deletions(-) create mode 100644 arch/arm/boot/dts/bcm47094.dtsi diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts index c8c0b3616935..661348dbb7ce 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts @@ -9,7 +9,7 @@ /dts-v1/; -#include "bcm4708.dtsi" +#include "bcm47094.dtsi" #include "bcm5301x-nand-cs0-bch1.dtsi" / { @@ -107,7 +107,6 @@ restart { &uart0 { status = "okay"; - clock-frequency = <125000000>; }; &usb3 { diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts index 10db4f8f2a44..521b4155de60 100644 --- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts +++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include "bcm4708.dtsi" +#include "bcm47094.dtsi" #include "bcm5301x-nand-cs0-bch8.dtsi" / { @@ -100,5 +100,4 @@ rfkill { &uart0 { status = "okay"; - clock-frequency = <125000000>; }; diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi new file mode 100644 index 000000000000..f03976597a6d --- /dev/null +++ b/arch/arm/boot/dts/bcm47094.dtsi @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2016 Rafał Miłecki + * + * Licensed under the ISC license. + */ + +#include "bcm4708.dtsi" + +&uart0 { + clock-frequency = <125000000>; +}; From fa87b008da3fcfc030545a48310dbfddd538a3c7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 21 Sep 2016 22:58:33 +0200 Subject: [PATCH 12/29] ARM: BCM5301X: Enable UART on Netgear R8000 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It was tested by LEDE users, all we need is to adjust clock frequency. While we're at it create a separated DTS include file to share code with other BCM4709 devices easier. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 2 +- arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 2 +- arch/arm/boot/dts/bcm4709-netgear-r7000.dts | 2 +- arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 6 +++++- arch/arm/boot/dts/bcm4709.dtsi | 11 +++++++++++ 5 files changed, 19 insertions(+), 4 deletions(-) create mode 100644 arch/arm/boot/dts/bcm4709.dtsi diff --git a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts index 8ade7def2e8a..eac0f52e5ebd 100644 --- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts @@ -9,7 +9,7 @@ /dts-v1/; -#include "bcm4708.dtsi" +#include "bcm4709.dtsi" #include "bcm5301x-nand-cs0-bch8.dtsi" / { diff --git a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts index 0653e7ef248c..aab39c9864da 100644 --- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts @@ -9,7 +9,7 @@ /dts-v1/; -#include "bcm4708.dtsi" +#include "bcm4709.dtsi" #include "bcm5301x-nand-cs0-bch8.dtsi" / { diff --git a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts index a22ed144040b..fd38d2aa3521 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts @@ -9,7 +9,7 @@ /dts-v1/; -#include "bcm4708.dtsi" +#include "bcm4709.dtsi" #include "bcm5301x-nand-cs0-bch8.dtsi" / { diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts index ca181516c28a..92f8a7219e98 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts @@ -9,7 +9,7 @@ /dts-v1/; -#include "bcm4708.dtsi" +#include "bcm4709.dtsi" #include "bcm5301x-nand-cs0-bch8.dtsi" / { @@ -107,6 +107,10 @@ restart { }; }; +&uart0 { + status = "okay"; +}; + &usb2 { vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/bcm4709.dtsi b/arch/arm/boot/dts/bcm4709.dtsi new file mode 100644 index 000000000000..f03976597a6d --- /dev/null +++ b/arch/arm/boot/dts/bcm4709.dtsi @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2016 Rafał Miłecki + * + * Licensed under the ISC license. + */ + +#include "bcm4708.dtsi" + +&uart0 { + clock-frequency = <125000000>; +}; From 92b7b6ad1a095fd72561a33855f93dfde5b2324f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 21 Sep 2016 22:58:34 +0200 Subject: [PATCH 13/29] ARM: BCM5301X: Specify USB 3.0 PHY in DT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Driver for Northstar USB 3.0 PHY has been recently added under the name phy-bcm-ns-usb3. Add binding for it into the DT files. The only slightly tricky part is BCM47094 which uses different PHY version and requires different compatible value. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094.dtsi | 6 ++++++ arch/arm/boot/dts/bcm5301x.dtsi | 7 +++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi index f03976597a6d..4f09aa0114e6 100644 --- a/arch/arm/boot/dts/bcm47094.dtsi +++ b/arch/arm/boot/dts/bcm47094.dtsi @@ -6,6 +6,12 @@ #include "bcm4708.dtsi" +/ { + usb3_phy: usb3-phy { + compatible = "brcm,ns-bx-usb3-phy"; + }; +}; + &uart0 { clock-frequency = <125000000>; }; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index ae4b3880616d..f09a2bb08979 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -149,6 +149,13 @@ usb2_phy: usb2-phy { clock-names = "phy-ref-clk"; }; + usb3_phy: usb3-phy { + compatible = "brcm,ns-ax-usb3-phy"; + reg = <0x18105000 0x1000>, <0x18003000 0x1000>; + reg-names = "dmp", "ccb-mii"; + #phy-cells = <0>; + }; + axi@18000000 { compatible = "brcm,bus-axi"; reg = <0x18000000 0x1000>; From fe91846397ca9ac1b4b0f913676a057b1ecabbc2 Mon Sep 17 00:00:00 2001 From: Dan Haab Date: Tue, 27 Sep 2016 11:27:10 -0600 Subject: [PATCH 14/29] ARM: BCM5301X: Add DT for Luxul XAP-1510 Luxul XAP-1510 is an AP device based on BCM4708 SoC with 2 x BCM4360 chipsets on PCB connected using PCIe. Signed-off-by: Dan Haab Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 64 ++++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 103c2cf56f68..fd4e299871a7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -75,6 +75,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4708-asus-rt-ac56u.dtb \ bcm4708-asus-rt-ac68u.dtb \ bcm4708-buffalo-wzr-1750dhp.dtb \ + bcm4708-luxul-xap-1510.dtb \ bcm4708-luxul-xwc-1000.dtb \ bcm4708-netgear-r6250.dtb \ bcm4708-netgear-r6300-v2.dtb \ diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts new file mode 100644 index 000000000000..35e6ed6a3ef7 --- /dev/null +++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts @@ -0,0 +1,64 @@ +/* + * Copyright 2016 Luxul Inc. + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" + +/ { + compatible = "luxul,xap-1510v1", "brcm,bcm4708"; + model = "Luxul XAP-1510 V1"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + 5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + 2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi_nor { + status = "okay"; +}; From 4335e6fd58b8771ac15f949307b088f7df60c592 Mon Sep 17 00:00:00 2001 From: Dan Haab Date: Tue, 27 Sep 2016 11:27:11 -0600 Subject: [PATCH 15/29] ARM: BCM5301X: Add DT for Luxul XWR-3100 Luxul XWR-3100 is a wireless router based on BCM47094 SoC with two 4366c0 FullMAC PCIe cards on the PCB. It uses NAND with BCH-4 ECC algorithm. Signed-off-by: Dan Haab Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 111 ++++++++++++++++++ arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi | 13 ++ 3 files changed, 125 insertions(+) create mode 100644 arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts create mode 100644 arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index fd4e299871a7..837703ac79e8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -88,6 +88,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4709-netgear-r7000.dtb \ bcm4709-netgear-r8000.dtb \ bcm47094-dlink-dir-885l.dtb \ + bcm47094-luxul-xwr-3100.dtb \ bcm47094-netgear-r8500.dtb \ bcm94708.dtb \ bcm94709.dtb \ diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts new file mode 100644 index 000000000000..169b35fe5651 --- /dev/null +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts @@ -0,0 +1,111 @@ +/* + * Copyright 2016 Luxul Inc. + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm47094.dtsi" +#include "bcm5301x-nand-cs0-bch4.dtsi" + +/ { + compatible = "luxul,xwr-3100v1", "brcm,bcm47094", "brcm,bcm4708"; + model = "Luxul XWR-3100 V1"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + power { + label = "bcm53xx:green:power"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + lan3 { + label = "bcm53xx:green:lan1"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + lan4 { + label = "bcm53xx:green:lan0"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + wan { + label = "bcm53xx:green:wan"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + lan1 { + label = "bcm53xx:green:lan3"; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + lan2 { + label = "bcm53xx:green:lan2"; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + usb3 { + label = "bcm53xx:green:usb3"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + status { + label = "bcm53xx:green:status"; + gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + + 2ghz { + label = "bcm53xx:green:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + 5ghz { + label = "bcm53xx:green:5ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&usb3 { + vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +}; + +&spi_nor { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi new file mode 100644 index 000000000000..b4e875df9528 --- /dev/null +++ b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch4.dtsi @@ -0,0 +1,13 @@ +/* + * Copyright 2016 Luxul Inc. + * + * Licensed under the ISC license. + */ + +#include "bcm5301x-nand-cs0.dtsi" + +&nandcs { + nand-ecc-algo = "bch"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; +}; From 547f23183d9d77b51754689a71e3e58d085ccaec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Sat, 17 Sep 2016 22:13:46 +0200 Subject: [PATCH 16/29] ARM: BCM53573: Specify PMU and its ILP clock in the DT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ILP clock (sometimes called a "slow clock") is a part of PMU (Power Management Unit). There has been recently added a driver for it, so add a proper entry in the DT as well. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm53573.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi index efa07de50969..e2c496a96c32 100644 --- a/arch/arm/boot/dts/bcm53573.dtsi +++ b/arch/arm/boot/dts/bcm53573.dtsi @@ -143,5 +143,17 @@ gmac0: ethernet@5000 { gmac1: ethernet@b000 { reg = <0xb000 0x1000>; }; + + pmu@12000 { + compatible = "simple-mfd", "syscon"; + reg = <0x00012000 0x00001000>; + + ilp: ilp { + compatible = "brcm,bcm53573-ilp"; + clocks = <&alp>; + #clock-cells = <0>; + clock-output-names = "ilp"; + }; + }; }; }; From b350e9dd1f782933ff587d20259371acdc1213c8 Mon Sep 17 00:00:00 2001 From: Scott Branden Date: Sat, 8 Oct 2016 13:34:26 -0700 Subject: [PATCH 17/29] ARM: dts: cygnus: fix naming of pinctrl node Remove 0x from pinctrl node to match device tree naming convention. Signed-off-by: Scott Branden Reviewed-by: Ray Jui Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index fabc9f36c408..539c58f12f51 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -108,7 +108,7 @@ pcie1_phy: phy@1 { }; }; - pinctrl: pinctrl@0x0301d0c8 { + pinctrl: pinctrl@0301d0c8 { compatible = "brcm,cygnus-pinmux"; reg = <0x0301d0c8 0x30>, <0x0301d24c 0x2c>; From 3435bbf28ae3b10c403bec4b042d4a17e3c44052 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Wed, 26 Oct 2016 18:13:59 +0000 Subject: [PATCH 18/29] DT: binding: bcm2835-mbox: fix address typo in example MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The address of the mailbox node in the example has a typo. So fix it accordingly. Signed-off-by: Stefan Wahren Fixes: d4b5c782b9f4 ("dt/bindings: Add binding for the BCM2835 mailbox driver") Acked-by: Rob Herring Reviewed-by: Andreas Färber Signed-off-by: Eric Anholt --- Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt index e893615ef635..b48d7d30012c 100644 --- a/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt +++ b/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt @@ -12,7 +12,7 @@ Required properties: Example: -mailbox: mailbox@7e00b800 { +mailbox: mailbox@7e00b880 { compatible = "brcm,bcm2835-mbox"; reg = <0x7e00b880 0x40>; interrupts = <0 1>; From 7d891a685dd46b925cf25b74ada0280a2531c34f Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 30 Oct 2016 17:22:19 +0000 Subject: [PATCH 19/29] ARM: dts: bcm283x: fix typo in mailbox address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The address of the mailbox node in the bcm283x.dtsi also has a typo. So fix it accordingly. Signed-off-by: Stefan Wahren Reviewed-by: Andreas Färber Fixes: 05b682b7a3b2 ("ARM: bcm2835: dt: Add the mailbox to the device tree") Signed-off-by: Eric Anholt --- arch/arm/boot/dts/bcm283x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index 2123d0eb1890..eae6ab88d1a6 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -104,7 +104,7 @@ rng@7e104000 { reg = <0x7e104000 0x10>; }; - mailbox: mailbox@7e00b800 { + mailbox: mailbox@7e00b880 { compatible = "brcm,bcm2835-mbox"; reg = <0x7e00b880 0x40>; interrupts = <0 1>; From 1567e95a010b7e0adbfacbf3c5d863e7850fdc28 Mon Sep 17 00:00:00 2001 From: Martin Sperl Date: Wed, 2 Nov 2016 10:18:21 +0000 Subject: [PATCH 20/29] dt: bindings: add thermal device driver for bcm2835 Add dt-binding documentation for bcm2835 SOC thermal sensor. Signed-off-by: Martin Sperl Acked-by: Eric Anholt Acked-by: Rob Herring Changelog: V1 -> V2: renamed file to follow naming conventions V2 -> V3: removed 0x in node name Signed-off-by: Eric Anholt --- .../bindings/thermal/brcm,bcm2835-thermal.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/brcm,bcm2835-thermal.txt diff --git a/Documentation/devicetree/bindings/thermal/brcm,bcm2835-thermal.txt b/Documentation/devicetree/bindings/thermal/brcm,bcm2835-thermal.txt new file mode 100644 index 000000000000..474531d2b2c5 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/brcm,bcm2835-thermal.txt @@ -0,0 +1,17 @@ +Binding for Thermal Sensor driver for BCM2835 SoCs. + +Required parameters: +------------------- + +compatible: should be one of: "brcm,bcm2835-thermal", + "brcm,bcm2836-thermal" or "brcm,bcm2837-thermal" +reg: Address range of the thermal registers. +clocks: Phandle of the clock used by the thermal sensor. + +Example: + +thermal: thermal@7e212000 { + compatible = "brcm,bcm2835-thermal"; + reg = <0x7e212000 0x8>; + clocks = <&clocks BCM2835_CLOCK_TSENS>; +}; From 43bac4133f405b67857e4c985aecc44a57233bfe Mon Sep 17 00:00:00 2001 From: Martin Sperl Date: Wed, 2 Nov 2016 10:18:23 +0000 Subject: [PATCH 21/29] ARM: bcm2835: dts: add thermal node to device-tree of bcm283x Add the node for the thermal sensor of the bcm2835-soc to the device tree. Signed-off-by: Martin Sperl Reviewed-by: Eric Anholt Acked-by: Stefan Wahren Changelog: V1 -> V5: generic settings is shared in bcm283x.dtsi, but disabled moved the compatible string to the SOC specific dtsi for arm and arm64 V5 -> V6: fix remove 0x prefix from thermal@0x7e212000 Note: there is no arm/boot/dts/bcm2837.dtsi as of now, so the 32-bit rpi3 dt is not modified. Signed-off-by: Eric Anholt --- arch/arm/boot/dts/bcm2835.dtsi | 6 ++++++ arch/arm/boot/dts/bcm2836.dtsi | 6 ++++++ arch/arm/boot/dts/bcm283x.dtsi | 7 +++++++ 3 files changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index a78759e73710..0890d97e674d 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -23,3 +23,9 @@ arm-pmu { }; }; }; + +/* enable thermal sensor with the correct compatible property set */ +&thermal { + compatible = "brcm,bcm2835-thermal"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi index 9d0651d8f373..519a44f5d25a 100644 --- a/arch/arm/boot/dts/bcm2836.dtsi +++ b/arch/arm/boot/dts/bcm2836.dtsi @@ -76,3 +76,9 @@ &intc { interrupt-parent = <&local_intc>; interrupts = <8>; }; + +/* enable thermal sensor with the correct compatible property set */ +&thermal { + compatible = "brcm,bcm2836-thermal"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index eae6ab88d1a6..9a44da190897 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -390,6 +390,13 @@ pixelvalve@7e207000 { interrupts = <2 14>; /* pwa1 */ }; + thermal: thermal@7e212000 { + compatible = "brcm,bcm2835-thermal"; + reg = <0x7e212000 0x8>; + clocks = <&clocks BCM2835_CLOCK_TSENS>; + status = "disabled"; + }; + aux: aux@0x7e215000 { compatible = "brcm,bcm2835-aux"; #clock-cells = <1>; From 731b26a6ac17f24057c559361c6d0cb7cb79baed Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 6 Oct 2016 13:15:02 +0200 Subject: [PATCH 22/29] ARM: bcm2835: Add names for the Raspberry Pi GPIO lines The idea is to give useful names to GPIO lines that an implementer will be using from userspace, e.g. for maker type projects. These are user-visible using tools/gpio/lsgpio.c v2: Major rewrite by anholt: Flatten each GPIO line to a line in the file for better diffing, prefix all expansion header pins with "P" or "P5HEADER_P" and drop the mostly-unused GPIO_GEN names in favor of GPIO, fix extra '[]' on a couple of lines, fix locations of SD_CARD_DETECT, CAM_GPIO and STATUS_LED, fix HDMI_HPD polarities, rewrite A+ using unreleased schematics. v3: More changes by anholt: Drop P / P5HEADER prefixes. I had been skeptical about adding them, and was convinced to drop them by Gottfried (who probably has more experience with GPIOs in educational contexts than the rest of us). Also drop [] brackets for "is pinmuxed", which didn't seem to clarify, and were ambiguous for things like the SPI_*-labeled pins which may or may not actually be pinmuxed to SPI. v4: Rename B+'s SDA0/SCL0 to match the other boards, despite the naming on its schematic. Signed-off-by: Linus Walleij Signed-off-by: Eric Anholt --- arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 65 +++++++++++++++++++++++ arch/arm/boot/dts/bcm2835-rpi-a.dts | 67 ++++++++++++++++++++++++ arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 66 +++++++++++++++++++++++ arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts | 66 +++++++++++++++++++++++ arch/arm/boot/dts/bcm2835-rpi-b.dts | 67 ++++++++++++++++++++++++ 5 files changed, 331 insertions(+) diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts index 21507c922783..5a22c7965f34 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts @@ -22,6 +22,71 @@ pwr { }; &gpio { + /* + * This is based on the unreleased schematic for the Model A+. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "SDA0", + "SCL0", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "NC", /* GPIO30 */ + "NC", /* GPIO31 */ + "NC", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "PWR_LOW_N", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "NC", /* GPIO38 */ + "NC", /* GPIO39 */ + "PWM0_OUT", /* GPIO40 */ + "CAM_GPIO0", /* GPIO41 */ + "NC", /* GPIO42 */ + "NC", /* GPIO43 */ + "NC", /* GPIO44 */ + "PWM1_OUT", /* GPIO45 */ + "HDMI_HPD_N", + "STATUS_LED", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; /* I2S interface */ diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts index 5afba0900449..54f98c59a75d 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts @@ -15,6 +15,73 @@ act { }; &gpio { + /* + * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf + * RPI00021 sheet 02 + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "SDA0", + "SCL0", + "SDA1", + "SCL1", + "GPIO_GCLK", + "CAM_CLK", + "LAN_RUN", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "NC", /* GPIO12 */ + "NC", /* GPIO13 */ + /* Serial port */ + "TXD0", + "RXD0", + "STATUS_LED_N", + "GPIO17", + "GPIO18", + "NC", /* GPIO19 */ + "NC", /* GPIO20 */ + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "NC", /* GPIO26 */ + "CAM_GPIO", + /* Binary number representing build/revision */ + "CONFIG0", + "CONFIG1", + "CONFIG2", + "CONFIG3", + "NC", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "NC", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "NC", /* GPIO38 */ + "NC", /* GPIO39 */ + "PWM0_OUT", + "NC", /* GPIO41 */ + "NC", /* GPIO42 */ + "NC", /* GPIO43 */ + "NC", /* GPIO44 */ + "PWM1_OUT", + "HDMI_HPD_P", + "SD_CARD_DET", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + pinctrl-0 = <&gpioout &alt0 &i2s_alt2>; /* I2S interface */ diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index 38f66aa244fe..b67587e6cbef 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -23,6 +23,72 @@ pwr { }; &gpio { + /* + * Taken from Raspberry-Pi-B-Plus-V1.2-Schematics.pdf + * RPI-BPLUS sheet 1 + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "SDA0", + "SCL0", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "NC", /* GPIO30 */ + "LAN_RUN", /* GPIO31 */ + "CAM_GPIO1", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "PWR_LOW_N", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "NC", /* GPIO38 */ + "NC", /* GPIO39 */ + "PWM0_OUT", /* GPIO40 */ + "CAM_GPIO0", /* GPIO41 */ + "NC", /* GPIO42 */ + "NC", /* GPIO43 */ + "ETHCLK", /* GPIO44 */ + "PWM1_OUT", /* GPIO45 */ + "HDMI_HPD_N", + "STATUS_LED", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; /* I2S interface */ diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts index 75e045aba7ce..4133bc2cd9be 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts @@ -16,6 +16,72 @@ act { }; &gpio { + /* + * Taken from Raspberry-Pi-Rev-2.0-Model-AB-Schematics.pdf + * RPI00022 sheet 02 + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "SDA0", + "SCL0", + "SDA1", + "SCL1", + "GPIO_GCLK", + "CAM_CLK", + "LAN_RUN", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "NC", /* GPIO12 */ + "NC", /* GPIO13 */ + /* Serial port */ + "TXD0", + "RXD0", + "STATUS_LED_N", + "GPIO17", + "GPIO18", + "NC", /* GPIO19 */ + "NC", /* GPIO20 */ + "CAM_GPIO", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "NC", /* GPIO26 */ + "GPIO27", + "GPIO28", + "GPIO29", + "GPIO30", + "GPIO31", + "NC", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "NC", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "NC", /* GPIO38 */ + "NC", /* GPIO39 */ + "PWM0_OUT", + "NC", /* GPIO41 */ + "NC", /* GPIO42 */ + "NC", /* GPIO43 */ + "NC", /* GPIO44 */ + "PWM1_OUT", + "HDMI_HPD_P", + "SD_CARD_DET", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + pinctrl-0 = <&gpioout &alt0 &i2s_alt2>; /* I2S interface */ diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index 76a254b3219a..71f50e16c646 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -16,6 +16,73 @@ act { }; &gpio { + /* + * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf + * RPI00021 sheet 02 + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "SDA0", + "SCL0", + "SDA1", + "SCL1", + "GPIO_GCLK", + "CAM_CLK", + "LAN_RUN", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "NC", /* GPIO12 */ + "NC", /* GPIO13 */ + /* Serial port */ + "TXD0", + "RXD0", + "STATUS_LED_N", + "GPIO17", + "GPIO18", + "NC", /* GPIO19 */ + "NC", /* GPIO20 */ + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "NC", /* GPIO26 */ + "CAM_GPIO", + /* Binary number representing build/revision */ + "CONFIG0", + "CONFIG1", + "CONFIG2", + "CONFIG3", + "NC", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "NC", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "NC", /* GPIO38 */ + "NC", /* GPIO39 */ + "PWM0_OUT", + "NC", /* GPIO41 */ + "NC", /* GPIO42 */ + "NC", /* GPIO43 */ + "NC", /* GPIO44 */ + "PWM1_OUT", + "HDMI_HPD_P", + "SD_CARD_DET", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + pinctrl-0 = <&gpioout &alt0>; }; From 77f923cb141bdc77b61a9296581ef86b34e134e5 Mon Sep 17 00:00:00 2001 From: Jonathan Richardson Date: Tue, 18 Oct 2016 12:00:37 -0700 Subject: [PATCH 23/29] ARM: dts: Enable Broadcom iProc mailbox controller Reviewed-by: Jonathan Richardson Reviewed-by: Shreesha Rajashekar Reviewed-by: Ray Jui Tested-by: Jonathan Richardson Reviewed-by: Vikram Prakash Reviewed-by: Scott Branden Signed-off-by: Jonathan Richardson Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 539c58f12f51..4b741f67ec6a 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -114,6 +114,15 @@ pinctrl: pinctrl@0301d0c8 { <0x0301d24c 0x2c>; }; + mailbox: mailbox@03024024 { + compatible = "brcm,iproc-mailbox"; + reg = <0x03024024 0x40>; + interrupts = ; + #interrupt-cells = <1>; + interrupt-controller; + #mbox-cells = <1>; + }; + gpio_crmu: gpio@03024800 { compatible = "brcm,cygnus-crmu-gpio"; reg = <0x03024800 0x50>, From 2c42d0f060801caad669290d337a12b26560fac9 Mon Sep 17 00:00:00 2001 From: Jonathan Richardson Date: Tue, 18 Oct 2016 12:00:38 -0700 Subject: [PATCH 24/29] ARM: dts: Enable interrupt support for cygnus crmu gpio driver The M0 processor handles interrupts for the always-on CRMU GPIO controller. Setting the CRMU GPIO driver with the mailbox controller as the interrupt parent allows the mailbox controller to forward interrupts from the M0 to the GPIO driver for processing. Reviewed-by: Jonathan Richardson Tested-by: Jonathan Richardson Reviewed-by: Vikram Prakash Reviewed-by: Shreesha Rajashekar Reviewed-by: Ray Jui Reviewed-by: Scott Branden Signed-off-by: Jonathan Richardson Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 4b741f67ec6a..c592f6d82685 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -130,6 +130,9 @@ gpio_crmu: gpio@03024800 { ngpios = <6>; #gpio-cells = <2>; gpio-controller; + interrupt-controller; + interrupt-parent = <&mailbox>; + interrupts = <0>; }; i2c0: i2c@18008000 { From 7fa8b51b5d2aff3cf8e932310eb43882f06a751c Mon Sep 17 00:00:00 2001 From: Jonathan Richardson Date: Mon, 24 Oct 2016 12:12:04 -0700 Subject: [PATCH 25/29] ARM: dts: Add node for Broadcom OTP controller driver Reviewed-by: Ray Jui Tested-by: Jonathan Richardson Signed-off-by: Scott Branden Signed-off-by: Oza Pawandeep Signed-off-by: Jonathan Richardson Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index c592f6d82685..8833a4c3cd96 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -91,6 +91,13 @@ axi { #address-cells = <1>; #size-cells = <1>; + otp: otp@0301c800 { + compatible = "brcm,ocotp"; + reg = <0x0301c800 0x2c>; + brcm,ocotp-size = <2048>; + status = "disabled"; + }; + pcie_phy: phy@0301d0a0 { compatible = "brcm,cygnus-pcie-phy"; reg = <0x0301d0a0 0x14>; From 41182beb217c47cfbaaf26a60f22a8b3943faa61 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Sun, 13 Nov 2016 11:12:09 +0100 Subject: [PATCH 26/29] ARM: BCM5301X: Add DT for TP-LINK Archer C9 V1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's BCM4709A0 based device with 16 MiB flash, 128 MiB of RAM and two PCIe based on-PCB BCM4360 chipsets. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/bcm4709-tplink-archer-c9-v1.dts | 114 ++++++++++++++++++ 2 files changed, 115 insertions(+) create mode 100644 arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 837703ac79e8..7a52a9f8d5a7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -87,6 +87,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4709-buffalo-wxr-1900dhp.dtb \ bcm4709-netgear-r7000.dtb \ bcm4709-netgear-r8000.dtb \ + bcm4709-tplink-archer-c9-v1.dtb \ bcm47094-dlink-dir-885l.dtb \ bcm47094-luxul-xwr-3100.dtb \ bcm47094-netgear-r8500.dtb \ diff --git a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts new file mode 100644 index 000000000000..9a92c24ac2d8 --- /dev/null +++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2016 Rafał Miłecki + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm4709.dtsi" + +/ { + compatible = "tplink,archer-c9-v1", "brcm,bcm4709", "brcm,bcm4708"; + model = "TP-LINK Archer C9 V1"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + lan { + label = "bcm53xx:blue:lan"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + wps { + label = "bcm53xx:blue:wps"; + gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + 2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + 5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + usb3 { + label = "bcm53xx:blue:usb3"; + gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + usb2 { + label = "bcm53xx:blue:usb2"; + gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + wan-blue { + label = "bcm53xx:blue:wan"; + gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + wan-amber { + label = "bcm53xx:amber:wan"; + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + power { + label = "bcm53xx:blue:power"; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&usb2 { + vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; +}; + +&usb3 { + vcc-gpio = <&chipcommon 12 GPIO_ACTIVE_HIGH>; +}; + +&spi_nor { + status = "okay"; +}; From 1480986d68ce32706ff08586e111dcb769dd3962 Mon Sep 17 00:00:00 2001 From: Yendapally Reddy Dhananjaya Reddy Date: Mon, 14 Nov 2016 08:30:19 -0500 Subject: [PATCH 27/29] ARM: dts: enable GPIO-b for Broadcom NSP This enables the GPIO-b support for Broadcom NSP SoC Signed-off-by: Yendapally Reddy Dhananjaya Reddy Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 7502556143f0..b6142bda661e 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -241,6 +241,16 @@ nand: nand@26000 { brcm,nand-has-wp; }; + gpiob: gpio@30000 { + compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio"; + reg = <0x30000 0x50>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <4>; + interrupt-controller; + interrupts = ; + }; + pwm: pwm@31000 { compatible = "brcm,iproc-pwm"; reg = <0x31000 0x28>; From 6b9170887e1b912b657dab4597f8b44ae4dbdf50 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Wed, 16 Nov 2016 17:52:06 +0000 Subject: [PATCH 28/29] ARM: bcm2835: Fix names for the Raspberry Pi GPIO lines There are some differences between the schematics and the official firmware DTS [1]. So based on these additional information the following has been changed: * use consistent "CAM_GPIO1" for camera LED * use consistent "CAM_GPIO0" for camera shutdown * add "USB_LIMIT" for USB current limit (0=600mA, 1=1200mA) [1] - https://github.com/raspberrypi/firmware/blob/master/extra/dt-blob.dts Signed-off-by: Stefan Wahren Signed-off-by: Eric Anholt --- arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 4 ++-- arch/arm/boot/dts/bcm2835-rpi-a.dts | 4 ++-- arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 2 +- arch/arm/boot/dts/bcm2835-rpi-b.dts | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts index 5a22c7965f34..d0704540db6b 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts @@ -63,13 +63,13 @@ &gpio { "SCL0", "NC", /* GPIO30 */ "NC", /* GPIO31 */ - "NC", /* GPIO32 */ + "CAM_GPIO1", /* GPIO32 */ "NC", /* GPIO33 */ "NC", /* GPIO34 */ "PWR_LOW_N", /* GPIO35 */ "NC", /* GPIO36 */ "NC", /* GPIO37 */ - "NC", /* GPIO38 */ + "USB_LIMIT", /* GPIO38 */ "NC", /* GPIO39 */ "PWM0_OUT", /* GPIO40 */ "CAM_GPIO0", /* GPIO41 */ diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts index 54f98c59a75d..46d078e29017 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts @@ -29,7 +29,7 @@ &gpio { "SDA1", "SCL1", "GPIO_GCLK", - "CAM_CLK", + "CAM_GPIO1", "LAN_RUN", "SPI_CE1_N", "SPI_CE0_N", @@ -52,7 +52,7 @@ &gpio { "GPIO24", "GPIO25", "NC", /* GPIO26 */ - "CAM_GPIO", + "CAM_GPIO0", /* Binary number representing build/revision */ "CONFIG0", "CONFIG1", diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index b67587e6cbef..432088ebb0a1 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -71,7 +71,7 @@ &gpio { "PWR_LOW_N", /* GPIO35 */ "NC", /* GPIO36 */ "NC", /* GPIO37 */ - "NC", /* GPIO38 */ + "USB_LIMIT", /* GPIO38 */ "NC", /* GPIO39 */ "PWM0_OUT", /* GPIO40 */ "CAM_GPIO0", /* GPIO41 */ diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index 71f50e16c646..4d56fe3006b0 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -30,7 +30,7 @@ &gpio { "SDA1", "SCL1", "GPIO_GCLK", - "CAM_CLK", + "CAM_GPIO1", "LAN_RUN", "SPI_CE1_N", "SPI_CE0_N", @@ -53,7 +53,7 @@ &gpio { "GPIO24", "GPIO25", "NC", /* GPIO26 */ - "CAM_GPIO", + "CAM_GPIO0", /* Binary number representing build/revision */ "CONFIG0", "CONFIG1", From 3a1689ea752436917c5ce4487527ed6c444630ee Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Wed, 16 Nov 2016 17:52:07 +0000 Subject: [PATCH 29/29] ARM: bcm2835: Add names for the RPi Zero GPIO lines This adds the GPIO names for the Raspberry Pi Zero. The GPIO lines of the RPi Zero are almost identical to the Model A+ except: * GPIO 35, 38, 40 and 45 are not connected * Status LED is active low Signed-off-by: Stefan Wahren Signed-off-by: Eric Anholt --- arch/arm/boot/dts/bcm2835-rpi-zero.dts | 65 ++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts index 7c1c18048948..cc8b832c4c78 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts @@ -26,6 +26,71 @@ act { }; &gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "SDA0", + "SCL0", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "SDA0", + "SCL0", + "NC", /* GPIO30 */ + "NC", /* GPIO31 */ + "CAM_GPIO1", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "NC", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "NC", /* GPIO38 */ + "NC", /* GPIO39 */ + "NC", /* GPIO40 */ + "CAM_GPIO0", /* GPIO41 */ + "NC", /* GPIO42 */ + "NC", /* GPIO43 */ + "NC", /* GPIO44 */ + "NC", /* GPIO45 */ + "HDMI_HPD_N", + "STATUS_LED_N", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; /* I2S interface */