mfd: 880m80x: Make use of BIT() macro
Instead of hard coding the shift for bit definition, use BIT() macro. Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Vaibhav Hiremath
Lee Jones
parent
acdecb04e2
commit
bc00d68f2f
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@ -60,24 +60,24 @@ enum {
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/* page 0 basic: slave adder 0x60 */
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#define PM800_STATUS_1 (0x01)
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#define PM800_ONKEY_STS1 (1 << 0)
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#define PM800_EXTON_STS1 (1 << 1)
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#define PM800_CHG_STS1 (1 << 2)
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#define PM800_BAT_STS1 (1 << 3)
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#define PM800_VBUS_STS1 (1 << 4)
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#define PM800_LDO_PGOOD_STS1 (1 << 5)
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#define PM800_BUCK_PGOOD_STS1 (1 << 6)
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#define PM800_ONKEY_STS1 BIT(0)
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#define PM800_EXTON_STS1 BIT(1)
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#define PM800_CHG_STS1 BIT(2)
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#define PM800_BAT_STS1 BIT(3)
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#define PM800_VBUS_STS1 BIT(4)
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#define PM800_LDO_PGOOD_STS1 BIT(5)
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#define PM800_BUCK_PGOOD_STS1 BIT(6)
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#define PM800_STATUS_2 (0x02)
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#define PM800_RTC_ALARM_STS2 (1 << 0)
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#define PM800_RTC_ALARM_STS2 BIT(0)
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/* Wakeup Registers */
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#define PM800_WAKEUP1 (0x0D)
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#define PM800_WAKEUP2 (0x0E)
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#define PM800_WAKEUP2_INV_INT (1 << 0)
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#define PM800_WAKEUP2_INT_CLEAR (1 << 1)
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#define PM800_WAKEUP2_INT_MASK (1 << 2)
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#define PM800_WAKEUP2_INV_INT BIT(0)
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#define PM800_WAKEUP2_INT_CLEAR BIT(1)
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#define PM800_WAKEUP2_INT_MASK BIT(2)
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#define PM800_POWER_UP_LOG (0x10)
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@ -89,26 +89,26 @@ enum {
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/* GPIO register */
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#define PM800_GPIO_0_1_CNTRL (0x30)
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#define PM800_GPIO0_VAL (1 << 0)
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#define PM800_GPIO0_VAL BIT(0)
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#define PM800_GPIO0_GPIO_MODE(x) (x << 1)
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#define PM800_GPIO1_VAL (1 << 4)
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#define PM800_GPIO1_VAL BIT(4)
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#define PM800_GPIO1_GPIO_MODE(x) (x << 5)
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#define PM800_GPIO_2_3_CNTRL (0x31)
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#define PM800_GPIO2_VAL (1 << 0)
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#define PM800_GPIO2_VAL BIT(0)
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#define PM800_GPIO2_GPIO_MODE(x) (x << 1)
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#define PM800_GPIO3_VAL (1 << 4)
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#define PM800_GPIO3_VAL BIT(4)
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#define PM800_GPIO3_GPIO_MODE(x) (x << 5)
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#define PM800_GPIO3_MODE_MASK 0x1F
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#define PM800_GPIO3_HEADSET_MODE PM800_GPIO3_GPIO_MODE(6)
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#define PM800_GPIO_4_CNTRL (0x32)
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#define PM800_GPIO4_VAL (1 << 0)
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#define PM800_GPIO4_VAL BIT(0)
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#define PM800_GPIO4_GPIO_MODE(x) (x << 1)
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#define PM800_HEADSET_CNTRL (0x38)
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#define PM800_HEADSET_DET_EN (1 << 7)
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#define PM800_HSDET_SLP (1 << 1)
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#define PM800_HEADSET_DET_EN BIT(7)
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#define PM800_HSDET_SLP BIT(1)
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/* PWM register */
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#define PM800_PWM1 (0x40)
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#define PM800_PWM2 (0x41)
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@ -123,10 +123,10 @@ enum {
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#define PM800_RTC_MISC4 (0xE4)
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#define PM800_RTC_MISC5 (0xE7)
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/* bit definitions of RTC Register 1 (0xD0) */
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#define PM800_ALARM1_EN (1 << 0)
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#define PM800_ALARM_WAKEUP (1 << 4)
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#define PM800_ALARM (1 << 5)
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#define PM800_RTC1_USE_XO (1 << 7)
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#define PM800_ALARM1_EN BIT(0)
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#define PM800_ALARM_WAKEUP BIT(4)
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#define PM800_ALARM BIT(5)
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#define PM800_RTC1_USE_XO BIT(7)
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/* Regulator Control Registers: BUCK1,BUCK5,LDO1 have DVC */
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@ -140,18 +140,18 @@ enum {
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/* page 2 GPADC: slave adder 0x02 */
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#define PM800_GPADC_MEAS_EN1 (0x01)
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#define PM800_MEAS_EN1_VBAT (1 << 2)
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#define PM800_MEAS_EN1_VBAT BIT(2)
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#define PM800_GPADC_MEAS_EN2 (0x02)
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#define PM800_MEAS_EN2_RFTMP (1 << 0)
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#define PM800_MEAS_GP0_EN (1 << 2)
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#define PM800_MEAS_GP1_EN (1 << 3)
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#define PM800_MEAS_GP2_EN (1 << 4)
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#define PM800_MEAS_GP3_EN (1 << 5)
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#define PM800_MEAS_GP4_EN (1 << 6)
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#define PM800_MEAS_EN2_RFTMP BIT(0)
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#define PM800_MEAS_GP0_EN BIT(2)
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#define PM800_MEAS_GP1_EN BIT(3)
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#define PM800_MEAS_GP2_EN BIT(4)
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#define PM800_MEAS_GP3_EN BIT(5)
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#define PM800_MEAS_GP4_EN BIT(6)
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#define PM800_GPADC_MISC_CONFIG1 (0x05)
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#define PM800_GPADC_MISC_CONFIG2 (0x06)
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#define PM800_GPADC_MISC_GPFSM_EN (1 << 0)
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#define PM800_GPADC_MISC_GPFSM_EN BIT(0)
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#define PM800_GPADC_SLOW_MODE(x) (x << 3)
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#define PM800_GPADC_MISC_CONFIG3 (0x09)
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@ -162,16 +162,16 @@ enum {
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#define PM800_GPADC_PREBIAS2 (0x10)
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#define PM800_GP_BIAS_ENA1 (0x14)
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#define PM800_GPADC_GP_BIAS_EN0 (1 << 0)
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#define PM800_GPADC_GP_BIAS_EN1 (1 << 1)
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#define PM800_GPADC_GP_BIAS_EN2 (1 << 2)
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#define PM800_GPADC_GP_BIAS_EN3 (1 << 3)
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#define PM800_GPADC_GP_BIAS_EN0 BIT(0)
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#define PM800_GPADC_GP_BIAS_EN1 BIT(1)
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#define PM800_GPADC_GP_BIAS_EN2 BIT(2)
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#define PM800_GPADC_GP_BIAS_EN3 BIT(3)
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#define PM800_GP_BIAS_OUT1 (0x15)
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#define PM800_BIAS_OUT_GP0 (1 << 0)
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#define PM800_BIAS_OUT_GP1 (1 << 1)
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#define PM800_BIAS_OUT_GP2 (1 << 2)
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#define PM800_BIAS_OUT_GP3 (1 << 3)
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#define PM800_BIAS_OUT_GP0 BIT(0)
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#define PM800_BIAS_OUT_GP1 BIT(1)
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#define PM800_BIAS_OUT_GP2 BIT(2)
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#define PM800_BIAS_OUT_GP3 BIT(3)
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#define PM800_GPADC0_LOW_TH 0x20
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#define PM800_GPADC1_LOW_TH 0x21
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@ -222,31 +222,31 @@ enum {
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#define PM805_INT_STATUS1 (0x03)
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#define PM805_INT1_HP1_SHRT (1 << 0)
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#define PM805_INT1_HP2_SHRT (1 << 1)
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#define PM805_INT1_MIC_CONFLICT (1 << 2)
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#define PM805_INT1_CLIP_FAULT (1 << 3)
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#define PM805_INT1_LDO_OFF (1 << 4)
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#define PM805_INT1_SRC_DPLL_LOCK (1 << 5)
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#define PM805_INT1_HP1_SHRT BIT(0)
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#define PM805_INT1_HP2_SHRT BIT(1)
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#define PM805_INT1_MIC_CONFLICT BIT(2)
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#define PM805_INT1_CLIP_FAULT BIT(3)
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#define PM805_INT1_LDO_OFF BIT(4)
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#define PM805_INT1_SRC_DPLL_LOCK BIT(5)
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#define PM805_INT_STATUS2 (0x04)
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#define PM805_INT2_MIC_DET (1 << 0)
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#define PM805_INT2_SHRT_BTN_DET (1 << 1)
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#define PM805_INT2_VOLM_BTN_DET (1 << 2)
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#define PM805_INT2_VOLP_BTN_DET (1 << 3)
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#define PM805_INT2_RAW_PLL_FAULT (1 << 4)
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#define PM805_INT2_FINE_PLL_FAULT (1 << 5)
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#define PM805_INT2_MIC_DET BIT(0)
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#define PM805_INT2_SHRT_BTN_DET BIT(1)
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#define PM805_INT2_VOLM_BTN_DET BIT(2)
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#define PM805_INT2_VOLP_BTN_DET BIT(3)
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#define PM805_INT2_RAW_PLL_FAULT BIT(4)
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#define PM805_INT2_FINE_PLL_FAULT BIT(5)
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#define PM805_INT_MASK1 (0x05)
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#define PM805_INT_MASK2 (0x06)
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#define PM805_SHRT_BTN_DET (1 << 1)
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#define PM805_SHRT_BTN_DET BIT(1)
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/* number of status and int reg in a row */
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#define PM805_INT_REG_NUM (2)
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#define PM805_MIC_DET1 (0x07)
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#define PM805_MIC_DET_EN_MIC_DET (1 << 0)
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#define PM805_MIC_DET_EN_MIC_DET BIT(0)
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#define PM805_MIC_DET2 (0x08)
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#define PM805_MIC_DET_STATUS1 (0x09)
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