scsi: hpsa: use pci_alloc_irq_vectors and automatic irq affinity
This patch converts over hpsa to use the pci_alloc_irq_vectors including the PCI_IRQ_AFFINITY flag that automatically assigns spread out irq affinity to the I/O queues. It also cleans up the per-ctrl interrupt state due to the use of the pci_irq_vector and pci_free_irq_vectors helpers that don't need to know the exact irq type. Additionally it changes a little oddity in the existing code that was using different array indixes into the per-vector arrays depending on whether a controller is using a single INTx or single MSI irq. [mkp: fixed typo] Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Don Brace <don.brace@microsemi.com> Tested-by: Don Brace <don.brace@microsemi.com> Reviewed-by: Hannes Reinecke <hare@suse.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Christoph Hellwig
Martin K. Petersen
parent
4861ee15f2
commit
bc2bb1543e
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@ -1001,7 +1001,7 @@ static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
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{
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if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
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c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
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if (unlikely(!h->msix_vector))
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if (unlikely(!h->msix_vectors))
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return;
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if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
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c->Header.ReplyQueue =
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@ -5618,7 +5618,7 @@ static int hpsa_scsi_host_alloc(struct ctlr_info *h)
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sh->sg_tablesize = h->maxsgentries;
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sh->transportt = hpsa_sas_transport_template;
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sh->hostdata[0] = (unsigned long) h;
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sh->irq = h->intr[h->intr_mode];
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sh->irq = pci_irq_vector(h->pdev, 0);
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sh->unique_id = sh->irq;
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h->scsi_host = sh;
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@ -7651,67 +7651,41 @@ static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
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static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
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{
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if (h->msix_vector) {
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if (h->pdev->msix_enabled)
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pci_disable_msix(h->pdev);
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h->msix_vector = 0;
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} else if (h->msi_vector) {
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if (h->pdev->msi_enabled)
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pci_disable_msi(h->pdev);
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h->msi_vector = 0;
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}
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pci_free_irq_vectors(h->pdev);
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h->msix_vectors = 0;
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}
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/* If MSI/MSI-X is supported by the kernel we will try to enable it on
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* controllers that are capable. If not, we use legacy INTx mode.
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*/
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static void hpsa_interrupt_mode(struct ctlr_info *h)
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static int hpsa_interrupt_mode(struct ctlr_info *h)
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{
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#ifdef CONFIG_PCI_MSI
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int err, i;
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struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
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for (i = 0; i < MAX_REPLY_QUEUES; i++) {
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hpsa_msix_entries[i].vector = 0;
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hpsa_msix_entries[i].entry = i;
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}
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unsigned int flags = PCI_IRQ_LEGACY;
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int ret;
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/* Some boards advertise MSI but don't really support it */
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if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
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(h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
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goto default_int_mode;
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if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
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dev_info(&h->pdev->dev, "MSI-X capable controller\n");
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h->msix_vector = MAX_REPLY_QUEUES;
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if (h->msix_vector > num_online_cpus())
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h->msix_vector = num_online_cpus();
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err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
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1, h->msix_vector);
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if (err < 0) {
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dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
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h->msix_vector = 0;
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goto single_msi_mode;
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} else if (err < h->msix_vector) {
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dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
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"available\n", err);
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switch (h->board_id) {
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case 0x40700E11:
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case 0x40800E11:
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case 0x40820E11:
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case 0x40830E11:
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break;
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default:
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ret = pci_alloc_irq_vectors(h->pdev, 1, MAX_REPLY_QUEUES,
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PCI_IRQ_MSIX | PCI_IRQ_AFFINITY);
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if (ret > 0) {
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h->msix_vectors = ret;
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return 0;
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}
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h->msix_vector = err;
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for (i = 0; i < h->msix_vector; i++)
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h->intr[i] = hpsa_msix_entries[i].vector;
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return;
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flags |= PCI_IRQ_MSI;
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break;
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}
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single_msi_mode:
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if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
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dev_info(&h->pdev->dev, "MSI capable controller\n");
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if (!pci_enable_msi(h->pdev))
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h->msi_vector = 1;
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else
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dev_warn(&h->pdev->dev, "MSI init failed\n");
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}
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default_int_mode:
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#endif /* CONFIG_PCI_MSI */
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/* if we get here we're going to use the default interrupt mode */
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h->intr[h->intr_mode] = h->pdev->irq;
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ret = pci_alloc_irq_vectors(h->pdev, 1, 1, flags);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
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@ -8067,7 +8041,9 @@ static int hpsa_pci_init(struct ctlr_info *h)
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pci_set_master(h->pdev);
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hpsa_interrupt_mode(h);
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err = hpsa_interrupt_mode(h);
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if (err)
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goto clean1;
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err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
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if (err)
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goto clean2; /* intmode+region, pci */
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@ -8103,6 +8079,7 @@ static int hpsa_pci_init(struct ctlr_info *h)
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h->vaddr = NULL;
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clean2: /* intmode+region, pci */
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hpsa_disable_interrupt_mode(h);
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clean1:
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/*
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* call pci_disable_device before pci_release_regions per
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* Documentation/PCI/pci.txt
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@ -8236,34 +8213,20 @@ static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
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return -ENOMEM;
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}
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static void hpsa_irq_affinity_hints(struct ctlr_info *h)
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{
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int i, cpu;
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cpu = cpumask_first(cpu_online_mask);
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for (i = 0; i < h->msix_vector; i++) {
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irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
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cpu = cpumask_next(cpu, cpu_online_mask);
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}
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}
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/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
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static void hpsa_free_irqs(struct ctlr_info *h)
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{
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int i;
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if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
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if (!h->msix_vectors || h->intr_mode != PERF_MODE_INT) {
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/* Single reply queue, only one irq to free */
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i = h->intr_mode;
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irq_set_affinity_hint(h->intr[i], NULL);
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free_irq(h->intr[i], &h->q[i]);
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h->q[i] = 0;
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free_irq(pci_irq_vector(h->pdev, 0), &h->q[i]);
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h->q[h->intr_mode] = 0;
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return;
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}
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for (i = 0; i < h->msix_vector; i++) {
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irq_set_affinity_hint(h->intr[i], NULL);
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free_irq(h->intr[i], &h->q[i]);
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for (i = 0; i < h->msix_vectors; i++) {
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free_irq(pci_irq_vector(h->pdev, i), &h->q[i]);
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h->q[i] = 0;
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}
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for (; i < MAX_REPLY_QUEUES; i++)
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@ -8284,11 +8247,11 @@ static int hpsa_request_irqs(struct ctlr_info *h,
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for (i = 0; i < MAX_REPLY_QUEUES; i++)
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h->q[i] = (u8) i;
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if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
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if (h->intr_mode == PERF_MODE_INT && h->msix_vectors > 0) {
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/* If performant mode and MSI-X, use multiple reply queues */
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for (i = 0; i < h->msix_vector; i++) {
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for (i = 0; i < h->msix_vectors; i++) {
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sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
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rc = request_irq(h->intr[i], msixhandler,
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rc = request_irq(pci_irq_vector(h->pdev, i), msixhandler,
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0, h->intrname[i],
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&h->q[i]);
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if (rc) {
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@ -8296,9 +8259,9 @@ static int hpsa_request_irqs(struct ctlr_info *h,
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dev_err(&h->pdev->dev,
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"failed to get irq %d for %s\n",
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h->intr[i], h->devname);
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pci_irq_vector(h->pdev, i), h->devname);
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for (j = 0; j < i; j++) {
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free_irq(h->intr[j], &h->q[j]);
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free_irq(pci_irq_vector(h->pdev, j), &h->q[j]);
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h->q[j] = 0;
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}
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for (; j < MAX_REPLY_QUEUES; j++)
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@ -8306,33 +8269,27 @@ static int hpsa_request_irqs(struct ctlr_info *h,
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return rc;
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}
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}
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hpsa_irq_affinity_hints(h);
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} else {
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/* Use single reply pool */
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if (h->msix_vector > 0 || h->msi_vector) {
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if (h->msix_vector)
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sprintf(h->intrname[h->intr_mode],
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"%s-msix", h->devname);
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else
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sprintf(h->intrname[h->intr_mode],
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"%s-msi", h->devname);
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rc = request_irq(h->intr[h->intr_mode],
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if (h->msix_vectors > 0 || h->pdev->msi_enabled) {
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sprintf(h->intrname[0], "%s-msi%s", h->devname,
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h->msix_vectors ? "x" : "");
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rc = request_irq(pci_irq_vector(h->pdev, 0),
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msixhandler, 0,
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h->intrname[h->intr_mode],
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h->intrname[0],
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&h->q[h->intr_mode]);
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} else {
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sprintf(h->intrname[h->intr_mode],
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"%s-intx", h->devname);
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rc = request_irq(h->intr[h->intr_mode],
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rc = request_irq(pci_irq_vector(h->pdev, 0),
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intxhandler, IRQF_SHARED,
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h->intrname[h->intr_mode],
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h->intrname[0],
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&h->q[h->intr_mode]);
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}
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irq_set_affinity_hint(h->intr[h->intr_mode], NULL);
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}
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if (rc) {
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dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
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h->intr[h->intr_mode], h->devname);
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pci_irq_vector(h->pdev, 0), h->devname);
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hpsa_free_irqs(h);
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return -ENODEV;
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}
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@ -9518,7 +9475,7 @@ static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
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return rc;
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}
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h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
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h->nreply_queues = h->msix_vectors > 0 ? h->msix_vectors : 1;
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hpsa_get_max_perf_mode_cmds(h);
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/* Performant mode ring buffer and supporting data structures */
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h->reply_queue_size = h->max_commands * sizeof(u64);
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@ -175,9 +175,7 @@ struct ctlr_info {
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# define DOORBELL_INT 1
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# define SIMPLE_MODE_INT 2
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# define MEMQ_MODE_INT 3
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unsigned int intr[MAX_REPLY_QUEUES];
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unsigned int msix_vector;
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unsigned int msi_vector;
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unsigned int msix_vectors;
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int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
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struct access_method access;
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@ -464,7 +462,7 @@ static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
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unsigned long register_value = FIFO_EMPTY;
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/* msi auto clears the interrupt pending bit. */
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if (unlikely(!(h->msi_vector || h->msix_vector))) {
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if (unlikely(!(h->pdev->msi_enabled || h->msix_vectors))) {
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/* flush the controller write of the reply queue by reading
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* outbound doorbell status register.
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*/
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