ASoC: Intel: bytcr_rt5640: Configure PLL1 before using it
When platform_clock_control() first selects PLL1 as sysclk the PLL_CTRL registers have not been setup yet and we effectively have an invalid clock configuration until byt_rt5640_aif1_hw_params() gets called. Add a new byt_rt5640_prepare_and_enable_pll1() helper and use that from both platform_clock_control() and byt_rt5640_aif1_hw_params() to fix this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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b16188a20f
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@ -141,6 +141,52 @@ static void log_quirks(struct device *dev)
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}
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}
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static int byt_rt5640_prepare_and_enable_pll1(struct snd_soc_dai *codec_dai,
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int rate)
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{
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int ret;
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/* Configure the PLL before selecting it */
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if (!(byt_rt5640_quirk & BYT_RT5640_MCLK_EN)) {
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/* use bitclock as PLL input */
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if ((byt_rt5640_quirk & BYT_RT5640_SSP0_AIF1) ||
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(byt_rt5640_quirk & BYT_RT5640_SSP0_AIF2)) {
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/* 2x16 bit slots on SSP0 */
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ret = snd_soc_dai_set_pll(codec_dai, 0,
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RT5640_PLL1_S_BCLK1,
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rate * 32, rate * 512);
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} else {
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/* 2x15 bit slots on SSP2 */
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ret = snd_soc_dai_set_pll(codec_dai, 0,
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RT5640_PLL1_S_BCLK1,
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rate * 50, rate * 512);
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}
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} else {
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if (byt_rt5640_quirk & BYT_RT5640_MCLK_25MHZ) {
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ret = snd_soc_dai_set_pll(codec_dai, 0,
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RT5640_PLL1_S_MCLK,
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25000000, rate * 512);
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} else {
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ret = snd_soc_dai_set_pll(codec_dai, 0,
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RT5640_PLL1_S_MCLK,
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19200000, rate * 512);
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}
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}
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if (ret < 0) {
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dev_err(codec_dai->codec->dev, "can't set pll: %d\n", ret);
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return ret;
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}
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ret = snd_soc_dai_set_sysclk(codec_dai, RT5640_SCLK_S_PLL1,
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rate * 512, SND_SOC_CLOCK_IN);
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if (ret < 0) {
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dev_err(codec_dai->codec->dev, "can't set clock %d\n", ret);
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return ret;
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}
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return 0;
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}
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#define BYT_CODEC_DAI1 "rt5640-aif1"
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#define BYT_CODEC_DAI2 "rt5640-aif2"
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@ -173,9 +219,7 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w,
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return ret;
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}
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}
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ret = snd_soc_dai_set_sysclk(codec_dai, RT5640_SCLK_S_PLL1,
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48000 * 512,
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SND_SOC_CLOCK_IN);
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ret = byt_rt5640_prepare_and_enable_pll1(codec_dai, 48000);
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} else {
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/*
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* Set codec clock source to internal clock before
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@ -299,55 +343,9 @@ static int byt_rt5640_aif1_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_dai *codec_dai = rtd->codec_dai;
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int ret;
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struct snd_soc_dai *dai = rtd->codec_dai;
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ret = snd_soc_dai_set_sysclk(codec_dai, RT5640_SCLK_S_PLL1,
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params_rate(params) * 512,
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SND_SOC_CLOCK_IN);
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if (ret < 0) {
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dev_err(rtd->dev, "can't set codec clock %d\n", ret);
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return ret;
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}
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if (!(byt_rt5640_quirk & BYT_RT5640_MCLK_EN)) {
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/* use bitclock as PLL input */
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if ((byt_rt5640_quirk & BYT_RT5640_SSP0_AIF1) ||
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(byt_rt5640_quirk & BYT_RT5640_SSP0_AIF2)) {
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/* 2x16 bit slots on SSP0 */
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ret = snd_soc_dai_set_pll(codec_dai, 0,
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RT5640_PLL1_S_BCLK1,
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params_rate(params) * 32,
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params_rate(params) * 512);
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} else {
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/* 2x15 bit slots on SSP2 */
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ret = snd_soc_dai_set_pll(codec_dai, 0,
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RT5640_PLL1_S_BCLK1,
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params_rate(params) * 50,
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params_rate(params) * 512);
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}
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} else {
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if (byt_rt5640_quirk & BYT_RT5640_MCLK_25MHZ) {
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ret = snd_soc_dai_set_pll(codec_dai, 0,
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RT5640_PLL1_S_MCLK,
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25000000,
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params_rate(params) * 512);
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} else {
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ret = snd_soc_dai_set_pll(codec_dai, 0,
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RT5640_PLL1_S_MCLK,
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19200000,
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params_rate(params) * 512);
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}
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}
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if (ret < 0) {
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dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
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return ret;
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}
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return 0;
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return byt_rt5640_prepare_and_enable_pll1(dai, params_rate(params));
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}
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static int byt_rt5640_quirk_cb(const struct dmi_system_id *id)
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