arm64 fixes and cpucaps.h automatic generation:
- Generate cpucaps.h at build time rather than carrying lots of
#defines. Merged at -rc1 to avoid some conflicts during the merging
window.
- Initialise RGSR_EL1.SEED in __cpu_setup() as it may be left as 0 out
of reset and the IRG instruction would not function as expected if
only the architected pseudorandom number generator is implemented.
- Fix potential race condition in __sync_icache_dcache() where the
PG_dcache_clean page flag is set before the actual cache maintenance.
- Fix header include in BTI kselftests.
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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fixes from Catalin Marinas:
"Fixes and cpucaps.h automatic generation:
- Generate cpucaps.h at build time rather than carrying lots of
#defines. Merged at -rc1 to avoid some conflicts during the merge
window.
- Initialise RGSR_EL1.SEED in __cpu_setup() as it may be left as 0
out of reset and the IRG instruction would not function as expected
if only the architected pseudorandom number generator is
implemented.
- Fix potential race condition in __sync_icache_dcache() where the
PG_dcache_clean page flag is set before the actual cache
maintenance.
- Fix header include in BTI kselftests"
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: Fix race condition on PG_dcache_clean in __sync_icache_dcache()
arm64: tools: Add __ASM_CPUCAPS_H to the endif in cpucaps.h
arm64: mte: initialize RGSR_EL1.SEED in __cpu_setup
kselftest/arm64: Add missing stddef.h include to BTI tests
arm64: Generate cpucaps.h
This commit is contained in:
Linus Torvalds
commit
bd3c9cdb21
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@ -175,6 +175,9 @@ vdso_install:
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$(if $(CONFIG_COMPAT_VDSO), \
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$(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso32 $@)
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archprepare:
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$(Q)$(MAKE) $(build)=arch/arm64/tools kapi
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# We use MRPROPER_FILES and CLEAN_FILES now
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archclean:
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$(Q)$(MAKE) $(clean)=$(boot)
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@ -5,3 +5,5 @@ generic-y += qrwlock.h
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generic-y += qspinlock.h
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generic-y += set_memory.h
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generic-y += user.h
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generated-y += cpucaps.h
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@ -1,74 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* arch/arm64/include/asm/cpucaps.h
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*
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* Copyright (C) 2016 ARM Ltd.
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*/
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#ifndef __ASM_CPUCAPS_H
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#define __ASM_CPUCAPS_H
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#define ARM64_WORKAROUND_CLEAN_CACHE 0
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#define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1
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#define ARM64_WORKAROUND_845719 2
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#define ARM64_HAS_SYSREG_GIC_CPUIF 3
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#define ARM64_HAS_PAN 4
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#define ARM64_HAS_LSE_ATOMICS 5
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#define ARM64_WORKAROUND_CAVIUM_23154 6
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#define ARM64_WORKAROUND_834220 7
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#define ARM64_HAS_NO_HW_PREFETCH 8
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#define ARM64_HAS_VIRT_HOST_EXTN 11
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#define ARM64_WORKAROUND_CAVIUM_27456 12
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#define ARM64_HAS_32BIT_EL0 13
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#define ARM64_SPECTRE_V3A 14
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#define ARM64_HAS_CNP 15
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#define ARM64_HAS_NO_FPSIMD 16
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#define ARM64_WORKAROUND_REPEAT_TLBI 17
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#define ARM64_WORKAROUND_QCOM_FALKOR_E1003 18
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#define ARM64_WORKAROUND_858921 19
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#define ARM64_WORKAROUND_CAVIUM_30115 20
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#define ARM64_HAS_DCPOP 21
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#define ARM64_SVE 22
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#define ARM64_UNMAP_KERNEL_AT_EL0 23
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#define ARM64_SPECTRE_V2 24
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#define ARM64_HAS_RAS_EXTN 25
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#define ARM64_WORKAROUND_843419 26
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#define ARM64_HAS_CACHE_IDC 27
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#define ARM64_HAS_CACHE_DIC 28
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#define ARM64_HW_DBM 29
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#define ARM64_SPECTRE_V4 30
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#define ARM64_MISMATCHED_CACHE_TYPE 31
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#define ARM64_HAS_STAGE2_FWB 32
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#define ARM64_HAS_CRC32 33
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#define ARM64_SSBS 34
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#define ARM64_WORKAROUND_1418040 35
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#define ARM64_HAS_SB 36
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#define ARM64_WORKAROUND_SPECULATIVE_AT 37
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#define ARM64_HAS_ADDRESS_AUTH_ARCH 38
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#define ARM64_HAS_ADDRESS_AUTH_IMP_DEF 39
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#define ARM64_HAS_GENERIC_AUTH_ARCH 40
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#define ARM64_HAS_GENERIC_AUTH_IMP_DEF 41
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#define ARM64_HAS_IRQ_PRIO_MASKING 42
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#define ARM64_HAS_DCPODP 43
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#define ARM64_WORKAROUND_1463225 44
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#define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM 45
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#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 46
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#define ARM64_WORKAROUND_1542419 47
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#define ARM64_HAS_E0PD 48
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#define ARM64_HAS_RNG 49
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#define ARM64_HAS_AMU_EXTN 50
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#define ARM64_HAS_ADDRESS_AUTH 51
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#define ARM64_HAS_GENERIC_AUTH 52
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#define ARM64_HAS_32BIT_EL1 53
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#define ARM64_BTI 54
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#define ARM64_HAS_ARMv8_4_TTL 55
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#define ARM64_HAS_TLB_RANGE 56
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#define ARM64_MTE 57
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#define ARM64_WORKAROUND_1508412 58
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#define ARM64_HAS_LDAPR 59
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#define ARM64_KVM_PROTECTED_MODE 60
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#define ARM64_WORKAROUND_NVIDIA_CARMEL_CNP 61
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#define ARM64_HAS_EPAN 62
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#define ARM64_NCAPS 63
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#endif /* __ASM_CPUCAPS_H */
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@ -55,8 +55,10 @@ void __sync_icache_dcache(pte_t pte)
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{
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struct page *page = pte_page(pte);
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if (!test_and_set_bit(PG_dcache_clean, &page->flags))
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if (!test_bit(PG_dcache_clean, &page->flags)) {
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sync_icache_aliases(page_address(page), page_size(page));
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set_bit(PG_dcache_clean, &page->flags);
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}
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}
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EXPORT_SYMBOL_GPL(__sync_icache_dcache);
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@ -447,6 +447,18 @@ SYM_FUNC_START(__cpu_setup)
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mov x10, #(SYS_GCR_EL1_RRND | SYS_GCR_EL1_EXCL_MASK)
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msr_s SYS_GCR_EL1, x10
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/*
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* If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then
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* RGSR_EL1.SEED must be non-zero for IRG to produce
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* pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we
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* must initialize it.
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*/
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mrs x10, CNTVCT_EL0
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ands x10, x10, #SYS_RGSR_EL1_SEED_MASK
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csinc x10, x10, xzr, ne
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lsl x10, x10, #SYS_RGSR_EL1_SEED_SHIFT
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msr_s SYS_RGSR_EL1, x10
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/* clear any pending tag check faults in TFSR*_EL1 */
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msr_s SYS_TFSR_EL1, xzr
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msr_s SYS_TFSRE0_EL1, xzr
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@ -0,0 +1,22 @@
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# SPDX-License-Identifier: GPL-2.0
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gen := arch/$(ARCH)/include/generated
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kapi := $(gen)/asm
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kapi-hdrs-y := $(kapi)/cpucaps.h
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targets += $(addprefix ../../../,$(gen-y) $(kapi-hdrs-y))
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PHONY += kapi
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kapi: $(kapi-hdrs-y) $(gen-y)
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# Create output directory if not already present
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_dummy := $(shell [ -d '$(kapi)' ] || mkdir -p '$(kapi)')
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quiet_cmd_gen_cpucaps = GEN $@
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cmd_gen_cpucaps = mkdir -p $(dir $@) && \
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$(AWK) -f $(filter-out $(PHONY),$^) > $@
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$(kapi)/cpucaps.h: $(src)/gen-cpucaps.awk $(src)/cpucaps FORCE
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$(call if_changed,gen_cpucaps)
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@ -0,0 +1,65 @@
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# SPDX-License-Identifier: GPL-2.0
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#
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# Internal CPU capabilities constants, keep this list sorted
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BTI
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HAS_32BIT_EL0
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HAS_32BIT_EL1
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HAS_ADDRESS_AUTH
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HAS_ADDRESS_AUTH_ARCH
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HAS_ADDRESS_AUTH_IMP_DEF
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HAS_AMU_EXTN
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HAS_ARMv8_4_TTL
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HAS_CACHE_DIC
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HAS_CACHE_IDC
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HAS_CNP
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HAS_CRC32
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HAS_DCPODP
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HAS_DCPOP
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HAS_E0PD
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HAS_EPAN
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HAS_GENERIC_AUTH
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HAS_GENERIC_AUTH_ARCH
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HAS_GENERIC_AUTH_IMP_DEF
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HAS_IRQ_PRIO_MASKING
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HAS_LDAPR
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HAS_LSE_ATOMICS
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HAS_NO_FPSIMD
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HAS_NO_HW_PREFETCH
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HAS_PAN
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HAS_RAS_EXTN
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HAS_RNG
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HAS_SB
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HAS_STAGE2_FWB
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HAS_SYSREG_GIC_CPUIF
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HAS_TLB_RANGE
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HAS_VIRT_HOST_EXTN
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HW_DBM
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KVM_PROTECTED_MODE
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MISMATCHED_CACHE_TYPE
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MTE
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SPECTRE_V2
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SPECTRE_V3A
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SPECTRE_V4
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SSBS
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SVE
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UNMAP_KERNEL_AT_EL0
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WORKAROUND_834220
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WORKAROUND_843419
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WORKAROUND_845719
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WORKAROUND_858921
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WORKAROUND_1418040
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WORKAROUND_1463225
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WORKAROUND_1508412
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WORKAROUND_1542419
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WORKAROUND_CAVIUM_23154
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WORKAROUND_CAVIUM_27456
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WORKAROUND_CAVIUM_30115
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WORKAROUND_CAVIUM_TX2_219_PRFM
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WORKAROUND_CAVIUM_TX2_219_TVM
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WORKAROUND_CLEAN_CACHE
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WORKAROUND_DEVICE_LOAD_ACQUIRE
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WORKAROUND_NVIDIA_CARMEL_CNP
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WORKAROUND_QCOM_FALKOR_E1003
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WORKAROUND_REPEAT_TLBI
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WORKAROUND_SPECULATIVE_AT
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@ -0,0 +1,40 @@
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#!/bin/awk -f
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# SPDX-License-Identifier: GPL-2.0
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# gen-cpucaps.awk: arm64 cpucaps header generator
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#
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# Usage: awk -f gen-cpucaps.awk cpucaps.txt
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# Log an error and terminate
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function fatal(msg) {
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print "Error at line " NR ": " msg > "/dev/stderr"
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exit 1
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}
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# skip blank lines and comment lines
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/^$/ { next }
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/^#/ { next }
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BEGIN {
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print "#ifndef __ASM_CPUCAPS_H"
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print "#define __ASM_CPUCAPS_H"
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print ""
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print "/* Generated file - do not edit */"
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cap_num = 0
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print ""
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}
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/^[vA-Z0-9_]+$/ {
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printf("#define ARM64_%-30s\t%d\n", $0, cap_num++)
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next
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}
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END {
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printf("#define ARM64_NCAPS\t\t\t\t%d\n", cap_num)
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print ""
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print "#endif /* __ASM_CPUCAPS_H */"
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}
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# Any lines not handled by previous rules are unexpected
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{
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fatal("unhandled statement")
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}
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@ -6,6 +6,7 @@
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#include "system.h"
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#include <stddef.h>
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#include <linux/errno.h>
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#include <linux/auxvec.h>
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#include <linux/signal.h>
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