i2c: designware: 10-bit addressing mode enabling if I2C_DYNAMIC_TAR_UPDATE is set
According to Designware I2C spec, if I2C_DYNAMIC_TAR_UPDATE is set to 1, the 10-bit addressing mode is controlled by IC_10BITADDR_MASTER bit of IC_TAR register instead of IC_CON register. The IC_10BITADDR_MASTER in IC_CON register becomes read-only copy. Since I2C_DYNAMIC_TAR_UPDATE value can't be detected from hardware register, so we will always set the IC_10BITADDR_MASTER bit in both IC_CON and IC_TAR register whenever 10-bit addresing mode is requested by user application. Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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@ -98,6 +98,8 @@
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#define DW_IC_ERR_TX_ABRT 0x1
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#define DW_IC_TAR_10BITADDR_MASTER BIT(12)
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/*
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* status codes
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*/
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@ -388,22 +390,34 @@ static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
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static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
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{
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struct i2c_msg *msgs = dev->msgs;
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u32 ic_con;
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u32 ic_con, ic_tar = 0;
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/* Disable the adapter */
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__i2c_dw_enable(dev, false);
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/* set the slave (target) address */
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dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR);
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/* if the slave address is ten bit address, enable 10BITADDR */
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ic_con = dw_readl(dev, DW_IC_CON);
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if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
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if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
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ic_con |= DW_IC_CON_10BITADDR_MASTER;
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else
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/*
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* If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
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* mode has to be enabled via bit 12 of IC_TAR register.
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* We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
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* detected from registers.
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*/
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ic_tar = DW_IC_TAR_10BITADDR_MASTER;
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} else {
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ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
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}
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dw_writel(dev, ic_con, DW_IC_CON);
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/*
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* Set the slave (target) address and enable 10-bit addressing mode
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* if applicable.
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*/
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dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
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/* Enable the adapter */
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__i2c_dw_enable(dev, true);
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