arm64: dts: clearfog-gt-8k: fix SGMII PHY reset signal
The PHY reset signal goes to mpp43 on CP0.
Fixes: babc5544c2
("arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal")
Reported-by: Denis Odintsov <oversun@me.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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@ -351,7 +351,7 @@ ge_phy: ethernet-phy@0 {
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_copper_eth_phy_reset>;
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reset-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
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reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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};
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