Merge branch 'clk-hikey' into clk-next
* clk-hikey: clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu' clk: hisilicon: Delete an error message for a failed memory allocation in hisi_register_clkgate_sep() clk: hi3660: fix incorrect uart3 clock freqency clk: hi6220: mark clock cs_atb_syspll as critical
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commit
bdf6bfb378
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@ -34,7 +34,7 @@ static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = {
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/* crgctrl */
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/* crgctrl */
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static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = {
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static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = {
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{ HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 8, 0, },
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{ HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 16, 0, },
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{ HI3660_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys", 1, 6, 0, },
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{ HI3660_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys", 1, 6, 0, },
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{ HI3660_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_iomcu", 1, 4, 0, },
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{ HI3660_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_iomcu", 1, 4, 0, },
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{ HI3660_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_iomcu", 1, 4, 0, },
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{ HI3660_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_iomcu", 1, 4, 0, },
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@ -145,7 +145,7 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = {
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{ HI6220_BBPPLL_SEL, "bbppll_sel", "pll0_bbp_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 9, 0, },
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{ HI6220_BBPPLL_SEL, "bbppll_sel", "pll0_bbp_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 9, 0, },
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{ HI6220_MEDIA_PLL_SRC, "media_pll_src", "pll_media_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 10, 0, },
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{ HI6220_MEDIA_PLL_SRC, "media_pll_src", "pll_media_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 10, 0, },
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{ HI6220_MMC2_SEL, "mmc2_sel", "mmc2_mux1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 11, 0, },
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{ HI6220_MMC2_SEL, "mmc2_sel", "mmc2_mux1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 11, 0, },
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{ HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 12, 0, },
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{ HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IS_CRITICAL, 0x270, 12, 0, },
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};
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};
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static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata = {
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static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata = {
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@ -105,10 +105,8 @@ struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name,
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struct clk_init_data init;
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struct clk_init_data init;
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sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
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sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
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if (!sclk) {
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if (!sclk)
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pr_err("%s: fail to allocate separated gated clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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init.name = name;
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init.ops = &clkgate_separated_ops;
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init.ops = &clkgate_separated_ops;
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@ -47,6 +47,8 @@
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#define HI3798CV200_FIXED_12M 81
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#define HI3798CV200_FIXED_12M 81
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#define HI3798CV200_FIXED_48M 82
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#define HI3798CV200_FIXED_48M 82
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#define HI3798CV200_FIXED_60M 83
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#define HI3798CV200_FIXED_60M 83
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#define HI3798CV200_FIXED_166P5M 84
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#define HI3798CV200_SDIO0_MUX 85
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#define HI3798CV200_CRG_NR_CLKS 128
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#define HI3798CV200_CRG_NR_CLKS 128
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@ -63,6 +65,7 @@ static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = {
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{ HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
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{ HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
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{ HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },
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{ HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },
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{ HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },
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{ HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },
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{ HI3798CV200_FIXED_166P5M, "166p5m", NULL, 0, 165000000, },
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{ HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, },
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{ HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, },
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{ HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, },
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{ HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, },
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};
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};
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@ -75,12 +78,19 @@ static const char *const comphy1_mux_p[] = {
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"100m", "25m"};
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"100m", "25m"};
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static u32 comphy1_mux_table[] = {2, 3};
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static u32 comphy1_mux_table[] = {2, 3};
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static const char *const sdio_mux_p[] = {
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"100m", "50m", "150m", "166p5m" };
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static u32 sdio_mux_table[] = {0, 1, 2, 3};
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static struct hisi_mux_clock hi3798cv200_mux_clks[] = {
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static struct hisi_mux_clock hi3798cv200_mux_clks[] = {
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{ HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
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{ HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
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CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
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CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
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{ HI3798CV200_COMBPHY1_MUX, "combphy1_mux",
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{ HI3798CV200_COMBPHY1_MUX, "combphy1_mux",
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comphy1_mux_p, ARRAY_SIZE(comphy1_mux_p),
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comphy1_mux_p, ARRAY_SIZE(comphy1_mux_p),
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CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy1_mux_table, },
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CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy1_mux_table, },
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{ HI3798CV200_SDIO0_MUX, "sdio0_mux", sdio_mux_p,
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ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT,
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0x9c, 8, 2, 0, sdio_mux_table, },
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};
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};
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static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
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static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
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@ -104,7 +114,7 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
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/* SDIO */
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/* SDIO */
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{ HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m",
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{ HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m",
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CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
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CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
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{ HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "mmc_mux",
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{ HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "sdio0_mux",
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CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
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CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
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/* EMMC */
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/* EMMC */
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{ HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m",
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{ HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m",
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