drm/i915/gvt: vGPU command scanner
This patch introduces a command scanner to scan guest command buffers. Signed-off-by: Yulei Zhang <yulei.zhang@intel.com> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
This commit is contained in:
Zhi Wang
Zhenyu Wang
parent
1786571393
commit
be1da7070a
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@ -1,7 +1,7 @@
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GVT_DIR := gvt
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GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
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interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
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execlist.o scheduler.o sched_policy.o render.o
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execlist.o scheduler.o sched_policy.o render.o cmd_parser.o
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ccflags-y += -I$(src) -I$(src)/$(GVT_DIR) -Wall
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i915-y += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,49 @@
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/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Ke Yu
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* Kevin Tian <kevin.tian@intel.com>
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* Zhiyuan Lv <zhiyuan.lv@intel.com>
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*
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* Contributors:
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* Min He <min.he@intel.com>
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* Ping Gao <ping.a.gao@intel.com>
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* Tina Zhang <tina.zhang@intel.com>
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* Yulei Zhang <yulei.zhang@intel.com>
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* Zhi Wang <zhi.a.wang@intel.com>
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*
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*/
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#ifndef _GVT_CMD_PARSER_H_
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#define _GVT_CMD_PARSER_H_
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#define GVT_CMD_HASH_BITS 7
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void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt);
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int intel_gvt_init_cmd_parser(struct intel_gvt *gvt);
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int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload);
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int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx);
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#endif
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@ -51,4 +51,7 @@
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#define gvt_dbg_render(fmt, args...) \
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DRM_DEBUG_DRIVER("gvt: render: "fmt, ##args)
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#define gvt_dbg_cmd(fmt, args...) \
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DRM_DEBUG_DRIVER("gvt: cmd: "fmt, ##args)
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#endif
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@ -363,6 +363,109 @@ static void free_workload(struct intel_vgpu_workload *workload)
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#define get_desc_from_elsp_dwords(ed, i) \
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((struct execlist_ctx_descriptor_format *)&((ed)->data[i * 2]))
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#define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
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#define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
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static int set_gma_to_bb_cmd(struct intel_shadow_bb_entry *entry_obj,
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unsigned long add, int gmadr_bytes)
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{
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if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8))
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return -1;
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*((u32 *)(entry_obj->bb_start_cmd_va + (1 << 2))) = add &
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BATCH_BUFFER_ADDR_MASK;
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if (gmadr_bytes == 8) {
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*((u32 *)(entry_obj->bb_start_cmd_va + (2 << 2))) =
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add & BATCH_BUFFER_ADDR_HIGH_MASK;
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}
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return 0;
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}
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static void prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
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{
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int gmadr_bytes = workload->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
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struct i915_vma *vma;
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unsigned long gma;
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/* pin the gem object to ggtt */
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if (!list_empty(&workload->shadow_bb)) {
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struct intel_shadow_bb_entry *entry_obj =
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list_first_entry(&workload->shadow_bb,
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struct intel_shadow_bb_entry,
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list);
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struct intel_shadow_bb_entry *temp;
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list_for_each_entry_safe(entry_obj, temp, &workload->shadow_bb,
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list) {
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vma = i915_gem_object_ggtt_pin(entry_obj->obj, NULL, 0,
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0, 0);
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if (IS_ERR(vma)) {
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gvt_err("Cannot pin\n");
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return;
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}
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i915_gem_object_unpin_pages(entry_obj->obj);
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/* update the relocate gma with shadow batch buffer*/
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gma = i915_gem_object_ggtt_offset(entry_obj->obj, NULL);
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WARN_ON(!IS_ALIGNED(gma, 4));
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set_gma_to_bb_cmd(entry_obj, gma, gmadr_bytes);
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}
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}
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}
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static int update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
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{
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int ring_id = wa_ctx->workload->ring_id;
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struct i915_gem_context *shadow_ctx =
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wa_ctx->workload->vgpu->shadow_ctx;
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struct drm_i915_gem_object *ctx_obj =
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shadow_ctx->engine[ring_id].state->obj;
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struct execlist_ring_context *shadow_ring_context;
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struct page *page;
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page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
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shadow_ring_context = kmap_atomic(page);
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shadow_ring_context->bb_per_ctx_ptr.val =
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(shadow_ring_context->bb_per_ctx_ptr.val &
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(~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma;
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shadow_ring_context->rcs_indirect_ctx.val =
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(shadow_ring_context->rcs_indirect_ctx.val &
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(~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma;
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kunmap_atomic(shadow_ring_context);
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return 0;
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}
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static void prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
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{
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struct i915_vma *vma;
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unsigned long gma;
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unsigned char *per_ctx_va =
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(unsigned char *)wa_ctx->indirect_ctx.shadow_va +
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wa_ctx->indirect_ctx.size;
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if (wa_ctx->indirect_ctx.size == 0)
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return;
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vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL, 0, 0, 0);
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if (IS_ERR(vma)) {
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gvt_err("Cannot pin indirect ctx obj\n");
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return;
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}
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i915_gem_object_unpin_pages(wa_ctx->indirect_ctx.obj);
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gma = i915_gem_object_ggtt_offset(wa_ctx->indirect_ctx.obj, NULL);
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WARN_ON(!IS_ALIGNED(gma, CACHELINE_BYTES));
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wa_ctx->indirect_ctx.shadow_gma = gma;
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wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1);
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memset(per_ctx_va, 0, CACHELINE_BYTES);
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update_wa_ctx_2_shadow_ctx(wa_ctx);
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}
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static int prepare_execlist_workload(struct intel_vgpu_workload *workload)
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{
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struct intel_vgpu *vgpu = workload->vgpu;
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@ -372,6 +475,8 @@ static int prepare_execlist_workload(struct intel_vgpu_workload *workload)
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intel_vgpu_pin_mm(workload->shadow_mm);
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intel_vgpu_sync_oos_pages(workload->vgpu);
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intel_vgpu_flush_post_shadow(workload->vgpu);
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prepare_shadow_batch_buffer(workload);
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prepare_shadow_wa_ctx(&workload->wa_ctx);
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if (!workload->emulate_schedule_in)
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return 0;
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@ -381,6 +486,35 @@ static int prepare_execlist_workload(struct intel_vgpu_workload *workload)
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return emulate_execlist_schedule_in(&vgpu->execlist[ring_id], ctx);
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}
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static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
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{
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/* release all the shadow batch buffer */
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if (!list_empty(&workload->shadow_bb)) {
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struct intel_shadow_bb_entry *entry_obj =
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list_first_entry(&workload->shadow_bb,
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struct intel_shadow_bb_entry,
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list);
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struct intel_shadow_bb_entry *temp;
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list_for_each_entry_safe(entry_obj, temp, &workload->shadow_bb,
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list) {
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drm_gem_object_unreference(&(entry_obj->obj->base));
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kvfree(entry_obj->va);
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list_del(&entry_obj->list);
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kfree(entry_obj);
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}
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}
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}
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static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
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{
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if (wa_ctx->indirect_ctx.size == 0)
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return;
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drm_gem_object_unreference(&(wa_ctx->indirect_ctx.obj->base));
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kvfree(wa_ctx->indirect_ctx.shadow_va);
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}
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static int complete_execlist_workload(struct intel_vgpu_workload *workload)
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{
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struct intel_vgpu *vgpu = workload->vgpu;
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@ -394,6 +528,9 @@ static int complete_execlist_workload(struct intel_vgpu_workload *workload)
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gvt_dbg_el("complete workload %p status %d\n", workload,
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workload->status);
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release_shadow_batch_buffer(workload);
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release_shadow_wa_ctx(&workload->wa_ctx);
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if (workload->status || vgpu->resetting)
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goto out;
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@ -487,7 +624,7 @@ bool submit_context(struct intel_vgpu *vgpu, int ring_id,
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struct intel_vgpu_workload *last_workload = get_last_workload(q);
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struct intel_vgpu_workload *workload = NULL;
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u64 ring_context_gpa;
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u32 head, tail, start, ctl, ctx_ctl;
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u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;
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int ret;
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ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
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@ -532,6 +669,7 @@ bool submit_context(struct intel_vgpu *vgpu, int ring_id,
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RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4);
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INIT_LIST_HEAD(&workload->list);
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INIT_LIST_HEAD(&workload->shadow_bb);
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init_waitqueue_head(&workload->shadow_ctx_status_wq);
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atomic_set(&workload->shadow_ctx_active, 0);
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@ -549,6 +687,24 @@ bool submit_context(struct intel_vgpu *vgpu, int ring_id,
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workload->status = -EINPROGRESS;
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workload->emulate_schedule_in = emulate_schedule_in;
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if (ring_id == RCS) {
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intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
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RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4);
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intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
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RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4);
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workload->wa_ctx.indirect_ctx.guest_gma =
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indirect_ctx & INDIRECT_CTX_ADDR_MASK;
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workload->wa_ctx.indirect_ctx.size =
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(indirect_ctx & INDIRECT_CTX_SIZE_MASK) *
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CACHELINE_BYTES;
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workload->wa_ctx.per_ctx.guest_gma =
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per_ctx & PER_CTX_ADDR_MASK;
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workload->wa_ctx.workload = workload;
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WARN_ON(workload->wa_ctx.indirect_ctx.size && !(per_ctx & 0x1));
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}
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if (emulate_schedule_in)
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memcpy(&workload->elsp_dwords,
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&vgpu->execlist[ring_id].elsp_dwords,
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@ -112,6 +112,8 @@ static void init_device_info(struct intel_gvt *gvt)
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info->gtt_start_offset = 8 * 1024 * 1024;
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info->gtt_entry_size = 8;
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info->gtt_entry_size_shift = 3;
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info->gmadr_bytes_in_cmd = 8;
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info->max_surface_size = 36 * 1024 * 1024;
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}
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}
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@ -177,6 +179,7 @@ void intel_gvt_clean_device(struct drm_i915_private *dev_priv)
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return;
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clean_service_thread(gvt);
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intel_gvt_clean_cmd_parser(gvt);
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intel_gvt_clean_sched_policy(gvt);
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intel_gvt_clean_workload_scheduler(gvt);
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intel_gvt_clean_opregion(gvt);
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@ -249,14 +252,20 @@ int intel_gvt_init_device(struct drm_i915_private *dev_priv)
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if (ret)
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goto out_clean_workload_scheduler;
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ret = init_service_thread(gvt);
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ret = intel_gvt_init_cmd_parser(gvt);
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if (ret)
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goto out_clean_sched_policy;
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ret = init_service_thread(gvt);
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if (ret)
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goto out_clean_cmd_parser;
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gvt_dbg_core("gvt device creation is done\n");
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gvt->initialized = true;
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return 0;
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out_clean_cmd_parser:
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intel_gvt_clean_cmd_parser(gvt);
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out_clean_sched_policy:
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intel_gvt_clean_sched_policy(gvt);
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out_clean_workload_scheduler:
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@ -45,6 +45,7 @@
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#include "scheduler.h"
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#include "sched_policy.h"
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#include "render.h"
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#include "cmd_parser.h"
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#define GVT_MAX_VGPU 8
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@ -71,6 +72,8 @@ struct intel_gvt_device_info {
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u32 gtt_start_offset;
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u32 gtt_entry_size;
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u32 gtt_entry_size_shift;
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int gmadr_bytes_in_cmd;
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u32 max_surface_size;
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};
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/* GM resources owned by a vGPU */
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@ -203,6 +206,7 @@ struct intel_gvt {
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struct intel_gvt_gtt gtt;
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struct intel_gvt_opregion opregion;
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struct intel_gvt_workload_scheduler scheduler;
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DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS);
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struct task_struct *service_thread;
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wait_queue_head_t service_thread_wq;
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@ -226,4 +226,8 @@ int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
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int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
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unsigned int reg, void *p_data, unsigned int bytes);
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int gvt_ring_id_to_pipe_control_notify_event(int ring_id);
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int gvt_ring_id_to_mi_flush_dw_event(int ring_id);
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int gvt_ring_id_to_mi_user_interrupt_event(int ring_id);
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#endif /* _GVT_INTERRUPT_H_ */
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@ -185,6 +185,14 @@ static int dispatch_workload(struct intel_vgpu_workload *workload)
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mutex_lock(&gvt->lock);
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ret = intel_gvt_scan_and_shadow_workload(workload);
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if (ret)
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goto err;
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|
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ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
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if (ret)
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goto err;
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ret = populate_shadow_context(workload);
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if (ret)
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goto err;
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|
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@ -345,6 +353,7 @@ static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
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{
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struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
|
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struct intel_vgpu_workload *workload;
|
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int event;
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|
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mutex_lock(&gvt->lock);
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|
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@ -355,6 +364,11 @@ static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
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!atomic_read(&workload->shadow_ctx_active));
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update_guest_context(workload);
|
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|
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for_each_set_bit(event, workload->pending_events,
|
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INTEL_GVT_EVENT_MAX)
|
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intel_vgpu_trigger_virtual_event(workload->vgpu,
|
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event);
|
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}
|
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|
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gvt_dbg_sched("ring id %d complete workload %p status %d\n",
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|
|
|
|||
|
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@ -50,6 +50,29 @@ struct intel_gvt_workload_scheduler {
|
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struct intel_gvt_sched_policy_ops *sched_ops;
|
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};
|
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|
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#define INDIRECT_CTX_ADDR_MASK 0xffffffc0
|
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#define INDIRECT_CTX_SIZE_MASK 0x3f
|
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struct shadow_indirect_ctx {
|
||||
struct drm_i915_gem_object *obj;
|
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unsigned long guest_gma;
|
||||
unsigned long shadow_gma;
|
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void *shadow_va;
|
||||
uint32_t size;
|
||||
};
|
||||
|
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#define PER_CTX_ADDR_MASK 0xfffff000
|
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struct shadow_per_ctx {
|
||||
unsigned long guest_gma;
|
||||
unsigned long shadow_gma;
|
||||
};
|
||||
|
||||
struct intel_shadow_wa_ctx {
|
||||
struct intel_vgpu_workload *workload;
|
||||
struct shadow_indirect_ctx indirect_ctx;
|
||||
struct shadow_per_ctx per_ctx;
|
||||
|
||||
};
|
||||
|
||||
struct intel_vgpu_workload {
|
||||
struct intel_vgpu *vgpu;
|
||||
int ring_id;
|
||||
|
|
@ -65,16 +88,32 @@ struct intel_vgpu_workload {
|
|||
int (*complete)(struct intel_vgpu_workload *);
|
||||
struct list_head list;
|
||||
|
||||
DECLARE_BITMAP(pending_events, INTEL_GVT_EVENT_MAX);
|
||||
void *shadow_ring_buffer_va;
|
||||
|
||||
/* execlist context information */
|
||||
struct execlist_ctx_descriptor_format ctx_desc;
|
||||
struct execlist_ring_context *ring_context;
|
||||
unsigned long rb_head, rb_tail, rb_ctl, rb_start;
|
||||
unsigned long rb_head, rb_tail, rb_ctl, rb_start, rb_len;
|
||||
bool restore_inhibit;
|
||||
struct intel_vgpu_elsp_dwords elsp_dwords;
|
||||
bool emulate_schedule_in;
|
||||
atomic_t shadow_ctx_active;
|
||||
wait_queue_head_t shadow_ctx_status_wq;
|
||||
u64 ring_context_gpa;
|
||||
|
||||
/* shadow batch buffer */
|
||||
struct list_head shadow_bb;
|
||||
struct intel_shadow_wa_ctx wa_ctx;
|
||||
};
|
||||
|
||||
/* Intel shadow batch buffer is a i915 gem object */
|
||||
struct intel_shadow_bb_entry {
|
||||
struct list_head list;
|
||||
struct drm_i915_gem_object *obj;
|
||||
void *va;
|
||||
unsigned long len;
|
||||
void *bb_start_cmd_va;
|
||||
};
|
||||
|
||||
#define workload_q_head(vgpu, ring_id) \
|
||||
|
|
|
|||
|
|
@ -224,6 +224,58 @@ TRACE_EVENT(oos_sync,
|
|||
TP_printk("%s", __entry->buf)
|
||||
);
|
||||
|
||||
#define MAX_CMD_STR_LEN 256
|
||||
TRACE_EVENT(gvt_command,
|
||||
TP_PROTO(u8 vm_id, u8 ring_id, u32 ip_gma, u32 *cmd_va, u32 cmd_len, bool ring_buffer_cmd, cycles_t cost_pre_cmd_handler, cycles_t cost_cmd_handler),
|
||||
|
||||
TP_ARGS(vm_id, ring_id, ip_gma, cmd_va, cmd_len, ring_buffer_cmd, cost_pre_cmd_handler, cost_cmd_handler),
|
||||
|
||||
TP_STRUCT__entry(
|
||||
__field(u8, vm_id)
|
||||
__field(u8, ring_id)
|
||||
__field(int, i)
|
||||
__array(char, tmp_buf, MAX_CMD_STR_LEN)
|
||||
__array(char, cmd_str, MAX_CMD_STR_LEN)
|
||||
),
|
||||
|
||||
TP_fast_assign(
|
||||
__entry->vm_id = vm_id;
|
||||
__entry->ring_id = ring_id;
|
||||
__entry->cmd_str[0] = '\0';
|
||||
snprintf(__entry->tmp_buf, MAX_CMD_STR_LEN, "VM(%d) Ring(%d): %s ip(%08x) pre handler cost (%llu), handler cost (%llu) ", vm_id, ring_id, ring_buffer_cmd ? "RB":"BB", ip_gma, cost_pre_cmd_handler, cost_cmd_handler);
|
||||
strcat(__entry->cmd_str, __entry->tmp_buf);
|
||||
entry->i = 0;
|
||||
while (cmd_len > 0) {
|
||||
if (cmd_len >= 8) {
|
||||
snprintf(__entry->tmp_buf, MAX_CMD_STR_LEN, "%08x %08x %08x %08x %08x %08x %08x %08x ",
|
||||
cmd_va[__entry->i], cmd_va[__entry->i+1], cmd_va[__entry->i+2], cmd_va[__entry->i+3],
|
||||
cmd_va[__entry->i+4], cmd_va[__entry->i+5], cmd_va[__entry->i+6], cmd_va[__entry->i+7]);
|
||||
__entry->i += 8;
|
||||
cmd_len -= 8;
|
||||
strcat(__entry->cmd_str, __entry->tmp_buf);
|
||||
} else if (cmd_len >= 4) {
|
||||
snprintf(__entry->tmp_buf, MAX_CMD_STR_LEN, "%08x %08x %08x %08x ",
|
||||
cmd_va[__entry->i], cmd_va[__entry->i+1], cmd_va[__entry->i+2], cmd_va[__entry->i+3]);
|
||||
__entry->i += 4;
|
||||
cmd_len -= 4;
|
||||
strcat(__entry->cmd_str, __entry->tmp_buf);
|
||||
} else if (cmd_len >= 2) {
|
||||
snprintf(__entry->tmp_buf, MAX_CMD_STR_LEN, "%08x %08x ", cmd_va[__entry->i], cmd_va[__entry->i+1]);
|
||||
__entry->i += 2;
|
||||
cmd_len -= 2;
|
||||
strcat(__entry->cmd_str, __entry->tmp_buf);
|
||||
} else if (cmd_len == 1) {
|
||||
snprintf(__entry->tmp_buf, MAX_CMD_STR_LEN, "%08x ", cmd_va[__entry->i]);
|
||||
__entry->i += 1;
|
||||
cmd_len -= 1;
|
||||
strcat(__entry->cmd_str, __entry->tmp_buf);
|
||||
}
|
||||
}
|
||||
strcat(__entry->cmd_str, "\n");
|
||||
),
|
||||
|
||||
TP_printk("%s", __entry->cmd_str)
|
||||
);
|
||||
#endif /* _GVT_TRACE_H_ */
|
||||
|
||||
/* This part must be out of protection */
|
||||
|
|
|
|||
Loading…
Reference in New Issue