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This pull request contains Device Tree changes for Broadcom ARM-based SoCs: 

- Chris provides documentation and DTS fixes for the bcm11351 CPU enable-method in preparation
   for adding support for the BCM23550 SoC and its corresponding documentation, SoC dtsi
   and the Sparrow board DTS file
 
 - Jon adds MSI support to the PCI nodes, updates the secondary cores boot address for the B0
   production revision of the Northstar Plus SoC, adds a DTS for the BCM958625HR board, another
   one for the BCM958525XMC board, and finally adds the PL330 DMA controller to the NSP DTS
 
 - Rafal enables the SPI NOR flash on dual flash systems (NAND + SPI) on the BCM5301x SoCs
   and devices
 
 - Florian adds support for the BCM5301x built-in Ethernet switch by adding nodes for the
   Gigabit MAC controllers and the Switch Register Access block, and finally updates the
   SmartRG SR-400AC board with its switch port layout
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Merge tag 'arm-soc/for-4.8/devicetree' of http://github.com/Broadcom/stblinux into next/dt

This pull request contains Device Tree changes for Broadcom ARM-based SoCs:

- Chris provides documentation and DTS fixes for the bcm11351 CPU enable-method in preparation
  for adding support for the BCM23550 SoC and its corresponding documentation, SoC dtsi
  and the Sparrow board DTS file

- Jon adds MSI support to the PCI nodes, updates the secondary cores boot address for the B0
  production revision of the Northstar Plus SoC, adds a DTS for the BCM958625HR board, another
  one for the BCM958525XMC board, and finally adds the PL330 DMA controller to the NSP DTS

- Rafal enables the SPI NOR flash on dual flash systems (NAND + SPI) on the BCM5301x SoCs
  and devices

- Florian adds support for the BCM5301x built-in Ethernet switch by adding nodes for the
  Gigabit MAC controllers and the Switch Register Access block, and finally updates the
  SmartRG SR-400AC board with its switch port layout

* tag 'arm-soc/for-4.8/devicetree' of http://github.com/Broadcom/stblinux:
  ARM: dts: BCM5310x: Enable switch ports on SmartRG SR400AC
  ARM: dts: BCM5301X: Add SRAB interrupts
  ARM: dts: Enable SRAB switch and GMACs on 5301x DTS
  ARM: dts: NSP: Add PL330 support
  ARM: dts: NSP: Add XMC board support
  ARM: dts: bcm23550: Add device tree files
  Documentation: devicetree: Document BCM23550 bindings
  ARM: BCM5301X: Enable SPI-NOR on dual flash devices
  ARM: dts: NSP: Add new DT file for bcm958625hr
  ARM: dts: NSP: modify second CPU address
  ARM: dts: NSP: Add MSI support on PCI
  ARM: BCM: modify Broadcom CPU enable method
  ARM: dts: fix use of bcm11351 enable method
  Documentation: Binding docs for bcm11351 enable method

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2016-06-19 22:45:47 -07:00
parent 00d624dcb9 2df1808dc0
commit be6e3f3160
20 changed files with 966 additions and 86 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
View File

@ -5,7 +5,7 @@ CPUs in the following Broadcom SoCs:
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664
The enable method is specified by defining the following required
properties in the "cpus" device tree node:
properties in the "cpu" device tree node:
- enable-method = "brcm,bcm11351-cpu-method";
- secondary-boot-reg = <...>;
@ -19,8 +19,6 @@ Example:
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "brcm,bcm11351-cpu-method";
secondary-boot-reg = <0x3500417c>;
cpu0: cpu@0 {
device_type = "cpu";
@ -32,5 +30,7 @@ Example:
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
enable-method = "brcm,bcm11351-cpu-method";
secondary-boot-reg = <0x3500417c>;
};
};

36
Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt Normal file
View File

@ -0,0 +1,36 @@
Broadcom Kona Family CPU Enable Method
--------------------------------------
This binding defines the enable method used for starting secondary
CPUs in the following Broadcom SoCs:
BCM23550
The enable method is specified by defining the following required
properties in the "cpu" device tree node:
- enable-method = "brcm,bcm23550";
- secondary-boot-reg = <...>;
The secondary-boot-reg property is a u32 value that specifies the
physical address of the register used to request the ROM holding pen
code release a secondary CPU. The value written to the register is
formed by encoding the target CPU id into the low bits of the
physical start address it should jump to.
Example:
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
enable-method = "brcm,bcm23550";
secondary-boot-reg = <0x3500417c>;
};
};

15
Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.txt Normal file
View File

@ -0,0 +1,15 @@
Broadcom BCM23550 device tree bindings
--------------------------------------
This document describes the device tree bindings for boards with the BCM23550
SoC.
Required root node property:
- compatible: brcm,bcm23550
Example:
/ {
model = "BCM23550 SoC";
compatible = "brcm,bcm23550";
[...]
}

2
Documentation/devicetree/bindings/arm/cpus.txt
View File

@ -193,6 +193,8 @@ nodes to be present and contain the properties described below.
"allwinner,sun6i-a31"
"allwinner,sun8i-a23"
"arm,realview-smp"
"brcm,bcm11351-cpu-method"
"brcm,bcm23550"
"brcm,bcm-nsp-smp"
"brcm,brahma-b15"
"marvell,armada-375-smp"

5
arch/arm/boot/dts/Makefile
View File

@ -96,8 +96,11 @@ dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
bcm958305k.dtb
dtb-$(CONFIG_ARCH_BCM_MOBILE) += \
bcm28155-ap.dtb \
bcm21664-garnet.dtb
bcm21664-garnet.dtb \
bcm23550-sparrow.dtb
dtb-$(CONFIG_ARCH_BCM_NSP) += \
bcm958525xmc.dtb \
bcm958625hr.dtb \
bcm958625k.dtb
dtb-$(CONFIG_ARCH_BERLIN) += \
berlin2-sony-nsz-gs7.dtb \

55
arch/arm/boot/dts/bcm-nsp.dtsi
View File

@ -57,7 +57,7 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
enable-method = "brcm,bcm-nsp-smp";
secondary-boot-reg = <0xffff042c>;
secondary-boot-reg = <0xffff0fec>;
reg = <0x1>;
};
};
@ -192,6 +192,23 @@ uart1: serial@0400 {
status = "disabled";
};
dma@20000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x20000 0x1000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>;
clock-names = "apb_pclk";
#dma-cells = <1>;
};
nand: nand@26000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x026000 0x600>,
@ -290,6 +307,18 @@ pcie0: pcie@18012000 {
ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
status = "disabled";
msi-parent = <&msi0>;
msi0: msi@18012000 {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>,
<GIC_SPI 128 IRQ_TYPE_NONE>,
<GIC_SPI 129 IRQ_TYPE_NONE>,
<GIC_SPI 130 IRQ_TYPE_NONE>;
brcm,pcie-msi-inten;
};
};
pcie1: pcie@18013000 {
@ -314,6 +343,18 @@ pcie1: pcie@18013000 {
ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
status = "disabled";
msi-parent = <&msi1>;
msi1: msi@18013000 {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 133 IRQ_TYPE_NONE>,
<GIC_SPI 134 IRQ_TYPE_NONE>,
<GIC_SPI 135 IRQ_TYPE_NONE>,
<GIC_SPI 136 IRQ_TYPE_NONE>;
brcm,pcie-msi-inten;
};
};
pcie2: pcie@18014000 {
@ -338,5 +379,17 @@ pcie2: pcie@18014000 {
ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
status = "disabled";
msi-parent = <&msi2>;
msi2: msi@18014000 {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>,
<GIC_SPI 140 IRQ_TYPE_NONE>,
<GIC_SPI 141 IRQ_TYPE_NONE>,
<GIC_SPI 142 IRQ_TYPE_NONE>;
brcm,pcie-msi-inten;
};
};
};

2
arch/arm/boot/dts/bcm11351.dtsi
View File

@ -30,7 +30,6 @@ chosen {
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "brcm,bcm11351-cpu-method";
cpu0: cpu@0 {
device_type = "cpu";
@ -41,6 +40,7 @@ cpu0: cpu@0 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
enable-method = "brcm,bcm11351-cpu-method";
secondary-boot-reg = <0x3500417c>;
reg = <1>;
};

2
arch/arm/boot/dts/bcm21664.dtsi
View File

@ -30,7 +30,6 @@ chosen {
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "brcm,bcm11351-cpu-method";
cpu0: cpu@0 {
device_type = "cpu";
@ -41,6 +40,7 @@ cpu0: cpu@0 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
enable-method = "brcm,bcm11351-cpu-method";
secondary-boot-reg = <0x35004178>;
reg = <1>;
};

80
arch/arm/boot/dts/bcm23550-sparrow.dts Normal file
View File

@ -0,0 +1,80 @@
/*
* BSD LICENSE
*
* Copyright(c) 2016 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "bcm23550.dtsi"
/ {
model = "BCM23550 Sparrow board";
compatible = "brcm,bcm23550-sparrow", "brcm,bcm23550";
chosen {
stdout-path = "/slaves@3e000000/serial@0:115200n8";
bootargs = "console=ttyS0,115200n8";
};
memory {
reg = <0x80000000 0x20000000>; /* 512 MB */
};
};
&uartb {
status = "okay";
};
&usbotg {
status = "okay";
};
&usbphy {
status = "okay";
};
&sdio1 {
max-frequency = <48000000>;
status = "okay";
};
&sdio2 {
non-removable;
max-frequency = <48000000>;
status = "okay";
};
&sdio4 {
max-frequency = <48000000>;
cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>;
status = "okay";
};

415
arch/arm/boot/dts/bcm23550.dtsi Normal file
View File

@ -0,0 +1,415 @@
/*
* BSD LICENSE
*
* Copyright(c) 2016 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/* BCM23550 and BCM21664 have almost identical clocks */
#include "dt-bindings/clock/bcm21664.h"
#include "skeleton.dtsi"
/ {
model = "BCM23550 SoC";
compatible = "brcm,bcm23550";
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0>;
clock-frequency = <1000000000>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
enable-method = "brcm,bcm23550";
secondary-boot-reg = <0x35004178>;
reg = <1>;
clock-frequency = <1000000000>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
enable-method = "brcm,bcm23550";
secondary-boot-reg = <0x35004178>;
reg = <2>;
clock-frequency = <1000000000>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
enable-method = "brcm,bcm23550";
secondary-boot-reg = <0x35004178>;
reg = <3>;
clock-frequency = <1000000000>;
};
};
/* Hub bus */
hub@34000000 {
compatible = "simple-bus";
ranges = <0 0x34000000 0x102f83ac>;
#address-cells = <1>;
#size-cells = <1>;
smc@4e000 {
compatible = "brcm,bcm23550-smc", "brcm,kona-smc";
reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
};
resetmgr: reset-controller@1001f00 {
compatible = "brcm,bcm21664-resetmgr";
reg = <0x01001f00 0x24>;
};
gpio: gpio@1003000 {
compatible = "brcm,bcm23550-gpio", "brcm,kona-gpio";
reg = <0x01003000 0x524>;
interrupts =
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;
interrupt-controller;
};
timer@1006000 {
compatible = "brcm,kona-timer";
reg = <0x01006000 0x1c>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
};
};
/* Slaves bus */
slaves@3e000000 {
compatible = "simple-bus";
ranges = <0 0x3e000000 0x0001c070>;
#address-cells = <1>;
#size-cells = <1>;
uartb: serial@0 {
compatible = "snps,dw-apb-uart";
status = "disabled";
reg = <0x00000000 0x118>;
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
uartb2: serial@1000 {
compatible = "snps,dw-apb-uart";
status = "disabled";
reg = <0x00001000 0x118>;
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
uartb3: serial@2000 {
compatible = "snps,dw-apb-uart";
status = "disabled";
reg = <0x00002000 0x118>;
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
bsc1: i2c@16000 {
compatible = "brcm,kona-i2c";
reg = <0x00016000 0x70>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
status = "disabled";
};
bsc2: i2c@17000 {
compatible = "brcm,kona-i2c";
reg = <0x00017000 0x70>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
status = "disabled";
};
bsc3: i2c@18000 {
compatible = "brcm,kona-i2c";
reg = <0x00018000 0x70>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>;
status = "disabled";
};
bsc4: i2c@1c000 {
compatible = "brcm,kona-i2c";
reg = <0x0001c000 0x70>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>;
status = "disabled";
};
};
/* Apps bus */
apps@3e300000 {
compatible = "simple-bus";
ranges = <0 0x3e300000 0x01b77000>;
#address-cells = <1>;
#size-cells = <1>;
usbotg: usb@e20000 {
compatible = "snps,dwc2";
reg = <0x00e20000 0x10000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usb_otg_ahb_clk>;
clock-names = "otg";
phys = <&usbphy>;
phy-names = "usb2-phy";
status = "disabled";
};
usbphy: usb-phy@e30000 {
compatible = "brcm,kona-usb2-phy";
reg = <0x00e30000 0x28>;
#phy-cells = <0>;
status = "disabled";
};
sdio1: sdio@e80000 {
compatible = "brcm,kona-sdhci";
reg = <0x00e80000 0x801c>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
status = "disabled";
};
sdio2: sdio@e90000 {
compatible = "brcm,kona-sdhci";
reg = <0x00e90000 0x801c>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
status = "disabled";
};
sdio3: sdio@ea0000 {
compatible = "brcm,kona-sdhci";
reg = <0x00ea0000 0x801c>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
status = "disabled";
};
sdio4: sdio@eb0000 {
compatible = "brcm,kona-sdhci";
reg = <0x00eb0000 0x801c>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
status = "disabled";
};
cdc: cdc@1b0e000 {
compatible = "brcm,bcm23550-cdc";
reg = <0x01b0e000 0x78>;
};
gic: interrupt-controller@1b21000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x01b21000 0x1000>,
<0x01b22000 0x1000>;
};
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/*
* Fixed clocks are defined before CCUs whose
* clocks may depend on them.
*/
ref_32k_clk: ref_32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
bbl_32k_clk: bbl_32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
ref_13m_clk: ref_13m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <13000000>;
};
var_13m_clk: var_13m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <13000000>;
};
dft_19_5m_clk: dft_19_5m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <19500000>;
};
ref_crystal_clk: ref_crystal {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <26000000>;
};
ref_52m_clk: ref_52m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <52000000>;
};
var_52m_clk: var_52m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <52000000>;
};
usb_otg_ahb_clk: usb_otg_ahb {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <52000000>;
};
ref_96m_clk: ref_96m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <96000000>;
};
var_96m_clk: var_96m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <96000000>;
};
ref_104m_clk: ref_104m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <104000000>;
};
var_104m_clk: var_104m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <104000000>;
};
ref_156m_clk: ref_156m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <156000000>;
};
var_156m_clk: var_156m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <156000000>;
};
root_ccu: root_ccu {
compatible = BCM21664_DT_ROOT_CCU_COMPAT;
reg = <0x35001000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "frac_1m";
};
aon_ccu: aon_ccu {
compatible = BCM21664_DT_AON_CCU_COMPAT;
reg = <0x35002000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "hub_timer";
};
slave_ccu: slave_ccu {
compatible = BCM21664_DT_SLAVE_CCU_COMPAT;
reg = <0x3e011000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "uartb",
"uartb2",
"uartb3",
"bsc1",
"bsc2",
"bsc3",
"bsc4";
};
master_ccu: master_ccu {
compatible = BCM21664_DT_MASTER_CCU_COMPAT;
reg = <0x3f001000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "sdio1",
"sdio2",
"sdio3",
"sdio4",
"sdio1_sleep",
"sdio2_sleep",
"sdio3_sleep",
"sdio4_sleep";
};
};
};

4
arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
View File

@ -147,3 +147,7 @@ &usb2 {
&usb3 {
vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>;
};
&spi_nor {
status = "okay";
};

4
arch/arm/boot/dts/bcm4708-netgear-r6250.dts
View File

@ -90,3 +90,7 @@ &uart0 {
&usb3 {
vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
};
&spi_nor {
status = "okay";
};

4
arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
View File

@ -82,3 +82,7 @@ restart {
};
};
};
&spi_nor {
status = "okay";
};

40
arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
View File

@ -126,3 +126,43 @@ &uart0 {
&spi_nor {
status = "okay";
};
&srab {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan4";
};
port@1 {
reg = <1>;
label = "lan3";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan1";
};
port@4 {
reg = <4>;
label = "wan";
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
};
};
};

4
arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
View File

@ -131,3 +131,7 @@ eject {
&usb2 {
vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
};
&spi_nor {
status = "okay";
};

4
arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
View File

@ -113,3 +113,7 @@ &uart0 {
&usb3 {
vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
};
&spi_nor {
status = "okay";
};

42
arch/arm/boot/dts/bcm5301x.dtsi
View File

@ -153,6 +153,21 @@ axi@18000000 {
/* ChipCommon */
<0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
/* Switch Register Access Block */
<0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
/* PCIe Controller 0 */
<0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
@ -239,6 +254,22 @@ spi_nor: spi-nor@0 {
status = "disabled";
};
};
gmac0: ethernet@24000 {
reg = <0x24000 0x800>;
};
gmac1: ethernet@25000 {
reg = <0x25000 0x800>;
};
gmac2: ethernet@26000 {
reg = <0x26000 0x800>;
};
gmac3: ethernet@27000 {
reg = <0x27000 0x800>;
};
};
lcpll0: lcpll0@1800c100 {
@ -260,6 +291,17 @@ genpll: genpll@1800c140 {
"sata2";
};
srab: srab@18007000 {
compatible = "brcm,bcm5301x-srab";
reg = <0x18007000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
/* ports are defined in board DTS */
};
nand: nand@18028000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;

109
arch/arm/boot/dts/bcm958525xmc.dts Normal file
View File

@ -0,0 +1,109 @@
/*
* BSD LICENSE
*
* Copyright(c) 2016 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
#include "bcm-nsp.dtsi"
/ {
model = "NorthStar Plus XMC (BCM958525xmc)";
compatible = "brcm,bcm58525", "brcm,nsp";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&nand {
nandcs@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <1>;
nand-ecc-strength = <24>;
nand-ecc-step-size = <1024>;
brcm,nand-oob-sector-size = <27>;
partition@0 {
label = "nboot";
reg = <0x00000000 0x00200000>;
read-only;
};
partition@200000 {
label = "nenv";
reg = <0x00200000 0x00400000>;
};
partition@600000 {
label = "nsystem";
reg = <0x00600000 0x00a00000>;
};
partition@1000000 {
label = "nrootfs";
reg = <0x01000000 0x03000000>;
};
partition@4000000 {
label = "ncustfs";
reg = <0x04000000 0x3c000000>;
};
};
};
/* XHCI, SATA, MMC, and Ethernet support needed to be complete */
&uart0 {
status = "okay";
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&nand_sel>;
nand_sel: nand_sel {
function = "nand";
groups = "nand_grp";
};
};

107
arch/arm/boot/dts/bcm958625hr.dts Normal file
View File

@ -0,0 +1,107 @@
/*
* BSD LICENSE
*
* Copyright (c) 2016 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
#include "bcm-nsp.dtsi"
/ {
model = "NorthStar Plus SVK (BCM958625HR)";
compatible = "brcm,bcm58625", "brcm,nsp";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&nand {
nandcs@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <1>;
nand-ecc-strength = <24>;
nand-ecc-step-size = <1024>;
brcm,nand-oob-sector-size = <27>;
partition@0 {
label = "nboot";
reg = <0x00000000 0x00200000>;
read-only;
};
partition@200000 {
label = "nenv";
reg = <0x00200000 0x00400000>;
};
partition@600000 {
label = "nsystem";
reg = <0x00600000 0x00a00000>;
};
partition@1000000 {
label = "nrootfs";
reg = <0x01000000 0x03000000>;
};
partition@4000000 {
label = "ncustfs";
reg = <0x04000000 0x3c000000>;
};
};
};
&uart0 {
status = "okay";
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&nand_sel>;
nand_sel: nand_sel {
function = "nand";
groups = "nand_grp";
};
};

116
arch/arm/mach-bcm/platsmp.c
View File

@ -37,9 +37,6 @@
#define OF_SECONDARY_BOOT "secondary-boot-reg"
#define MPIDR_CPUID_BITMASK 0x3
/* I/O address of register used to coordinate secondary core startup */
static u32 secondary_boot_addr;
/*
* Enable the Cortex A9 Snoop Control Unit
*
@ -81,20 +78,40 @@ static int __init scu_a9_enable(void)
return 0;
}
static int nsp_write_lut(void)
static u32 secondary_boot_addr_for(unsigned int cpu)
{
u32 secondary_boot_addr = 0;
struct device_node *cpu_node = of_get_cpu_node(cpu, NULL);
if (!cpu_node) {
pr_err("Failed to find device tree node for CPU%u\n", cpu);
return 0;
}
if (of_property_read_u32(cpu_node,
OF_SECONDARY_BOOT,
&secondary_boot_addr))
pr_err("required secondary boot register not specified for CPU%u\n",
cpu);
of_node_put(cpu_node);
return secondary_boot_addr;
}
static int nsp_write_lut(unsigned int cpu)
{
void __iomem *sku_rom_lut;
phys_addr_t secondary_startup_phy;
const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);
if (!secondary_boot_addr) {
pr_warn("required secondary boot register not specified\n");
if (!secondary_boot_addr)
return -EINVAL;
}
sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot_addr,
sizeof(secondary_boot_addr));
sizeof(phys_addr_t));
if (!sku_rom_lut) {
pr_warn("unable to ioremap SKU-ROM LUT register\n");
pr_warn("unable to ioremap SKU-ROM LUT register for cpu %u\n", cpu);
return -ENOMEM;
}
@ -113,70 +130,12 @@ static int nsp_write_lut(void)
static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
{
static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
struct device_node *cpus_node = NULL;
struct device_node *cpu_node = NULL;
int ret;
const cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
/*
* This function is only called via smp_ops->smp_prepare_cpu().
* That only happens if a "/cpus" device tree node exists
* and has an "enable-method" property that selects the SMP
* operations defined herein.
*/
cpus_node = of_find_node_by_path("/cpus");
if (!cpus_node)
return;
for_each_child_of_node(cpus_node, cpu_node) {
u32 cpuid;
if (of_node_cmp(cpu_node->type, "cpu"))
continue;
if (of_property_read_u32(cpu_node, "reg", &cpuid)) {
pr_debug("%s: missing reg property\n",
cpu_node->full_name);
ret = -ENOENT;
goto out;
}
/*
* "secondary-boot-reg" property should be defined only
* for secondary cpu
*/
if ((cpuid & MPIDR_CPUID_BITMASK) == 1) {
/*
* Our secondary enable method requires a
* "secondary-boot-reg" property to specify a register
* address used to request the ROM code boot a secondary
* core. If we have any trouble getting this we fall
* back to uniprocessor mode.
*/
if (of_property_read_u32(cpu_node,
OF_SECONDARY_BOOT,
&secondary_boot_addr)) {
pr_warn("%s: no" OF_SECONDARY_BOOT "property\n",
cpu_node->name);
ret = -ENOENT;
goto out;
}
}
}
/*
* Enable the SCU on Cortex A9 based SoCs. If -ENOENT is
* returned, the SoC reported a uniprocessor configuration.
* We bail on any other error.
*/
ret = scu_a9_enable();
out:
of_node_put(cpu_node);
of_node_put(cpus_node);
if (ret) {
/* Enable the SCU on Cortex A9 based SoCs */
if (scu_a9_enable()) {
/* Update the CPU present map to reflect uniprocessor mode */
pr_warn("disabling SMP\n");
pr_warn("failed to enable A9 SCU - disabling SMP\n");
init_cpu_present(&only_cpu_0);
}
}
@ -207,6 +166,7 @@ static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
u32 cpu_id;
u32 boot_val;
bool timeout = false;
const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);
cpu_id = cpu_logical_map(cpu);
if (cpu_id & ~BOOT_ADDR_CPUID_MASK) {
@ -214,13 +174,11 @@ static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
return -EINVAL;
}
if (!secondary_boot_addr) {
pr_err("required secondary boot register not specified\n");
if (!secondary_boot_addr)
return -EINVAL;
}
boot_reg = ioremap_nocache(
(phys_addr_t)secondary_boot_addr, sizeof(u32));
boot_reg = ioremap_nocache((phys_addr_t)secondary_boot_addr,
sizeof(phys_addr_t));
if (!boot_reg) {
pr_err("unable to map boot register for cpu %u\n", cpu_id);
return -ENOMEM;
@ -263,7 +221,7 @@ static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
* After wake up, secondary core branches to the startup
* address programmed at SKU ROM LUT location.
*/
ret = nsp_write_lut();
ret = nsp_write_lut(cpu);
if (ret) {
pr_err("unable to write startup addr to SKU ROM LUT\n");
goto out;
@ -276,12 +234,12 @@ static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
return ret;
}
static const struct smp_operations bcm_smp_ops __initconst = {
static const struct smp_operations kona_smp_ops __initconst = {
.smp_prepare_cpus = bcm_smp_prepare_cpus,
.smp_boot_secondary = kona_boot_secondary,
};
CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
&bcm_smp_ops);
&kona_smp_ops);
static const struct smp_operations nsp_smp_ops __initconst = {
.smp_prepare_cpus = bcm_smp_prepare_cpus,