drm/tegra: Changes for v4.3-rc1
There are a bunch of non-critical fixes here that I've collected over the past few months, but the biggest part is Tegra210 support, in the DC, DSI and SOR/HDMI drivers. Also this finally restores DPMS with atomic mode-setting, something that has been broken since the conversion and which I had originally expected to take far less longer to fix. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJVzgFhAAoJEN0jrNd/PrOhBLAP/2vDyK8H52ZusDdh06GNnmSB hr3Dfa3tePWUH/Um5qSPUvzdJg8Pnz85LsYUuQuHQRLeXfk2IsDe284CpMcKt6pW YQPXYqQreKwZFgct2fjqohlqRjNP6qRWuPYsTciz0IMiSFyEJY9DBuYhQQbD+HHb 9CJsHNUl2Oi3jOORvuawJKIyDPFfh4JzPRGcfdGRSE1VE6qt5Cb6XVcQxwR6R6UW 7NlOg0ylYcSkC1PpDTSIpTdpksxNJI0I4k263UlYQ9sfmHQjX1N3Ef/s1DOm4vHf 1CWJlT0zI8BVerukMe2rDkyzsXJgVN5QphQzwnRz7AhEtXtFNUKoRP6mIsCjYxRp 3HTQI4rOF2VbHw2yDSOTl9SBrq94dOtkZ3YskvHQICjcO6P/602ZqFrLjFj/jn6n rMNXoioYi8u3DDGsCdutiQTh+7BiQx9Mk/vVOei0vEeUk5KefGSawMwjo1Djjknb aagRpVHAbTZV178RO8tMGB10Z2aiYdYp/K7sywK4ktkhlYUGpIH6kmPwY/bERPes dZMqABSG8AslKZYrZhXWcXBPq5ymGojcJ0mqD7rK8xk1hAsE1LbMHqVwfrMCOaue r4bnhjnBkjcSXa+Pwz/5OvdbmLjXxmWMGIes1DYYgsWaIBvPfTMCzMv7Cq6f6A9X 7zCHroPgA/APxrk3b4Dc =lxYn -----END PGP SIGNATURE----- Merge tag 'drm/tegra/for-4.3-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Changes for v4.3-rc1 There are a bunch of non-critical fixes here that I've collected over the past few months, but the biggest part is Tegra210 support, in the DC, DSI and SOR/HDMI drivers. Also this finally restores DPMS with atomic mode-setting, something that has been broken since the conversion and which I had originally expected to take far less longer to fix. * tag 'drm/tegra/for-4.3-rc1' of git://anongit.freedesktop.org/tegra/linux: (41 commits) drm/tegra: sor: Add HDMI support drm/tegra: sor: Add Tegra210 eDP support drm/tegra: dc: Implement atomic DPMS drm/tegra: sor: Restore DPMS drm/tegra: dsi: Restore DPMS drm/tegra: hdmi: Restore DPMS drm/tegra: rgb: Restore DPMS drm/tegra: sor: Use DRM debugfs infrastructure for CRC drm/tegra: sor: Write correct head state registers drm/tegra: sor: Constify display mode drm/tegra: sor: Reset the correct debugfs fields drm/tegra: sor: Set minor after debugfs initialization drm/tegra: sor: Provide error messages in probe drm/tegra: sor: Rename registers for consistency drm/tegra: dpaux: Disable interrupt when detached drm/tegra: dpaux: Configure pads as I2C by default drm/tegra: dpaux: Provide error message in probe drm/tegra: dsi: Add Tegra210 support drm/tegra: dsi: Add Tegra132 support drm/tegra: dsi: Add Tegra124 support ...
This commit is contained in:
Dave Airlie
commit
bef2c7bd57
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@ -197,9 +197,11 @@ of the following host1x client modules:
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- sor: serial output resource
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Required properties:
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- compatible: For Tegra124, must contain "nvidia,tegra124-sor". Otherwise,
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must contain '"nvidia,<chip>-sor", "nvidia,tegra124-sor"', where <chip>
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is tegra132.
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- compatible: Should be:
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- "nvidia,tegra124-sor": for Tegra124 and Tegra132
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- "nvidia,tegra132-sor": for Tegra132
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- "nvidia,tegra210-sor": for Tegra210
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- "nvidia,tegra210-sor1": for Tegra210
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain an entry for each entry in clock-names.
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@ -76,6 +76,14 @@ to_tegra_plane_state(struct drm_plane_state *state)
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return NULL;
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}
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static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
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{
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stats->frames = 0;
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stats->vblank = 0;
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stats->underflow = 0;
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stats->overflow = 0;
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}
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/*
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* Reads the active copy of a register. This takes the dc->lock spinlock to
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* prevent races with the VBLANK processing which also needs access to the
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@ -759,7 +767,6 @@ static void tegra_cursor_atomic_update(struct drm_plane *plane,
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/* position the cursor */
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value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
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tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
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}
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static void tegra_cursor_atomic_disable(struct drm_plane *plane,
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@ -809,9 +816,11 @@ static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
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return ERR_PTR(-ENOMEM);
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/*
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* We'll treat the cursor as an overlay plane with index 6 here so
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* that the update and activation request bits in DC_CMD_STATE_CONTROL
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* match up.
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* This index is kind of fake. The cursor isn't a regular plane, but
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* its update and activation request bits in DC_CMD_STATE_CONTROL do
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* use the same programming. Setting this fake index here allows the
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* code in tegra_add_plane_state() to do the right thing without the
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* need to special-casing the cursor plane.
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*/
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plane->index = 6;
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@ -1015,6 +1024,8 @@ static void tegra_crtc_reset(struct drm_crtc *crtc)
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crtc->state = &state->base;
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crtc->state->crtc = crtc;
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}
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drm_crtc_vblank_reset(crtc);
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}
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static struct drm_crtc_state *
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@ -1052,90 +1063,6 @@ static const struct drm_crtc_funcs tegra_crtc_funcs = {
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.atomic_destroy_state = tegra_crtc_atomic_destroy_state,
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};
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static void tegra_dc_stop(struct tegra_dc *dc)
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{
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u32 value;
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/* stop the display controller */
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value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
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value &= ~DISP_CTRL_MODE_MASK;
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tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
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tegra_dc_commit(dc);
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}
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static bool tegra_dc_idle(struct tegra_dc *dc)
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{
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u32 value;
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value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
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return (value & DISP_CTRL_MODE_MASK) == 0;
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}
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static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
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{
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timeout = jiffies + msecs_to_jiffies(timeout);
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while (time_before(jiffies, timeout)) {
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if (tegra_dc_idle(dc))
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return 0;
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usleep_range(1000, 2000);
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}
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dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
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return -ETIMEDOUT;
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}
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static void tegra_crtc_disable(struct drm_crtc *crtc)
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{
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struct tegra_dc *dc = to_tegra_dc(crtc);
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u32 value;
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if (!tegra_dc_idle(dc)) {
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tegra_dc_stop(dc);
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/*
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* Ignore the return value, there isn't anything useful to do
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* in case this fails.
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*/
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tegra_dc_wait_idle(dc, 100);
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}
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/*
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* This should really be part of the RGB encoder driver, but clearing
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* these bits has the side-effect of stopping the display controller.
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* When that happens no VBLANK interrupts will be raised. At the same
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* time the encoder is disabled before the display controller, so the
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* above code is always going to timeout waiting for the controller
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* to go idle.
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*
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* Given the close coupling between the RGB encoder and the display
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* controller doing it here is still kind of okay. None of the other
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* encoder drivers require these bits to be cleared.
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*
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* XXX: Perhaps given that the display controller is switched off at
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* this point anyway maybe clearing these bits isn't even useful for
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* the RGB encoder?
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*/
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if (dc->rgb) {
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value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
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value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
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PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
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tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
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}
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drm_crtc_vblank_off(crtc);
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}
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static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted)
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{
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return true;
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}
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static int tegra_dc_set_timings(struct tegra_dc *dc,
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struct drm_display_mode *mode)
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{
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@ -1229,7 +1156,85 @@ static void tegra_dc_commit_state(struct tegra_dc *dc,
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tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
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}
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static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
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static void tegra_dc_stop(struct tegra_dc *dc)
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{
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u32 value;
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/* stop the display controller */
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value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
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value &= ~DISP_CTRL_MODE_MASK;
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tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
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tegra_dc_commit(dc);
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}
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static bool tegra_dc_idle(struct tegra_dc *dc)
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{
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u32 value;
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value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
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return (value & DISP_CTRL_MODE_MASK) == 0;
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}
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static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
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{
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timeout = jiffies + msecs_to_jiffies(timeout);
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while (time_before(jiffies, timeout)) {
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if (tegra_dc_idle(dc))
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return 0;
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usleep_range(1000, 2000);
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}
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dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
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return -ETIMEDOUT;
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}
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static void tegra_crtc_disable(struct drm_crtc *crtc)
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{
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struct tegra_dc *dc = to_tegra_dc(crtc);
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u32 value;
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if (!tegra_dc_idle(dc)) {
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tegra_dc_stop(dc);
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/*
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* Ignore the return value, there isn't anything useful to do
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* in case this fails.
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*/
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tegra_dc_wait_idle(dc, 100);
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}
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/*
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* This should really be part of the RGB encoder driver, but clearing
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* these bits has the side-effect of stopping the display controller.
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* When that happens no VBLANK interrupts will be raised. At the same
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* time the encoder is disabled before the display controller, so the
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* above code is always going to timeout waiting for the controller
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* to go idle.
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*
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* Given the close coupling between the RGB encoder and the display
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* controller doing it here is still kind of okay. None of the other
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* encoder drivers require these bits to be cleared.
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*
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* XXX: Perhaps given that the display controller is switched off at
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* this point anyway maybe clearing these bits isn't even useful for
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* the RGB encoder?
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*/
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if (dc->rgb) {
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value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
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value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
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PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
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tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
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}
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tegra_dc_stats_reset(&dc->stats);
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drm_crtc_vblank_off(crtc);
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}
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static void tegra_crtc_enable(struct drm_crtc *crtc)
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{
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struct drm_display_mode *mode = &crtc->state->adjusted_mode;
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struct tegra_dc_state *state = to_dc_state(crtc->state);
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@ -1259,15 +1264,7 @@ static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
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tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
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tegra_dc_commit(dc);
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}
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static void tegra_crtc_prepare(struct drm_crtc *crtc)
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{
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drm_crtc_vblank_off(crtc);
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}
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static void tegra_crtc_commit(struct drm_crtc *crtc)
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{
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drm_crtc_vblank_on(crtc);
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}
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@ -1304,10 +1301,7 @@ static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
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static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
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.disable = tegra_crtc_disable,
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.mode_fixup = tegra_crtc_mode_fixup,
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.mode_set_nofb = tegra_crtc_mode_set_nofb,
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.prepare = tegra_crtc_prepare,
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.commit = tegra_crtc_commit,
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.enable = tegra_crtc_enable,
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.atomic_check = tegra_crtc_atomic_check,
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.atomic_begin = tegra_crtc_atomic_begin,
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.atomic_flush = tegra_crtc_atomic_flush,
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@ -1325,6 +1319,7 @@ static irqreturn_t tegra_dc_irq(int irq, void *data)
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/*
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dev_dbg(dc->dev, "%s(): frame end\n", __func__);
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*/
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dc->stats.frames++;
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}
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if (status & VBLANK_INT) {
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@ -1333,12 +1328,21 @@ static irqreturn_t tegra_dc_irq(int irq, void *data)
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*/
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drm_crtc_handle_vblank(&dc->base);
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tegra_dc_finish_page_flip(dc);
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dc->stats.vblank++;
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}
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if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
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/*
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dev_dbg(dc->dev, "%s(): underflow\n", __func__);
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*/
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dc->stats.underflow++;
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}
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if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
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/*
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dev_dbg(dc->dev, "%s(): overflow\n", __func__);
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*/
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dc->stats.overflow++;
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}
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return IRQ_HANDLED;
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@ -1348,6 +1352,14 @@ static int tegra_dc_show_regs(struct seq_file *s, void *data)
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{
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struct drm_info_node *node = s->private;
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struct tegra_dc *dc = node->info_ent->data;
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int err = 0;
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drm_modeset_lock_crtc(&dc->base, NULL);
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|
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if (!dc->base.state->active) {
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err = -EBUSY;
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goto unlock;
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}
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|
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#define DUMP_REG(name) \
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seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
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|
@ -1568,11 +1580,59 @@ static int tegra_dc_show_regs(struct seq_file *s, void *data)
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|
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#undef DUMP_REG
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|
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unlock:
|
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drm_modeset_unlock_crtc(&dc->base);
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return err;
|
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}
|
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|
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static int tegra_dc_show_crc(struct seq_file *s, void *data)
|
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{
|
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struct drm_info_node *node = s->private;
|
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struct tegra_dc *dc = node->info_ent->data;
|
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int err = 0;
|
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u32 value;
|
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|
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drm_modeset_lock_crtc(&dc->base, NULL);
|
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|
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if (!dc->base.state->active) {
|
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err = -EBUSY;
|
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goto unlock;
|
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}
|
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|
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value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
|
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tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
|
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tegra_dc_commit(dc);
|
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|
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drm_crtc_wait_one_vblank(&dc->base);
|
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drm_crtc_wait_one_vblank(&dc->base);
|
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|
||||
value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
|
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seq_printf(s, "%08x\n", value);
|
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|
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tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
|
||||
|
||||
unlock:
|
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drm_modeset_unlock_crtc(&dc->base);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int tegra_dc_show_stats(struct seq_file *s, void *data)
|
||||
{
|
||||
struct drm_info_node *node = s->private;
|
||||
struct tegra_dc *dc = node->info_ent->data;
|
||||
|
||||
seq_printf(s, "frames: %lu\n", dc->stats.frames);
|
||||
seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
|
||||
seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
|
||||
seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct drm_info_list debugfs_files[] = {
|
||||
{ "regs", tegra_dc_show_regs, 0, NULL },
|
||||
{ "crc", tegra_dc_show_crc, 0, NULL },
|
||||
{ "stats", tegra_dc_show_stats, 0, NULL },
|
||||
};
|
||||
|
||||
static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
|
||||
|
|
@ -1718,7 +1778,8 @@ static int tegra_dc_init(struct host1x_client *client)
|
|||
tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
|
||||
}
|
||||
|
||||
value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
|
||||
value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
|
||||
WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
|
||||
tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
|
||||
|
||||
value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
|
||||
|
|
@ -1734,15 +1795,19 @@ static int tegra_dc_init(struct host1x_client *client)
|
|||
WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
|
||||
tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
|
||||
|
||||
value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
|
||||
value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
|
||||
WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
|
||||
tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
|
||||
|
||||
value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
|
||||
value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
|
||||
WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
|
||||
tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
|
||||
|
||||
if (dc->soc->supports_border_color)
|
||||
tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
|
||||
|
||||
tegra_dc_stats_reset(&dc->stats);
|
||||
|
||||
return 0;
|
||||
|
||||
cleanup:
|
||||
|
|
@ -1828,8 +1893,20 @@ static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
|
|||
.has_powergate = true,
|
||||
};
|
||||
|
||||
static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
|
||||
.supports_border_color = false,
|
||||
.supports_interlacing = true,
|
||||
.supports_cursor = true,
|
||||
.supports_block_linear = true,
|
||||
.pitch_align = 64,
|
||||
.has_powergate = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id tegra_dc_of_match[] = {
|
||||
{
|
||||
.compatible = "nvidia,tegra210-dc",
|
||||
.data = &tegra210_dc_soc_info,
|
||||
}, {
|
||||
.compatible = "nvidia,tegra124-dc",
|
||||
.data = &tegra124_dc_soc_info,
|
||||
}, {
|
||||
|
|
@ -1959,6 +2036,10 @@ static int tegra_dc_probe(struct platform_device *pdev)
|
|||
return -ENXIO;
|
||||
}
|
||||
|
||||
dc->syncpt = host1x_syncpt_request(&pdev->dev, flags);
|
||||
if (!dc->syncpt)
|
||||
dev_warn(&pdev->dev, "failed to allocate syncpoint\n");
|
||||
|
||||
INIT_LIST_HEAD(&dc->client.list);
|
||||
dc->client.ops = &dc_client_ops;
|
||||
dc->client.dev = &pdev->dev;
|
||||
|
|
@ -1976,10 +2057,6 @@ static int tegra_dc_probe(struct platform_device *pdev)
|
|||
return err;
|
||||
}
|
||||
|
||||
dc->syncpt = host1x_syncpt_request(&pdev->dev, flags);
|
||||
if (!dc->syncpt)
|
||||
dev_warn(&pdev->dev, "failed to allocate syncpoint\n");
|
||||
|
||||
platform_set_drvdata(pdev, dc);
|
||||
|
||||
return 0;
|
||||
|
|
@ -2018,7 +2095,6 @@ static int tegra_dc_remove(struct platform_device *pdev)
|
|||
struct platform_driver tegra_dc_driver = {
|
||||
.driver = {
|
||||
.name = "tegra-dc",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = tegra_dc_of_match,
|
||||
},
|
||||
.probe = tegra_dc_probe,
|
||||
|
|
|
|||
|
|
@ -86,6 +86,11 @@
|
|||
#define DC_CMD_REG_ACT_CONTROL 0x043
|
||||
|
||||
#define DC_COM_CRC_CONTROL 0x300
|
||||
#define DC_COM_CRC_CONTROL_ALWAYS (1 << 3)
|
||||
#define DC_COM_CRC_CONTROL_FULL_FRAME (0 << 2)
|
||||
#define DC_COM_CRC_CONTROL_ACTIVE_DATA (1 << 2)
|
||||
#define DC_COM_CRC_CONTROL_WAIT (1 << 1)
|
||||
#define DC_COM_CRC_CONTROL_ENABLE (1 << 0)
|
||||
#define DC_COM_CRC_CHECKSUM 0x301
|
||||
#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
|
||||
#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
|
||||
|
|
@ -114,15 +119,17 @@
|
|||
#define DC_COM_CRC_CHECKSUM_LATCHED 0x329
|
||||
|
||||
#define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400
|
||||
#define H_PULSE_0_ENABLE (1 << 8)
|
||||
#define H_PULSE_1_ENABLE (1 << 10)
|
||||
#define H_PULSE_2_ENABLE (1 << 12)
|
||||
#define H_PULSE0_ENABLE (1 << 8)
|
||||
#define H_PULSE1_ENABLE (1 << 10)
|
||||
#define H_PULSE2_ENABLE (1 << 12)
|
||||
|
||||
#define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401
|
||||
|
||||
#define DC_DISP_DISP_WIN_OPTIONS 0x402
|
||||
#define HDMI_ENABLE (1 << 30)
|
||||
#define DSI_ENABLE (1 << 29)
|
||||
#define SOR1_TIMING_CYA (1 << 27)
|
||||
#define SOR1_ENABLE (1 << 26)
|
||||
#define SOR_ENABLE (1 << 25)
|
||||
#define CURSOR_ENABLE (1 << 16)
|
||||
|
||||
|
|
@ -242,9 +249,20 @@
|
|||
#define BASE_COLOR_SIZE565 (6 << 0)
|
||||
#define BASE_COLOR_SIZE332 (7 << 0)
|
||||
#define BASE_COLOR_SIZE888 (8 << 0)
|
||||
#define DITHER_CONTROL_MASK (3 << 8)
|
||||
#define DITHER_CONTROL_DISABLE (0 << 8)
|
||||
#define DITHER_CONTROL_ORDERED (2 << 8)
|
||||
#define DITHER_CONTROL_ERRDIFF (3 << 8)
|
||||
#define BASE_COLOR_SIZE_MASK (0xf << 0)
|
||||
#define BASE_COLOR_SIZE_666 (0 << 0)
|
||||
#define BASE_COLOR_SIZE_111 (1 << 0)
|
||||
#define BASE_COLOR_SIZE_222 (2 << 0)
|
||||
#define BASE_COLOR_SIZE_333 (3 << 0)
|
||||
#define BASE_COLOR_SIZE_444 (4 << 0)
|
||||
#define BASE_COLOR_SIZE_555 (5 << 0)
|
||||
#define BASE_COLOR_SIZE_565 (6 << 0)
|
||||
#define BASE_COLOR_SIZE_332 (7 << 0)
|
||||
#define BASE_COLOR_SIZE_888 (8 << 0)
|
||||
|
||||
#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
|
||||
#define SC1_H_QUALIFIER_NONE (1 << 16)
|
||||
|
|
|
|||
|
|
@ -294,26 +294,41 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
|
||||
if (IS_ERR(dpaux->rst))
|
||||
if (IS_ERR(dpaux->rst)) {
|
||||
dev_err(&pdev->dev, "failed to get reset control: %ld\n",
|
||||
PTR_ERR(dpaux->rst));
|
||||
return PTR_ERR(dpaux->rst);
|
||||
}
|
||||
|
||||
dpaux->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(dpaux->clk))
|
||||
if (IS_ERR(dpaux->clk)) {
|
||||
dev_err(&pdev->dev, "failed to get module clock: %ld\n",
|
||||
PTR_ERR(dpaux->clk));
|
||||
return PTR_ERR(dpaux->clk);
|
||||
}
|
||||
|
||||
err = clk_prepare_enable(dpaux->clk);
|
||||
if (err < 0)
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev, "failed to enable module clock: %d\n",
|
||||
err);
|
||||
return err;
|
||||
}
|
||||
|
||||
reset_control_deassert(dpaux->rst);
|
||||
|
||||
dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
|
||||
if (IS_ERR(dpaux->clk_parent))
|
||||
if (IS_ERR(dpaux->clk_parent)) {
|
||||
dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
|
||||
PTR_ERR(dpaux->clk_parent));
|
||||
return PTR_ERR(dpaux->clk_parent);
|
||||
}
|
||||
|
||||
err = clk_prepare_enable(dpaux->clk_parent);
|
||||
if (err < 0)
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev, "failed to enable parent clock: %d\n",
|
||||
err);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = clk_set_rate(dpaux->clk_parent, 270000000);
|
||||
if (err < 0) {
|
||||
|
|
@ -323,8 +338,11 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");
|
||||
if (IS_ERR(dpaux->vdd))
|
||||
if (IS_ERR(dpaux->vdd)) {
|
||||
dev_err(&pdev->dev, "failed to get VDD supply: %ld\n",
|
||||
PTR_ERR(dpaux->vdd));
|
||||
return PTR_ERR(dpaux->vdd);
|
||||
}
|
||||
|
||||
err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
|
||||
dev_name(dpaux->dev), dpaux);
|
||||
|
|
@ -334,6 +352,8 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
|
|||
return err;
|
||||
}
|
||||
|
||||
disable_irq(dpaux->irq);
|
||||
|
||||
dpaux->aux.transfer = tegra_dpaux_transfer;
|
||||
dpaux->aux.dev = &pdev->dev;
|
||||
|
||||
|
|
@ -341,6 +361,24 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
|
|||
if (err < 0)
|
||||
return err;
|
||||
|
||||
/*
|
||||
* Assume that by default the DPAUX/I2C pads will be used for HDMI,
|
||||
* so power them up and configure them in I2C mode.
|
||||
*
|
||||
* The DPAUX code paths reconfigure the pads in AUX mode, but there
|
||||
* is no possibility to perform the I2C mode configuration in the
|
||||
* HDMI path.
|
||||
*/
|
||||
value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
|
||||
value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
|
||||
tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
|
||||
|
||||
value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_PADCTL);
|
||||
value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
|
||||
DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
|
||||
DPAUX_HYBRID_PADCTL_MODE_I2C;
|
||||
tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
|
||||
|
||||
/* enable and clear all interrupts */
|
||||
value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
|
||||
DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
|
||||
|
|
@ -359,6 +397,12 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
|
|||
static int tegra_dpaux_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
|
||||
u32 value;
|
||||
|
||||
/* make sure pads are powered down when not in use */
|
||||
value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
|
||||
value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
|
||||
tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
|
||||
|
||||
drm_dp_aux_unregister(&dpaux->aux);
|
||||
|
||||
|
|
@ -376,6 +420,7 @@ static int tegra_dpaux_remove(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
static const struct of_device_id tegra_dpaux_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra210-dpaux", },
|
||||
{ .compatible = "nvidia,tegra124-dpaux", },
|
||||
{ },
|
||||
};
|
||||
|
|
@ -425,8 +470,10 @@ int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output)
|
|||
enum drm_connector_status status;
|
||||
|
||||
status = tegra_dpaux_detect(dpaux);
|
||||
if (status == connector_status_connected)
|
||||
if (status == connector_status_connected) {
|
||||
enable_irq(dpaux->irq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
usleep_range(1000, 2000);
|
||||
}
|
||||
|
|
@ -439,6 +486,8 @@ int tegra_dpaux_detach(struct tegra_dpaux *dpaux)
|
|||
unsigned long timeout;
|
||||
int err;
|
||||
|
||||
disable_irq(dpaux->irq);
|
||||
|
||||
err = regulator_disable(dpaux->vdd);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
|
|
|||
|
|
@ -57,6 +57,8 @@
|
|||
#define DPAUX_DP_AUX_CONFIG 0x45
|
||||
|
||||
#define DPAUX_HYBRID_PADCTL 0x49
|
||||
#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV (1 << 15)
|
||||
#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV (1 << 14)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_CMH(x) (((x) & 0x3) << 12)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ(x) (((x) & 0x7) << 8)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVI(x) (((x) & 0x3f) << 2)
|
||||
|
|
|
|||
|
|
@ -171,8 +171,6 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
|
|||
if (err < 0)
|
||||
goto fbdev;
|
||||
|
||||
drm_mode_config_reset(drm);
|
||||
|
||||
/*
|
||||
* We don't use the drm_irq_install() helpers provided by the DRM
|
||||
* core, so we need to set this manually in order to allow the
|
||||
|
|
@ -182,11 +180,14 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
|
|||
|
||||
/* syncpoints are used for full 32-bit hardware VBLANK counters */
|
||||
drm->max_vblank_count = 0xffffffff;
|
||||
drm->vblank_disable_allowed = true;
|
||||
|
||||
err = drm_vblank_init(drm, drm->mode_config.num_crtc);
|
||||
if (err < 0)
|
||||
goto device;
|
||||
|
||||
drm_mode_config_reset(drm);
|
||||
|
||||
err = tegra_drm_fb_init(drm);
|
||||
if (err < 0)
|
||||
goto vblank;
|
||||
|
|
@ -1037,9 +1038,8 @@ static int host1x_drm_resume(struct device *dev)
|
|||
}
|
||||
#endif
|
||||
|
||||
static const struct dev_pm_ops host1x_drm_pm_ops = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(host1x_drm_suspend, host1x_drm_resume)
|
||||
};
|
||||
static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
|
||||
host1x_drm_resume);
|
||||
|
||||
static const struct of_device_id host1x_drm_subdevs[] = {
|
||||
{ .compatible = "nvidia,tegra20-dc", },
|
||||
|
|
@ -1056,6 +1056,12 @@ static const struct of_device_id host1x_drm_subdevs[] = {
|
|||
{ .compatible = "nvidia,tegra124-dc", },
|
||||
{ .compatible = "nvidia,tegra124-sor", },
|
||||
{ .compatible = "nvidia,tegra124-hdmi", },
|
||||
{ .compatible = "nvidia,tegra124-dsi", },
|
||||
{ .compatible = "nvidia,tegra132-dsi", },
|
||||
{ .compatible = "nvidia,tegra210-dc", },
|
||||
{ .compatible = "nvidia,tegra210-dsi", },
|
||||
{ .compatible = "nvidia,tegra210-sor", },
|
||||
{ .compatible = "nvidia,tegra210-sor1", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
|
||||
#include <uapi/drm/tegra_drm.h>
|
||||
#include <linux/host1x.h>
|
||||
#include <linux/of_gpio.h>
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/drm_crtc_helper.h>
|
||||
|
|
@ -104,6 +105,13 @@ int tegra_drm_exit(struct tegra_drm *tegra);
|
|||
struct tegra_dc_soc_info;
|
||||
struct tegra_output;
|
||||
|
||||
struct tegra_dc_stats {
|
||||
unsigned long frames;
|
||||
unsigned long vblank;
|
||||
unsigned long underflow;
|
||||
unsigned long overflow;
|
||||
};
|
||||
|
||||
struct tegra_dc {
|
||||
struct host1x_client client;
|
||||
struct host1x_syncpt *syncpt;
|
||||
|
|
@ -121,6 +129,7 @@ struct tegra_dc {
|
|||
|
||||
struct tegra_output *rgb;
|
||||
|
||||
struct tegra_dc_stats stats;
|
||||
struct list_head list;
|
||||
|
||||
struct drm_info_list *debugfs_files;
|
||||
|
|
@ -200,6 +209,7 @@ struct tegra_output {
|
|||
const struct edid *edid;
|
||||
unsigned int hpd_irq;
|
||||
int hpd_gpio;
|
||||
enum of_gpio_flags hpd_gpio_flags;
|
||||
|
||||
struct drm_encoder encoder;
|
||||
struct drm_connector connector;
|
||||
|
|
|
|||
|
|
@ -119,6 +119,16 @@ static int tegra_dsi_show_regs(struct seq_file *s, void *data)
|
|||
{
|
||||
struct drm_info_node *node = s->private;
|
||||
struct tegra_dsi *dsi = node->info_ent->data;
|
||||
struct drm_crtc *crtc = dsi->output.encoder.crtc;
|
||||
struct drm_device *drm = node->minor->dev;
|
||||
int err = 0;
|
||||
|
||||
drm_modeset_lock_all(drm);
|
||||
|
||||
if (!crtc || !crtc->state->active) {
|
||||
err = -EBUSY;
|
||||
goto unlock;
|
||||
}
|
||||
|
||||
#define DUMP_REG(name) \
|
||||
seq_printf(s, "%-32s %#05x %08x\n", #name, name, \
|
||||
|
|
@ -208,7 +218,9 @@ static int tegra_dsi_show_regs(struct seq_file *s, void *data)
|
|||
|
||||
#undef DUMP_REG
|
||||
|
||||
return 0;
|
||||
unlock:
|
||||
drm_modeset_unlock_all(drm);
|
||||
return err;
|
||||
}
|
||||
|
||||
static struct drm_info_list debugfs_files[] = {
|
||||
|
|
@ -548,14 +560,19 @@ static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
|
|||
|
||||
/* horizontal sync width */
|
||||
hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
|
||||
hsw -= 10;
|
||||
|
||||
/* horizontal back porch */
|
||||
hbp = (mode->htotal - mode->hsync_end) * mul / div;
|
||||
hbp -= 14;
|
||||
|
||||
if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
|
||||
hbp += hsw;
|
||||
|
||||
/* horizontal front porch */
|
||||
hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
|
||||
|
||||
/* subtract packet overhead */
|
||||
hsw -= 10;
|
||||
hbp -= 14;
|
||||
hfp -= 8;
|
||||
|
||||
tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
|
||||
|
|
@ -726,11 +743,6 @@ static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
|
|||
tegra_dsi_soft_reset(dsi->slave);
|
||||
}
|
||||
|
||||
static int tegra_dsi_connector_dpms(struct drm_connector *connector, int mode)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void tegra_dsi_connector_reset(struct drm_connector *connector)
|
||||
{
|
||||
struct tegra_dsi_state *state;
|
||||
|
|
@ -757,7 +769,7 @@ tegra_dsi_connector_duplicate_state(struct drm_connector *connector)
|
|||
}
|
||||
|
||||
static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
|
||||
.dpms = tegra_dsi_connector_dpms,
|
||||
.dpms = drm_atomic_helper_connector_dpms,
|
||||
.reset = tegra_dsi_connector_reset,
|
||||
.detect = tegra_output_connector_detect,
|
||||
.fill_modes = drm_helper_probe_single_connector_modes,
|
||||
|
|
@ -783,59 +795,6 @@ static const struct drm_encoder_funcs tegra_dsi_encoder_funcs = {
|
|||
.destroy = tegra_output_encoder_destroy,
|
||||
};
|
||||
|
||||
static void tegra_dsi_encoder_dpms(struct drm_encoder *encoder, int mode)
|
||||
{
|
||||
}
|
||||
|
||||
static void tegra_dsi_encoder_prepare(struct drm_encoder *encoder)
|
||||
{
|
||||
}
|
||||
|
||||
static void tegra_dsi_encoder_commit(struct drm_encoder *encoder)
|
||||
{
|
||||
}
|
||||
|
||||
static void tegra_dsi_encoder_mode_set(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted)
|
||||
{
|
||||
struct tegra_output *output = encoder_to_output(encoder);
|
||||
struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
|
||||
struct tegra_dsi *dsi = to_dsi(output);
|
||||
struct tegra_dsi_state *state;
|
||||
u32 value;
|
||||
|
||||
state = tegra_dsi_get_state(dsi);
|
||||
|
||||
tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
|
||||
|
||||
/*
|
||||
* The D-PHY timing fields are expressed in byte-clock cycles, so
|
||||
* multiply the period by 8.
|
||||
*/
|
||||
tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
|
||||
|
||||
if (output->panel)
|
||||
drm_panel_prepare(output->panel);
|
||||
|
||||
tegra_dsi_configure(dsi, dc->pipe, mode);
|
||||
|
||||
/* enable display controller */
|
||||
value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
|
||||
value |= DSI_ENABLE;
|
||||
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
|
||||
|
||||
tegra_dc_commit(dc);
|
||||
|
||||
/* enable DSI controller */
|
||||
tegra_dsi_enable(dsi);
|
||||
|
||||
if (output->panel)
|
||||
drm_panel_enable(output->panel);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
|
||||
{
|
||||
struct tegra_output *output = encoder_to_output(encoder);
|
||||
|
|
@ -875,6 +834,46 @@ static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
|
|||
return;
|
||||
}
|
||||
|
||||
static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
|
||||
{
|
||||
struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
|
||||
struct tegra_output *output = encoder_to_output(encoder);
|
||||
struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
|
||||
struct tegra_dsi *dsi = to_dsi(output);
|
||||
struct tegra_dsi_state *state;
|
||||
u32 value;
|
||||
|
||||
state = tegra_dsi_get_state(dsi);
|
||||
|
||||
tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
|
||||
|
||||
/*
|
||||
* The D-PHY timing fields are expressed in byte-clock cycles, so
|
||||
* multiply the period by 8.
|
||||
*/
|
||||
tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
|
||||
|
||||
if (output->panel)
|
||||
drm_panel_prepare(output->panel);
|
||||
|
||||
tegra_dsi_configure(dsi, dc->pipe, mode);
|
||||
|
||||
/* enable display controller */
|
||||
value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
|
||||
value |= DSI_ENABLE;
|
||||
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
|
||||
|
||||
tegra_dc_commit(dc);
|
||||
|
||||
/* enable DSI controller */
|
||||
tegra_dsi_enable(dsi);
|
||||
|
||||
if (output->panel)
|
||||
drm_panel_enable(output->panel);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static int
|
||||
tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder,
|
||||
struct drm_crtc_state *crtc_state,
|
||||
|
|
@ -957,11 +956,8 @@ tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder,
|
|||
}
|
||||
|
||||
static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
|
||||
.dpms = tegra_dsi_encoder_dpms,
|
||||
.prepare = tegra_dsi_encoder_prepare,
|
||||
.commit = tegra_dsi_encoder_commit,
|
||||
.mode_set = tegra_dsi_encoder_mode_set,
|
||||
.disable = tegra_dsi_encoder_disable,
|
||||
.enable = tegra_dsi_encoder_enable,
|
||||
.atomic_check = tegra_dsi_encoder_atomic_check,
|
||||
};
|
||||
|
||||
|
|
@ -993,6 +989,10 @@ static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
|
|||
DSI_PAD_OUT_CLK(0x0);
|
||||
tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
|
||||
|
||||
value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
|
||||
DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
|
||||
tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
|
||||
|
||||
return tegra_mipi_calibrate(dsi->mipi);
|
||||
}
|
||||
|
||||
|
|
@ -1622,6 +1622,9 @@ static int tegra_dsi_remove(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
static const struct of_device_id tegra_dsi_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra210-dsi", },
|
||||
{ .compatible = "nvidia,tegra132-dsi", },
|
||||
{ .compatible = "nvidia,tegra124-dsi", },
|
||||
{ .compatible = "nvidia,tegra114-dsi", },
|
||||
{ },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -113,6 +113,10 @@
|
|||
#define DSI_PAD_SLEW_DN(x) (((x) & 0x7) << 12)
|
||||
#define DSI_PAD_SLEW_UP(x) (((x) & 0x7) << 16)
|
||||
#define DSI_PAD_CONTROL_3 0x51
|
||||
#define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12)
|
||||
#define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8)
|
||||
#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4)
|
||||
#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0)
|
||||
#define DSI_PAD_CONTROL_4 0x52
|
||||
#define DSI_GANGED_MODE_CONTROL 0x53
|
||||
#define DSI_GANGED_MODE_CONTROL_ENABLE (1 << 0)
|
||||
|
|
|
|||
|
|
@ -772,14 +772,8 @@ static bool tegra_output_is_hdmi(struct tegra_output *output)
|
|||
return drm_detect_hdmi_monitor(edid);
|
||||
}
|
||||
|
||||
static int tegra_hdmi_connector_dpms(struct drm_connector *connector,
|
||||
int mode)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
|
||||
.dpms = tegra_hdmi_connector_dpms,
|
||||
.dpms = drm_atomic_helper_connector_dpms,
|
||||
.reset = drm_atomic_helper_connector_reset,
|
||||
.detect = tegra_output_connector_detect,
|
||||
.fill_modes = drm_helper_probe_single_connector_modes,
|
||||
|
|
@ -819,22 +813,27 @@ static const struct drm_encoder_funcs tegra_hdmi_encoder_funcs = {
|
|||
.destroy = tegra_output_encoder_destroy,
|
||||
};
|
||||
|
||||
static void tegra_hdmi_encoder_dpms(struct drm_encoder *encoder, int mode)
|
||||
static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
|
||||
{
|
||||
struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
|
||||
u32 value;
|
||||
|
||||
/*
|
||||
* The following accesses registers of the display controller, so make
|
||||
* sure it's only executed when the output is attached to one.
|
||||
*/
|
||||
if (dc) {
|
||||
value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
|
||||
value &= ~HDMI_ENABLE;
|
||||
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
|
||||
|
||||
tegra_dc_commit(dc);
|
||||
}
|
||||
}
|
||||
|
||||
static void tegra_hdmi_encoder_prepare(struct drm_encoder *encoder)
|
||||
{
|
||||
}
|
||||
|
||||
static void tegra_hdmi_encoder_commit(struct drm_encoder *encoder)
|
||||
{
|
||||
}
|
||||
|
||||
static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted)
|
||||
static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
|
||||
{
|
||||
struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
|
||||
unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
|
||||
struct tegra_output *output = encoder_to_output(encoder);
|
||||
struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
|
||||
|
|
@ -873,13 +872,13 @@ static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder,
|
|||
|
||||
tegra_dc_writel(dc, VSYNC_H_POSITION(1),
|
||||
DC_DISP_DISP_TIMING_OPTIONS);
|
||||
tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
|
||||
tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
|
||||
DC_DISP_DISP_COLOR_CONTROL);
|
||||
|
||||
/* video_preamble uses h_pulse2 */
|
||||
pulse_start = 1 + h_sync_width + h_back_porch - 10;
|
||||
|
||||
tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
|
||||
tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
|
||||
|
||||
value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
|
||||
PULSE_LAST_END_A;
|
||||
|
|
@ -1036,24 +1035,6 @@ static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder,
|
|||
/* TODO: add HDCP support */
|
||||
}
|
||||
|
||||
static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
|
||||
{
|
||||
struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
|
||||
u32 value;
|
||||
|
||||
/*
|
||||
* The following accesses registers of the display controller, so make
|
||||
* sure it's only executed when the output is attached to one.
|
||||
*/
|
||||
if (dc) {
|
||||
value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
|
||||
value &= ~HDMI_ENABLE;
|
||||
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
|
||||
|
||||
tegra_dc_commit(dc);
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
|
||||
struct drm_crtc_state *crtc_state,
|
||||
|
|
@ -1076,11 +1057,8 @@ tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
|
|||
}
|
||||
|
||||
static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
|
||||
.dpms = tegra_hdmi_encoder_dpms,
|
||||
.prepare = tegra_hdmi_encoder_prepare,
|
||||
.commit = tegra_hdmi_encoder_commit,
|
||||
.mode_set = tegra_hdmi_encoder_mode_set,
|
||||
.disable = tegra_hdmi_encoder_disable,
|
||||
.enable = tegra_hdmi_encoder_enable,
|
||||
.atomic_check = tegra_hdmi_encoder_atomic_check,
|
||||
};
|
||||
|
||||
|
|
@ -1088,11 +1066,16 @@ static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
|
|||
{
|
||||
struct drm_info_node *node = s->private;
|
||||
struct tegra_hdmi *hdmi = node->info_ent->data;
|
||||
int err;
|
||||
struct drm_crtc *crtc = hdmi->output.encoder.crtc;
|
||||
struct drm_device *drm = node->minor->dev;
|
||||
int err = 0;
|
||||
|
||||
err = clk_prepare_enable(hdmi->clk);
|
||||
if (err)
|
||||
return err;
|
||||
drm_modeset_lock_all(drm);
|
||||
|
||||
if (!crtc || !crtc->state->active) {
|
||||
err = -EBUSY;
|
||||
goto unlock;
|
||||
}
|
||||
|
||||
#define DUMP_REG(name) \
|
||||
seq_printf(s, "%-56s %#05x %08x\n", #name, name, \
|
||||
|
|
@ -1259,9 +1242,9 @@ static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
|
|||
|
||||
#undef DUMP_REG
|
||||
|
||||
clk_disable_unprepare(hdmi->clk);
|
||||
|
||||
return 0;
|
||||
unlock:
|
||||
drm_modeset_unlock_all(drm);
|
||||
return err;
|
||||
}
|
||||
|
||||
static struct drm_info_list debugfs_files[] = {
|
||||
|
|
|
|||
|
|
@ -7,8 +7,6 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/of_gpio.h>
|
||||
|
||||
#include <drm/drm_atomic_helper.h>
|
||||
#include <drm/drm_panel.h>
|
||||
#include "drm.h"
|
||||
|
|
@ -59,10 +57,17 @@ tegra_output_connector_detect(struct drm_connector *connector, bool force)
|
|||
enum drm_connector_status status = connector_status_unknown;
|
||||
|
||||
if (gpio_is_valid(output->hpd_gpio)) {
|
||||
if (gpio_get_value(output->hpd_gpio) == 0)
|
||||
status = connector_status_disconnected;
|
||||
else
|
||||
status = connector_status_connected;
|
||||
if (output->hpd_gpio_flags & OF_GPIO_ACTIVE_LOW) {
|
||||
if (gpio_get_value(output->hpd_gpio) != 0)
|
||||
status = connector_status_disconnected;
|
||||
else
|
||||
status = connector_status_connected;
|
||||
} else {
|
||||
if (gpio_get_value(output->hpd_gpio) == 0)
|
||||
status = connector_status_disconnected;
|
||||
else
|
||||
status = connector_status_connected;
|
||||
}
|
||||
} else {
|
||||
if (!output->panel)
|
||||
status = connector_status_disconnected;
|
||||
|
|
@ -97,7 +102,6 @@ static irqreturn_t hpd_irq(int irq, void *data)
|
|||
int tegra_output_probe(struct tegra_output *output)
|
||||
{
|
||||
struct device_node *ddc, *panel;
|
||||
enum of_gpio_flags flags;
|
||||
int err, size;
|
||||
|
||||
if (!output->of_node)
|
||||
|
|
@ -128,7 +132,7 @@ int tegra_output_probe(struct tegra_output *output)
|
|||
|
||||
output->hpd_gpio = of_get_named_gpio_flags(output->of_node,
|
||||
"nvidia,hpd-gpio", 0,
|
||||
&flags);
|
||||
&output->hpd_gpio_flags);
|
||||
if (gpio_is_valid(output->hpd_gpio)) {
|
||||
unsigned long flags;
|
||||
|
||||
|
|
|
|||
|
|
@ -18,7 +18,6 @@
|
|||
struct tegra_rgb {
|
||||
struct tegra_output output;
|
||||
struct tegra_dc *dc;
|
||||
bool enabled;
|
||||
|
||||
struct clk *clk_parent;
|
||||
struct clk *clk;
|
||||
|
|
@ -88,14 +87,8 @@ static void tegra_dc_write_regs(struct tegra_dc *dc,
|
|||
tegra_dc_writel(dc, table[i].value, table[i].offset);
|
||||
}
|
||||
|
||||
static int tegra_rgb_connector_dpms(struct drm_connector *connector,
|
||||
int mode)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct drm_connector_funcs tegra_rgb_connector_funcs = {
|
||||
.dpms = tegra_rgb_connector_dpms,
|
||||
.dpms = drm_atomic_helper_connector_dpms,
|
||||
.reset = drm_atomic_helper_connector_reset,
|
||||
.detect = tegra_output_connector_detect,
|
||||
.fill_modes = drm_helper_probe_single_connector_modes,
|
||||
|
|
@ -126,21 +119,22 @@ static const struct drm_encoder_funcs tegra_rgb_encoder_funcs = {
|
|||
.destroy = tegra_output_encoder_destroy,
|
||||
};
|
||||
|
||||
static void tegra_rgb_encoder_dpms(struct drm_encoder *encoder, int mode)
|
||||
static void tegra_rgb_encoder_disable(struct drm_encoder *encoder)
|
||||
{
|
||||
struct tegra_output *output = encoder_to_output(encoder);
|
||||
struct tegra_rgb *rgb = to_rgb(output);
|
||||
|
||||
if (output->panel)
|
||||
drm_panel_disable(output->panel);
|
||||
|
||||
tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
|
||||
tegra_dc_commit(rgb->dc);
|
||||
|
||||
if (output->panel)
|
||||
drm_panel_unprepare(output->panel);
|
||||
}
|
||||
|
||||
static void tegra_rgb_encoder_prepare(struct drm_encoder *encoder)
|
||||
{
|
||||
}
|
||||
|
||||
static void tegra_rgb_encoder_commit(struct drm_encoder *encoder)
|
||||
{
|
||||
}
|
||||
|
||||
static void tegra_rgb_encoder_mode_set(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted)
|
||||
static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
|
||||
{
|
||||
struct tegra_output *output = encoder_to_output(encoder);
|
||||
struct tegra_rgb *rgb = to_rgb(output);
|
||||
|
|
@ -175,21 +169,6 @@ static void tegra_rgb_encoder_mode_set(struct drm_encoder *encoder,
|
|||
drm_panel_enable(output->panel);
|
||||
}
|
||||
|
||||
static void tegra_rgb_encoder_disable(struct drm_encoder *encoder)
|
||||
{
|
||||
struct tegra_output *output = encoder_to_output(encoder);
|
||||
struct tegra_rgb *rgb = to_rgb(output);
|
||||
|
||||
if (output->panel)
|
||||
drm_panel_disable(output->panel);
|
||||
|
||||
tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
|
||||
tegra_dc_commit(rgb->dc);
|
||||
|
||||
if (output->panel)
|
||||
drm_panel_unprepare(output->panel);
|
||||
}
|
||||
|
||||
static int
|
||||
tegra_rgb_encoder_atomic_check(struct drm_encoder *encoder,
|
||||
struct drm_crtc_state *crtc_state,
|
||||
|
|
@ -232,11 +211,8 @@ tegra_rgb_encoder_atomic_check(struct drm_encoder *encoder,
|
|||
}
|
||||
|
||||
static const struct drm_encoder_helper_funcs tegra_rgb_encoder_helper_funcs = {
|
||||
.dpms = tegra_rgb_encoder_dpms,
|
||||
.prepare = tegra_rgb_encoder_prepare,
|
||||
.commit = tegra_rgb_encoder_commit,
|
||||
.mode_set = tegra_rgb_encoder_mode_set,
|
||||
.disable = tegra_rgb_encoder_disable,
|
||||
.enable = tegra_rgb_encoder_enable,
|
||||
.atomic_check = tegra_rgb_encoder_atomic_check,
|
||||
};
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -11,9 +11,9 @@
|
|||
|
||||
#define SOR_CTXSW 0x00
|
||||
|
||||
#define SOR_SUPER_STATE_0 0x01
|
||||
#define SOR_SUPER_STATE0 0x01
|
||||
|
||||
#define SOR_SUPER_STATE_1 0x02
|
||||
#define SOR_SUPER_STATE1 0x02
|
||||
#define SOR_SUPER_STATE_ATTACHED (1 << 3)
|
||||
#define SOR_SUPER_STATE_MODE_NORMAL (1 << 2)
|
||||
#define SOR_SUPER_STATE_HEAD_MODE_MASK (3 << 0)
|
||||
|
|
@ -21,9 +21,9 @@
|
|||
#define SOR_SUPER_STATE_HEAD_MODE_SNOOZE (1 << 0)
|
||||
#define SOR_SUPER_STATE_HEAD_MODE_SLEEP (0 << 0)
|
||||
|
||||
#define SOR_STATE_0 0x03
|
||||
#define SOR_STATE0 0x03
|
||||
|
||||
#define SOR_STATE_1 0x04
|
||||
#define SOR_STATE1 0x04
|
||||
#define SOR_STATE_ASY_PIXELDEPTH_MASK (0xf << 17)
|
||||
#define SOR_STATE_ASY_PIXELDEPTH_BPP_18_444 (0x2 << 17)
|
||||
#define SOR_STATE_ASY_PIXELDEPTH_BPP_24_444 (0x5 << 17)
|
||||
|
|
@ -33,19 +33,27 @@
|
|||
#define SOR_STATE_ASY_PROTOCOL_CUSTOM (0xf << 8)
|
||||
#define SOR_STATE_ASY_PROTOCOL_DP_A (0x8 << 8)
|
||||
#define SOR_STATE_ASY_PROTOCOL_DP_B (0x9 << 8)
|
||||
#define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A (0x1 << 8)
|
||||
#define SOR_STATE_ASY_PROTOCOL_LVDS (0x0 << 8)
|
||||
#define SOR_STATE_ASY_CRC_MODE_MASK (0x3 << 6)
|
||||
#define SOR_STATE_ASY_CRC_MODE_NON_ACTIVE (0x2 << 6)
|
||||
#define SOR_STATE_ASY_CRC_MODE_COMPLETE (0x1 << 6)
|
||||
#define SOR_STATE_ASY_CRC_MODE_ACTIVE (0x0 << 6)
|
||||
#define SOR_STATE_ASY_OWNER_MASK 0xf
|
||||
#define SOR_STATE_ASY_OWNER(x) (((x) & 0xf) << 0)
|
||||
|
||||
#define SOR_HEAD_STATE_0(x) (0x05 + (x))
|
||||
#define SOR_HEAD_STATE_1(x) (0x07 + (x))
|
||||
#define SOR_HEAD_STATE_2(x) (0x09 + (x))
|
||||
#define SOR_HEAD_STATE_3(x) (0x0b + (x))
|
||||
#define SOR_HEAD_STATE_4(x) (0x0d + (x))
|
||||
#define SOR_HEAD_STATE_5(x) (0x0f + (x))
|
||||
#define SOR_HEAD_STATE0(x) (0x05 + (x))
|
||||
#define SOR_HEAD_STATE_RANGECOMPRESS_MASK (0x1 << 3)
|
||||
#define SOR_HEAD_STATE_DYNRANGE_MASK (0x1 << 2)
|
||||
#define SOR_HEAD_STATE_DYNRANGE_VESA (0 << 2)
|
||||
#define SOR_HEAD_STATE_DYNRANGE_CEA (1 << 2)
|
||||
#define SOR_HEAD_STATE_COLORSPACE_MASK (0x3 << 0)
|
||||
#define SOR_HEAD_STATE_COLORSPACE_RGB (0 << 0)
|
||||
#define SOR_HEAD_STATE1(x) (0x07 + (x))
|
||||
#define SOR_HEAD_STATE2(x) (0x09 + (x))
|
||||
#define SOR_HEAD_STATE3(x) (0x0b + (x))
|
||||
#define SOR_HEAD_STATE4(x) (0x0d + (x))
|
||||
#define SOR_HEAD_STATE5(x) (0x0f + (x))
|
||||
#define SOR_CRC_CNTRL 0x11
|
||||
#define SOR_CRC_CNTRL_ENABLE (1 << 0)
|
||||
#define SOR_DP_DEBUG_MVID 0x12
|
||||
|
|
@ -75,62 +83,101 @@
|
|||
#define SOR_TEST_HEAD_MODE_MASK (3 << 8)
|
||||
#define SOR_TEST_HEAD_MODE_AWAKE (2 << 8)
|
||||
|
||||
#define SOR_PLL_0 0x17
|
||||
#define SOR_PLL_0_ICHPMP_MASK (0xf << 24)
|
||||
#define SOR_PLL_0_ICHPMP(x) (((x) & 0xf) << 24)
|
||||
#define SOR_PLL_0_VCOCAP_MASK (0xf << 8)
|
||||
#define SOR_PLL_0_VCOCAP(x) (((x) & 0xf) << 8)
|
||||
#define SOR_PLL_0_VCOCAP_RST SOR_PLL_0_VCOCAP(3)
|
||||
#define SOR_PLL_0_PLLREG_MASK (0x3 << 6)
|
||||
#define SOR_PLL_0_PLLREG_LEVEL(x) (((x) & 0x3) << 6)
|
||||
#define SOR_PLL_0_PLLREG_LEVEL_V25 SOR_PLL_0_PLLREG_LEVEL(0)
|
||||
#define SOR_PLL_0_PLLREG_LEVEL_V15 SOR_PLL_0_PLLREG_LEVEL(1)
|
||||
#define SOR_PLL_0_PLLREG_LEVEL_V35 SOR_PLL_0_PLLREG_LEVEL(2)
|
||||
#define SOR_PLL_0_PLLREG_LEVEL_V45 SOR_PLL_0_PLLREG_LEVEL(3)
|
||||
#define SOR_PLL_0_PULLDOWN (1 << 5)
|
||||
#define SOR_PLL_0_RESISTOR_EXT (1 << 4)
|
||||
#define SOR_PLL_0_VCOPD (1 << 2)
|
||||
#define SOR_PLL_0_POWER_OFF (1 << 0)
|
||||
#define SOR_PLL0 0x17
|
||||
#define SOR_PLL0_ICHPMP_MASK (0xf << 24)
|
||||
#define SOR_PLL0_ICHPMP(x) (((x) & 0xf) << 24)
|
||||
#define SOR_PLL0_VCOCAP_MASK (0xf << 8)
|
||||
#define SOR_PLL0_VCOCAP(x) (((x) & 0xf) << 8)
|
||||
#define SOR_PLL0_VCOCAP_RST SOR_PLL0_VCOCAP(3)
|
||||
#define SOR_PLL0_PLLREG_MASK (0x3 << 6)
|
||||
#define SOR_PLL0_PLLREG_LEVEL(x) (((x) & 0x3) << 6)
|
||||
#define SOR_PLL0_PLLREG_LEVEL_V25 SOR_PLL0_PLLREG_LEVEL(0)
|
||||
#define SOR_PLL0_PLLREG_LEVEL_V15 SOR_PLL0_PLLREG_LEVEL(1)
|
||||
#define SOR_PLL0_PLLREG_LEVEL_V35 SOR_PLL0_PLLREG_LEVEL(2)
|
||||
#define SOR_PLL0_PLLREG_LEVEL_V45 SOR_PLL0_PLLREG_LEVEL(3)
|
||||
#define SOR_PLL0_PULLDOWN (1 << 5)
|
||||
#define SOR_PLL0_RESISTOR_EXT (1 << 4)
|
||||
#define SOR_PLL0_VCOPD (1 << 2)
|
||||
#define SOR_PLL0_PWR (1 << 0)
|
||||
|
||||
#define SOR_PLL_1 0x18
|
||||
#define SOR_PLL1 0x18
|
||||
/* XXX: read-only bit? */
|
||||
#define SOR_PLL_1_TERM_COMPOUT (1 << 15)
|
||||
#define SOR_PLL_1_TMDS_TERM (1 << 8)
|
||||
#define SOR_PLL1_LOADADJ_MASK (0xf << 20)
|
||||
#define SOR_PLL1_LOADADJ(x) (((x) & 0xf) << 20)
|
||||
#define SOR_PLL1_TERM_COMPOUT (1 << 15)
|
||||
#define SOR_PLL1_TMDS_TERMADJ_MASK (0xf << 9)
|
||||
#define SOR_PLL1_TMDS_TERMADJ(x) (((x) & 0xf) << 9)
|
||||
#define SOR_PLL1_TMDS_TERM (1 << 8)
|
||||
|
||||
#define SOR_PLL_2 0x19
|
||||
#define SOR_PLL_2_LVDS_ENABLE (1 << 25)
|
||||
#define SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE (1 << 24)
|
||||
#define SOR_PLL_2_PORT_POWERDOWN (1 << 23)
|
||||
#define SOR_PLL_2_BANDGAP_POWERDOWN (1 << 22)
|
||||
#define SOR_PLL_2_POWERDOWN_OVERRIDE (1 << 18)
|
||||
#define SOR_PLL_2_SEQ_PLLCAPPD (1 << 17)
|
||||
#define SOR_PLL2 0x19
|
||||
#define SOR_PLL2_LVDS_ENABLE (1 << 25)
|
||||
#define SOR_PLL2_SEQ_PLLCAPPD_ENFORCE (1 << 24)
|
||||
#define SOR_PLL2_PORT_POWERDOWN (1 << 23)
|
||||
#define SOR_PLL2_BANDGAP_POWERDOWN (1 << 22)
|
||||
#define SOR_PLL2_POWERDOWN_OVERRIDE (1 << 18)
|
||||
#define SOR_PLL2_SEQ_PLLCAPPD (1 << 17)
|
||||
#define SOR_PLL2_SEQ_PLL_PULLDOWN (1 << 16)
|
||||
|
||||
#define SOR_PLL_3 0x1a
|
||||
#define SOR_PLL_3_PLL_VDD_MODE_V1_8 (0 << 13)
|
||||
#define SOR_PLL_3_PLL_VDD_MODE_V3_3 (1 << 13)
|
||||
#define SOR_PLL3 0x1a
|
||||
#define SOR_PLL3_BG_VREF_LEVEL_MASK (0xf << 24)
|
||||
#define SOR_PLL3_BG_VREF_LEVEL(x) (((x) & 0xf) << 24)
|
||||
#define SOR_PLL3_PLL_VDD_MODE_1V8 (0 << 13)
|
||||
#define SOR_PLL3_PLL_VDD_MODE_3V3 (1 << 13)
|
||||
|
||||
#define SOR_CSTM 0x1b
|
||||
#define SOR_CSTM_ROTCLK_MASK (0xf << 24)
|
||||
#define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24)
|
||||
#define SOR_CSTM_LVDS (1 << 16)
|
||||
#define SOR_CSTM_LINK_ACT_B (1 << 15)
|
||||
#define SOR_CSTM_LINK_ACT_A (1 << 14)
|
||||
#define SOR_CSTM_UPPER (1 << 11)
|
||||
|
||||
#define SOR_LVDS 0x1c
|
||||
#define SOR_CRC_A 0x1d
|
||||
#define SOR_CRC_A_VALID (1 << 0)
|
||||
#define SOR_CRC_A_RESET (1 << 0)
|
||||
#define SOR_CRC_B 0x1e
|
||||
#define SOR_CRCA 0x1d
|
||||
#define SOR_CRCA_VALID (1 << 0)
|
||||
#define SOR_CRCA_RESET (1 << 0)
|
||||
#define SOR_CRCB 0x1e
|
||||
#define SOR_BLANK 0x1f
|
||||
#define SOR_SEQ_CTL 0x20
|
||||
#define SOR_SEQ_CTL_PD_PC_ALT(x) (((x) & 0xf) << 12)
|
||||
#define SOR_SEQ_CTL_PD_PC(x) (((x) & 0xf) << 8)
|
||||
#define SOR_SEQ_CTL_PU_PC_ALT(x) (((x) & 0xf) << 4)
|
||||
#define SOR_SEQ_CTL_PU_PC(x) (((x) & 0xf) << 0)
|
||||
|
||||
#define SOR_LANE_SEQ_CTL 0x21
|
||||
#define SOR_LANE_SEQ_CTL_TRIGGER (1 << 31)
|
||||
#define SOR_LANE_SEQ_CTL_STATE_BUSY (1 << 28)
|
||||
#define SOR_LANE_SEQ_CTL_SEQUENCE_UP (0 << 20)
|
||||
#define SOR_LANE_SEQ_CTL_SEQUENCE_DOWN (1 << 20)
|
||||
#define SOR_LANE_SEQ_CTL_POWER_STATE_UP (0 << 16)
|
||||
#define SOR_LANE_SEQ_CTL_POWER_STATE_DOWN (1 << 16)
|
||||
#define SOR_LANE_SEQ_CTL_DELAY(x) (((x) & 0xf) << 12)
|
||||
|
||||
#define SOR_SEQ_INST(x) (0x22 + (x))
|
||||
#define SOR_SEQ_INST_PLL_PULLDOWN (1 << 31)
|
||||
#define SOR_SEQ_INST_POWERDOWN_MACRO (1 << 30)
|
||||
#define SOR_SEQ_INST_ASSERT_PLL_RESET (1 << 29)
|
||||
#define SOR_SEQ_INST_BLANK_V (1 << 28)
|
||||
#define SOR_SEQ_INST_BLANK_H (1 << 27)
|
||||
#define SOR_SEQ_INST_BLANK_DE (1 << 26)
|
||||
#define SOR_SEQ_INST_BLACK_DATA (1 << 25)
|
||||
#define SOR_SEQ_INST_TRISTATE_IOS (1 << 24)
|
||||
#define SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23)
|
||||
#define SOR_SEQ_INST_PIN_B_LOW (0 << 22)
|
||||
#define SOR_SEQ_INST_PIN_B_HIGH (1 << 22)
|
||||
#define SOR_SEQ_INST_PIN_A_LOW (0 << 21)
|
||||
#define SOR_SEQ_INST_PIN_A_HIGH (1 << 21)
|
||||
#define SOR_SEQ_INST_SEQUENCE_UP (0 << 19)
|
||||
#define SOR_SEQ_INST_SEQUENCE_DOWN (1 << 19)
|
||||
#define SOR_SEQ_INST_LANE_SEQ_STOP (0 << 18)
|
||||
#define SOR_SEQ_INST_LANE_SEQ_RUN (1 << 18)
|
||||
#define SOR_SEQ_INST_PORT_POWERDOWN (1 << 17)
|
||||
#define SOR_SEQ_INST_PLL_POWERDOWN (1 << 16)
|
||||
#define SOR_SEQ_INST_HALT (1 << 15)
|
||||
#define SOR_SEQ_INST_WAIT_US (0 << 12)
|
||||
#define SOR_SEQ_INST_WAIT_MS (1 << 12)
|
||||
#define SOR_SEQ_INST_WAIT_VSYNC (2 << 12)
|
||||
#define SOR_SEQ_INST_WAIT(x) (((x) & 0x3ff) << 0)
|
||||
|
||||
#define SOR_PWM_DIV 0x32
|
||||
#define SOR_PWM_DIV_MASK 0xffffff
|
||||
|
|
@ -140,32 +187,36 @@
|
|||
#define SOR_PWM_CTL_CLK_SEL (1 << 30)
|
||||
#define SOR_PWM_CTL_DUTY_CYCLE_MASK 0xffffff
|
||||
|
||||
#define SOR_VCRC_A_0 0x34
|
||||
#define SOR_VCRC_A_1 0x35
|
||||
#define SOR_VCRC_B_0 0x36
|
||||
#define SOR_VCRC_B_1 0x37
|
||||
#define SOR_CCRC_A_0 0x38
|
||||
#define SOR_CCRC_A_1 0x39
|
||||
#define SOR_CCRC_B_0 0x3a
|
||||
#define SOR_CCRC_B_1 0x3b
|
||||
#define SOR_EDATA_A_0 0x3c
|
||||
#define SOR_EDATA_A_1 0x3d
|
||||
#define SOR_EDATA_B_0 0x3e
|
||||
#define SOR_EDATA_B_1 0x3f
|
||||
#define SOR_COUNT_A_0 0x40
|
||||
#define SOR_COUNT_A_1 0x41
|
||||
#define SOR_COUNT_B_0 0x42
|
||||
#define SOR_COUNT_B_1 0x43
|
||||
#define SOR_DEBUG_A_0 0x44
|
||||
#define SOR_DEBUG_A_1 0x45
|
||||
#define SOR_DEBUG_B_0 0x46
|
||||
#define SOR_DEBUG_B_1 0x47
|
||||
#define SOR_VCRC_A0 0x34
|
||||
#define SOR_VCRC_A1 0x35
|
||||
#define SOR_VCRC_B0 0x36
|
||||
#define SOR_VCRC_B1 0x37
|
||||
#define SOR_CCRC_A0 0x38
|
||||
#define SOR_CCRC_A1 0x39
|
||||
#define SOR_CCRC_B0 0x3a
|
||||
#define SOR_CCRC_B1 0x3b
|
||||
#define SOR_EDATA_A0 0x3c
|
||||
#define SOR_EDATA_A1 0x3d
|
||||
#define SOR_EDATA_B0 0x3e
|
||||
#define SOR_EDATA_B1 0x3f
|
||||
#define SOR_COUNT_A0 0x40
|
||||
#define SOR_COUNT_A1 0x41
|
||||
#define SOR_COUNT_B0 0x42
|
||||
#define SOR_COUNT_B1 0x43
|
||||
#define SOR_DEBUG_A0 0x44
|
||||
#define SOR_DEBUG_A1 0x45
|
||||
#define SOR_DEBUG_B0 0x46
|
||||
#define SOR_DEBUG_B1 0x47
|
||||
#define SOR_TRIG 0x48
|
||||
#define SOR_MSCHECK 0x49
|
||||
#define SOR_XBAR_CTRL 0x4a
|
||||
#define SOR_XBAR_CTRL_LINK1_XSEL(channel, value) ((((value) & 0x7) << ((channel) * 3)) << 17)
|
||||
#define SOR_XBAR_CTRL_LINK0_XSEL(channel, value) ((((value) & 0x7) << ((channel) * 3)) << 2)
|
||||
#define SOR_XBAR_CTRL_LINK_SWAP (1 << 1)
|
||||
#define SOR_XBAR_CTRL_BYPASS (1 << 0)
|
||||
#define SOR_XBAR_POL 0x4b
|
||||
|
||||
#define SOR_DP_LINKCTL_0 0x4c
|
||||
#define SOR_DP_LINKCTL0 0x4c
|
||||
#define SOR_DP_LINKCTL_LANE_COUNT_MASK (0x1f << 16)
|
||||
#define SOR_DP_LINKCTL_LANE_COUNT(x) (((1 << (x)) - 1) << 16)
|
||||
#define SOR_DP_LINKCTL_ENHANCED_FRAME (1 << 14)
|
||||
|
|
@ -173,34 +224,34 @@
|
|||
#define SOR_DP_LINKCTL_TU_SIZE(x) (((x) & 0x7f) << 2)
|
||||
#define SOR_DP_LINKCTL_ENABLE (1 << 0)
|
||||
|
||||
#define SOR_DP_LINKCTL_1 0x4d
|
||||
#define SOR_DP_LINKCTL1 0x4d
|
||||
|
||||
#define SOR_LANE_DRIVE_CURRENT_0 0x4e
|
||||
#define SOR_LANE_DRIVE_CURRENT_1 0x4f
|
||||
#define SOR_LANE4_DRIVE_CURRENT_0 0x50
|
||||
#define SOR_LANE4_DRIVE_CURRENT_1 0x51
|
||||
#define SOR_LANE_DRIVE_CURRENT0 0x4e
|
||||
#define SOR_LANE_DRIVE_CURRENT1 0x4f
|
||||
#define SOR_LANE4_DRIVE_CURRENT0 0x50
|
||||
#define SOR_LANE4_DRIVE_CURRENT1 0x51
|
||||
#define SOR_LANE_DRIVE_CURRENT_LANE3(x) (((x) & 0xff) << 24)
|
||||
#define SOR_LANE_DRIVE_CURRENT_LANE2(x) (((x) & 0xff) << 16)
|
||||
#define SOR_LANE_DRIVE_CURRENT_LANE1(x) (((x) & 0xff) << 8)
|
||||
#define SOR_LANE_DRIVE_CURRENT_LANE0(x) (((x) & 0xff) << 0)
|
||||
|
||||
#define SOR_LANE_PREEMPHASIS_0 0x52
|
||||
#define SOR_LANE_PREEMPHASIS_1 0x53
|
||||
#define SOR_LANE4_PREEMPHASIS_0 0x54
|
||||
#define SOR_LANE4_PREEMPHASIS_1 0x55
|
||||
#define SOR_LANE_PREEMPHASIS0 0x52
|
||||
#define SOR_LANE_PREEMPHASIS1 0x53
|
||||
#define SOR_LANE4_PREEMPHASIS0 0x54
|
||||
#define SOR_LANE4_PREEMPHASIS1 0x55
|
||||
#define SOR_LANE_PREEMPHASIS_LANE3(x) (((x) & 0xff) << 24)
|
||||
#define SOR_LANE_PREEMPHASIS_LANE2(x) (((x) & 0xff) << 16)
|
||||
#define SOR_LANE_PREEMPHASIS_LANE1(x) (((x) & 0xff) << 8)
|
||||
#define SOR_LANE_PREEMPHASIS_LANE0(x) (((x) & 0xff) << 0)
|
||||
|
||||
#define SOR_LANE_POST_CURSOR_0 0x56
|
||||
#define SOR_LANE_POST_CURSOR_1 0x57
|
||||
#define SOR_LANE_POST_CURSOR_LANE3(x) (((x) & 0xff) << 24)
|
||||
#define SOR_LANE_POST_CURSOR_LANE2(x) (((x) & 0xff) << 16)
|
||||
#define SOR_LANE_POST_CURSOR_LANE1(x) (((x) & 0xff) << 8)
|
||||
#define SOR_LANE_POST_CURSOR_LANE0(x) (((x) & 0xff) << 0)
|
||||
#define SOR_LANE_POSTCURSOR0 0x56
|
||||
#define SOR_LANE_POSTCURSOR1 0x57
|
||||
#define SOR_LANE_POSTCURSOR_LANE3(x) (((x) & 0xff) << 24)
|
||||
#define SOR_LANE_POSTCURSOR_LANE2(x) (((x) & 0xff) << 16)
|
||||
#define SOR_LANE_POSTCURSOR_LANE1(x) (((x) & 0xff) << 8)
|
||||
#define SOR_LANE_POSTCURSOR_LANE0(x) (((x) & 0xff) << 0)
|
||||
|
||||
#define SOR_DP_CONFIG_0 0x58
|
||||
#define SOR_DP_CONFIG0 0x58
|
||||
#define SOR_DP_CONFIG_DISPARITY_NEGATIVE (1 << 31)
|
||||
#define SOR_DP_CONFIG_ACTIVE_SYM_ENABLE (1 << 26)
|
||||
#define SOR_DP_CONFIG_ACTIVE_SYM_POLARITY (1 << 24)
|
||||
|
|
@ -211,11 +262,11 @@
|
|||
#define SOR_DP_CONFIG_WATERMARK_MASK (0x3f << 0)
|
||||
#define SOR_DP_CONFIG_WATERMARK(x) (((x) & 0x3f) << 0)
|
||||
|
||||
#define SOR_DP_CONFIG_1 0x59
|
||||
#define SOR_DP_MN_0 0x5a
|
||||
#define SOR_DP_MN_1 0x5b
|
||||
#define SOR_DP_CONFIG1 0x59
|
||||
#define SOR_DP_MN0 0x5a
|
||||
#define SOR_DP_MN1 0x5b
|
||||
|
||||
#define SOR_DP_PADCTL_0 0x5c
|
||||
#define SOR_DP_PADCTL0 0x5c
|
||||
#define SOR_DP_PADCTL_PAD_CAL_PD (1 << 23)
|
||||
#define SOR_DP_PADCTL_TX_PU_ENABLE (1 << 22)
|
||||
#define SOR_DP_PADCTL_TX_PU_MASK (0xff << 8)
|
||||
|
|
@ -229,17 +280,18 @@
|
|||
#define SOR_DP_PADCTL_PD_TXD_1 (1 << 1)
|
||||
#define SOR_DP_PADCTL_PD_TXD_2 (1 << 0)
|
||||
|
||||
#define SOR_DP_PADCTL_1 0x5d
|
||||
#define SOR_DP_PADCTL1 0x5d
|
||||
|
||||
#define SOR_DP_DEBUG_0 0x5e
|
||||
#define SOR_DP_DEBUG_1 0x5f
|
||||
#define SOR_DP_DEBUG0 0x5e
|
||||
#define SOR_DP_DEBUG1 0x5f
|
||||
|
||||
#define SOR_DP_SPARE_0 0x60
|
||||
#define SOR_DP_SPARE_MACRO_SOR_CLK (1 << 2)
|
||||
#define SOR_DP_SPARE_PANEL_INTERNAL (1 << 1)
|
||||
#define SOR_DP_SPARE_SEQ_ENABLE (1 << 0)
|
||||
#define SOR_DP_SPARE0 0x60
|
||||
#define SOR_DP_SPARE_DISP_VIDEO_PREAMBLE (1 << 3)
|
||||
#define SOR_DP_SPARE_MACRO_SOR_CLK (1 << 2)
|
||||
#define SOR_DP_SPARE_PANEL_INTERNAL (1 << 1)
|
||||
#define SOR_DP_SPARE_SEQ_ENABLE (1 << 0)
|
||||
|
||||
#define SOR_DP_SPARE_1 0x61
|
||||
#define SOR_DP_SPARE1 0x61
|
||||
#define SOR_DP_AUDIO_CTRL 0x62
|
||||
|
||||
#define SOR_DP_AUDIO_HBLANK_SYMBOLS 0x63
|
||||
|
|
@ -249,13 +301,13 @@
|
|||
#define SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK (0x1fffff << 0)
|
||||
|
||||
#define SOR_DP_GENERIC_INFOFRAME_HEADER 0x65
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_0 0x66
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_1 0x67
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_2 0x68
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_3 0x69
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_4 0x6a
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_5 0x6b
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_6 0x6c
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK0 0x66
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK1 0x67
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK2 0x68
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK3 0x69
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK4 0x6a
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK5 0x6b
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK6 0x6c
|
||||
|
||||
#define SOR_DP_TPG 0x6d
|
||||
#define SOR_DP_TPG_CHANNEL_CODING (1 << 6)
|
||||
|
|
@ -275,8 +327,44 @@
|
|||
#define SOR_DP_TPG_PATTERN_NONE (0x0 << 0)
|
||||
|
||||
#define SOR_DP_TPG_CONFIG 0x6e
|
||||
#define SOR_DP_LQ_CSTM_0 0x6f
|
||||
#define SOR_DP_LQ_CSTM_1 0x70
|
||||
#define SOR_DP_LQ_CSTM_2 0x71
|
||||
#define SOR_DP_LQ_CSTM0 0x6f
|
||||
#define SOR_DP_LQ_CSTM1 0x70
|
||||
#define SOR_DP_LQ_CSTM2 0x71
|
||||
|
||||
#define SOR_HDMI_AUDIO_INFOFRAME_CTRL 0x9a
|
||||
#define SOR_HDMI_AUDIO_INFOFRAME_STATUS 0x9b
|
||||
#define SOR_HDMI_AUDIO_INFOFRAME_HEADER 0x9c
|
||||
|
||||
#define SOR_HDMI_AVI_INFOFRAME_CTRL 0x9f
|
||||
#define INFOFRAME_CTRL_CHECKSUM_ENABLE (1 << 9)
|
||||
#define INFOFRAME_CTRL_SINGLE (1 << 8)
|
||||
#define INFOFRAME_CTRL_OTHER (1 << 4)
|
||||
#define INFOFRAME_CTRL_ENABLE (1 << 0)
|
||||
|
||||
#define SOR_HDMI_AVI_INFOFRAME_STATUS 0xa0
|
||||
#define INFOFRAME_STATUS_DONE (1 << 0)
|
||||
|
||||
#define SOR_HDMI_AVI_INFOFRAME_HEADER 0xa1
|
||||
#define INFOFRAME_HEADER_LEN(x) (((x) & 0xff) << 16)
|
||||
#define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
|
||||
#define INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
|
||||
|
||||
#define SOR_HDMI_CTRL 0xc0
|
||||
#define SOR_HDMI_CTRL_ENABLE (1 << 30)
|
||||
#define SOR_HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16)
|
||||
#define SOR_HDMI_CTRL_AUDIO_LAYOUT (1 << 10)
|
||||
#define SOR_HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0)
|
||||
|
||||
#define SOR_REFCLK 0xe6
|
||||
#define SOR_REFCLK_DIV_INT(x) ((((x) >> 2) & 0xff) << 8)
|
||||
#define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x3) << 6)
|
||||
|
||||
#define SOR_INPUT_CONTROL 0xe8
|
||||
#define SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED (1 << 1)
|
||||
#define SOR_INPUT_CONTROL_HDMI_SRC_SELECT(x) (((x) & 0x1) << 0)
|
||||
|
||||
#define SOR_HDMI_VSI_INFOFRAME_CTRL 0x123
|
||||
#define SOR_HDMI_VSI_INFOFRAME_STATUS 0x124
|
||||
#define SOR_HDMI_VSI_INFOFRAME_HEADER 0x125
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -31,6 +31,9 @@
|
|||
#include "dev.h"
|
||||
|
||||
#define MIPI_CAL_CTRL 0x00
|
||||
#define MIPI_CAL_CTRL_NOISE_FILTER(x) (((x) & 0xf) << 26)
|
||||
#define MIPI_CAL_CTRL_PRESCALE(x) (((x) & 0x3) << 24)
|
||||
#define MIPI_CAL_CTRL_CLKEN_OVR (1 << 4)
|
||||
#define MIPI_CAL_CTRL_START (1 << 0)
|
||||
|
||||
#define MIPI_CAL_AUTOCAL_CTRL 0x01
|
||||
|
|
@ -44,15 +47,18 @@
|
|||
#define MIPI_CAL_CONFIG_CSIC 0x07
|
||||
#define MIPI_CAL_CONFIG_CSID 0x08
|
||||
#define MIPI_CAL_CONFIG_CSIE 0x09
|
||||
#define MIPI_CAL_CONFIG_CSIF 0x0a
|
||||
#define MIPI_CAL_CONFIG_DSIA 0x0e
|
||||
#define MIPI_CAL_CONFIG_DSIB 0x0f
|
||||
#define MIPI_CAL_CONFIG_DSIC 0x10
|
||||
#define MIPI_CAL_CONFIG_DSID 0x11
|
||||
|
||||
#define MIPI_CAL_CONFIG_DSIAB_CLK 0x19
|
||||
#define MIPI_CAL_CONFIG_DSICD_CLK 0x1a
|
||||
#define MIPI_CAL_CONFIG_DSIA_CLK 0x19
|
||||
#define MIPI_CAL_CONFIG_DSIB_CLK 0x1a
|
||||
#define MIPI_CAL_CONFIG_CSIAB_CLK 0x1b
|
||||
#define MIPI_CAL_CONFIG_DSIC_CLK 0x1c
|
||||
#define MIPI_CAL_CONFIG_CSICD_CLK 0x1c
|
||||
#define MIPI_CAL_CONFIG_DSID_CLK 0x1d
|
||||
#define MIPI_CAL_CONFIG_CSIE_CLK 0x1d
|
||||
|
||||
/* for data and clock lanes */
|
||||
|
|
@ -73,8 +79,11 @@
|
|||
|
||||
#define MIPI_CAL_BIAS_PAD_CFG1 0x17
|
||||
#define MIPI_CAL_BIAS_PAD_DRV_DN_REF(x) (((x) & 0x7) << 16)
|
||||
#define MIPI_CAL_BIAS_PAD_DRV_UP_REF(x) (((x) & 0x7) << 8)
|
||||
|
||||
#define MIPI_CAL_BIAS_PAD_CFG2 0x18
|
||||
#define MIPI_CAL_BIAS_PAD_VCLAMP(x) (((x) & 0x7) << 16)
|
||||
#define MIPI_CAL_BIAS_PAD_VAUXP(x) (((x) & 0x7) << 4)
|
||||
#define MIPI_CAL_BIAS_PAD_PDVREG (1 << 1)
|
||||
|
||||
struct tegra_mipi_pad {
|
||||
|
|
@ -86,13 +95,35 @@ struct tegra_mipi_soc {
|
|||
bool has_clk_lane;
|
||||
const struct tegra_mipi_pad *pads;
|
||||
unsigned int num_pads;
|
||||
|
||||
bool clock_enable_override;
|
||||
bool needs_vclamp_ref;
|
||||
|
||||
/* bias pad configuration settings */
|
||||
u8 pad_drive_down_ref;
|
||||
u8 pad_drive_up_ref;
|
||||
|
||||
u8 pad_vclamp_level;
|
||||
u8 pad_vauxp_level;
|
||||
|
||||
/* calibration settings for data lanes */
|
||||
u8 hspdos;
|
||||
u8 hspuos;
|
||||
u8 termos;
|
||||
|
||||
/* calibration settings for clock lanes */
|
||||
u8 hsclkpdos;
|
||||
u8 hsclkpuos;
|
||||
};
|
||||
|
||||
struct tegra_mipi {
|
||||
const struct tegra_mipi_soc *soc;
|
||||
struct device *dev;
|
||||
void __iomem *regs;
|
||||
struct mutex lock;
|
||||
struct clk *clk;
|
||||
|
||||
unsigned long usage_count;
|
||||
};
|
||||
|
||||
struct tegra_mipi_device {
|
||||
|
|
@ -114,6 +145,67 @@ static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 value,
|
|||
writel(value, mipi->regs + (offset << 2));
|
||||
}
|
||||
|
||||
static int tegra_mipi_power_up(struct tegra_mipi *mipi)
|
||||
{
|
||||
u32 value;
|
||||
int err;
|
||||
|
||||
err = clk_enable(mipi->clk);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG0);
|
||||
value &= ~MIPI_CAL_BIAS_PAD_PDVCLAMP;
|
||||
|
||||
if (mipi->soc->needs_vclamp_ref)
|
||||
value |= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
|
||||
|
||||
tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
|
||||
|
||||
value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG2);
|
||||
value &= ~MIPI_CAL_BIAS_PAD_PDVREG;
|
||||
tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
|
||||
|
||||
clk_disable(mipi->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_mipi_power_down(struct tegra_mipi *mipi)
|
||||
{
|
||||
u32 value;
|
||||
int err;
|
||||
|
||||
err = clk_enable(mipi->clk);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
/*
|
||||
* The MIPI_CAL_BIAS_PAD_PDVREG controls a voltage regulator that
|
||||
* supplies the DSI pads. This must be kept enabled until none of the
|
||||
* DSI lanes are used anymore.
|
||||
*/
|
||||
value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG2);
|
||||
value |= MIPI_CAL_BIAS_PAD_PDVREG;
|
||||
tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
|
||||
|
||||
/*
|
||||
* MIPI_CAL_BIAS_PAD_PDVCLAMP and MIPI_CAL_BIAS_PAD_E_VCLAMP_REF
|
||||
* control a regulator that supplies current to the pre-driver logic.
|
||||
* Powering down this regulator causes DSI to fail, so it must remain
|
||||
* powered on until none of the DSI lanes are used anymore.
|
||||
*/
|
||||
value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG0);
|
||||
|
||||
if (mipi->soc->needs_vclamp_ref)
|
||||
value &= ~MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
|
||||
|
||||
value |= MIPI_CAL_BIAS_PAD_PDVCLAMP;
|
||||
tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct tegra_mipi_device *tegra_mipi_request(struct device *device)
|
||||
{
|
||||
struct device_node *np = device->of_node;
|
||||
|
|
@ -150,6 +242,20 @@ struct tegra_mipi_device *tegra_mipi_request(struct device *device)
|
|||
dev->pads = args.args[0];
|
||||
dev->device = device;
|
||||
|
||||
mutex_lock(&dev->mipi->lock);
|
||||
|
||||
if (dev->mipi->usage_count++ == 0) {
|
||||
err = tegra_mipi_power_up(dev->mipi);
|
||||
if (err < 0) {
|
||||
dev_err(dev->mipi->dev,
|
||||
"failed to power up MIPI bricks: %d\n",
|
||||
err);
|
||||
return ERR_PTR(err);
|
||||
}
|
||||
}
|
||||
|
||||
mutex_unlock(&dev->mipi->lock);
|
||||
|
||||
return dev;
|
||||
|
||||
put:
|
||||
|
|
@ -164,6 +270,25 @@ EXPORT_SYMBOL(tegra_mipi_request);
|
|||
|
||||
void tegra_mipi_free(struct tegra_mipi_device *device)
|
||||
{
|
||||
int err;
|
||||
|
||||
mutex_lock(&device->mipi->lock);
|
||||
|
||||
if (--device->mipi->usage_count == 0) {
|
||||
err = tegra_mipi_power_down(device->mipi);
|
||||
if (err < 0) {
|
||||
/*
|
||||
* Not much that can be done here, so an error message
|
||||
* will have to do.
|
||||
*/
|
||||
dev_err(device->mipi->dev,
|
||||
"failed to power down MIPI bricks: %d\n",
|
||||
err);
|
||||
}
|
||||
}
|
||||
|
||||
mutex_unlock(&device->mipi->lock);
|
||||
|
||||
platform_device_put(device->pdev);
|
||||
kfree(device);
|
||||
}
|
||||
|
|
@ -199,16 +324,15 @@ int tegra_mipi_calibrate(struct tegra_mipi_device *device)
|
|||
|
||||
mutex_lock(&device->mipi->lock);
|
||||
|
||||
value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG0);
|
||||
value &= ~MIPI_CAL_BIAS_PAD_PDVCLAMP;
|
||||
value |= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
|
||||
tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
|
||||
|
||||
tegra_mipi_writel(device->mipi, MIPI_CAL_BIAS_PAD_DRV_DN_REF(2),
|
||||
MIPI_CAL_BIAS_PAD_CFG1);
|
||||
value = MIPI_CAL_BIAS_PAD_DRV_DN_REF(soc->pad_drive_down_ref) |
|
||||
MIPI_CAL_BIAS_PAD_DRV_UP_REF(soc->pad_drive_up_ref);
|
||||
tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG1);
|
||||
|
||||
value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2);
|
||||
value &= ~MIPI_CAL_BIAS_PAD_PDVREG;
|
||||
value &= ~MIPI_CAL_BIAS_PAD_VCLAMP(0x7);
|
||||
value &= ~MIPI_CAL_BIAS_PAD_VAUXP(0x7);
|
||||
value |= MIPI_CAL_BIAS_PAD_VCLAMP(soc->pad_vclamp_level);
|
||||
value |= MIPI_CAL_BIAS_PAD_VAUXP(soc->pad_vauxp_level);
|
||||
tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
|
||||
|
||||
for (i = 0; i < soc->num_pads; i++) {
|
||||
|
|
@ -216,20 +340,37 @@ int tegra_mipi_calibrate(struct tegra_mipi_device *device)
|
|||
|
||||
if (device->pads & BIT(i)) {
|
||||
data = MIPI_CAL_CONFIG_SELECT |
|
||||
MIPI_CAL_CONFIG_HSPDOS(0) |
|
||||
MIPI_CAL_CONFIG_HSPUOS(4) |
|
||||
MIPI_CAL_CONFIG_TERMOS(5);
|
||||
MIPI_CAL_CONFIG_HSPDOS(soc->hspdos) |
|
||||
MIPI_CAL_CONFIG_HSPUOS(soc->hspuos) |
|
||||
MIPI_CAL_CONFIG_TERMOS(soc->termos);
|
||||
clk = MIPI_CAL_CONFIG_SELECT |
|
||||
MIPI_CAL_CONFIG_HSCLKPDOSD(0) |
|
||||
MIPI_CAL_CONFIG_HSCLKPUOSD(4);
|
||||
MIPI_CAL_CONFIG_HSCLKPDOSD(soc->hsclkpdos) |
|
||||
MIPI_CAL_CONFIG_HSCLKPUOSD(soc->hsclkpuos);
|
||||
}
|
||||
|
||||
tegra_mipi_writel(device->mipi, data, soc->pads[i].data);
|
||||
|
||||
if (soc->has_clk_lane)
|
||||
if (soc->has_clk_lane && soc->pads[i].clk != 0)
|
||||
tegra_mipi_writel(device->mipi, clk, soc->pads[i].clk);
|
||||
}
|
||||
|
||||
value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
|
||||
value &= ~MIPI_CAL_CTRL_NOISE_FILTER(0xf);
|
||||
value &= ~MIPI_CAL_CTRL_PRESCALE(0x3);
|
||||
value |= MIPI_CAL_CTRL_NOISE_FILTER(0xa);
|
||||
value |= MIPI_CAL_CTRL_PRESCALE(0x2);
|
||||
|
||||
if (!soc->clock_enable_override)
|
||||
value &= ~MIPI_CAL_CTRL_CLKEN_OVR;
|
||||
else
|
||||
value |= MIPI_CAL_CTRL_CLKEN_OVR;
|
||||
|
||||
tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
|
||||
|
||||
/* clear any pending status bits */
|
||||
value = tegra_mipi_readl(device->mipi, MIPI_CAL_STATUS);
|
||||
tegra_mipi_writel(device->mipi, value, MIPI_CAL_STATUS);
|
||||
|
||||
value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
|
||||
value |= MIPI_CAL_CTRL_START;
|
||||
tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
|
||||
|
|
@ -259,6 +400,17 @@ static const struct tegra_mipi_soc tegra114_mipi_soc = {
|
|||
.has_clk_lane = false,
|
||||
.pads = tegra114_mipi_pads,
|
||||
.num_pads = ARRAY_SIZE(tegra114_mipi_pads),
|
||||
.clock_enable_override = true,
|
||||
.needs_vclamp_ref = true,
|
||||
.pad_drive_down_ref = 0x2,
|
||||
.pad_drive_up_ref = 0x0,
|
||||
.pad_vclamp_level = 0x0,
|
||||
.pad_vauxp_level = 0x0,
|
||||
.hspdos = 0x0,
|
||||
.hspuos = 0x4,
|
||||
.termos = 0x5,
|
||||
.hsclkpdos = 0x0,
|
||||
.hsclkpuos = 0x4,
|
||||
};
|
||||
|
||||
static const struct tegra_mipi_pad tegra124_mipi_pads[] = {
|
||||
|
|
@ -266,20 +418,80 @@ static const struct tegra_mipi_pad tegra124_mipi_pads[] = {
|
|||
{ .data = MIPI_CAL_CONFIG_CSIB, .clk = MIPI_CAL_CONFIG_CSIAB_CLK },
|
||||
{ .data = MIPI_CAL_CONFIG_CSIC, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
|
||||
{ .data = MIPI_CAL_CONFIG_CSID, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
|
||||
{ .data = MIPI_CAL_CONFIG_CSIE, .clk = MIPI_CAL_CONFIG_CSIE_CLK },
|
||||
{ .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIAB_CLK },
|
||||
{ .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIAB_CLK },
|
||||
{ .data = MIPI_CAL_CONFIG_CSIE, .clk = MIPI_CAL_CONFIG_CSIE_CLK },
|
||||
{ .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIA_CLK },
|
||||
{ .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIB_CLK },
|
||||
};
|
||||
|
||||
static const struct tegra_mipi_soc tegra124_mipi_soc = {
|
||||
.has_clk_lane = true,
|
||||
.pads = tegra124_mipi_pads,
|
||||
.num_pads = ARRAY_SIZE(tegra124_mipi_pads),
|
||||
.clock_enable_override = true,
|
||||
.needs_vclamp_ref = true,
|
||||
.pad_drive_down_ref = 0x2,
|
||||
.pad_drive_up_ref = 0x0,
|
||||
.pad_vclamp_level = 0x0,
|
||||
.pad_vauxp_level = 0x0,
|
||||
.hspdos = 0x0,
|
||||
.hspuos = 0x0,
|
||||
.termos = 0x0,
|
||||
.hsclkpdos = 0x1,
|
||||
.hsclkpuos = 0x2,
|
||||
};
|
||||
|
||||
static struct of_device_id tegra_mipi_of_match[] = {
|
||||
static const struct tegra_mipi_soc tegra132_mipi_soc = {
|
||||
.has_clk_lane = true,
|
||||
.pads = tegra124_mipi_pads,
|
||||
.num_pads = ARRAY_SIZE(tegra124_mipi_pads),
|
||||
.clock_enable_override = false,
|
||||
.needs_vclamp_ref = false,
|
||||
.pad_drive_down_ref = 0x0,
|
||||
.pad_drive_up_ref = 0x3,
|
||||
.pad_vclamp_level = 0x0,
|
||||
.pad_vauxp_level = 0x0,
|
||||
.hspdos = 0x0,
|
||||
.hspuos = 0x0,
|
||||
.termos = 0x0,
|
||||
.hsclkpdos = 0x3,
|
||||
.hsclkpuos = 0x2,
|
||||
};
|
||||
|
||||
static const struct tegra_mipi_pad tegra210_mipi_pads[] = {
|
||||
{ .data = MIPI_CAL_CONFIG_CSIA, .clk = 0 },
|
||||
{ .data = MIPI_CAL_CONFIG_CSIB, .clk = 0 },
|
||||
{ .data = MIPI_CAL_CONFIG_CSIC, .clk = 0 },
|
||||
{ .data = MIPI_CAL_CONFIG_CSID, .clk = 0 },
|
||||
{ .data = MIPI_CAL_CONFIG_CSIE, .clk = 0 },
|
||||
{ .data = MIPI_CAL_CONFIG_CSIF, .clk = 0 },
|
||||
{ .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIA_CLK },
|
||||
{ .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIB_CLK },
|
||||
{ .data = MIPI_CAL_CONFIG_DSIC, .clk = MIPI_CAL_CONFIG_DSIC_CLK },
|
||||
{ .data = MIPI_CAL_CONFIG_DSID, .clk = MIPI_CAL_CONFIG_DSID_CLK },
|
||||
};
|
||||
|
||||
static const struct tegra_mipi_soc tegra210_mipi_soc = {
|
||||
.has_clk_lane = true,
|
||||
.pads = tegra210_mipi_pads,
|
||||
.num_pads = ARRAY_SIZE(tegra210_mipi_pads),
|
||||
.clock_enable_override = true,
|
||||
.needs_vclamp_ref = false,
|
||||
.pad_drive_down_ref = 0x0,
|
||||
.pad_drive_up_ref = 0x3,
|
||||
.pad_vclamp_level = 0x1,
|
||||
.pad_vauxp_level = 0x1,
|
||||
.hspdos = 0x0,
|
||||
.hspuos = 0x2,
|
||||
.termos = 0x0,
|
||||
.hsclkpdos = 0x0,
|
||||
.hsclkpuos = 0x2,
|
||||
};
|
||||
|
||||
static const struct of_device_id tegra_mipi_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra114-mipi", .data = &tegra114_mipi_soc },
|
||||
{ .compatible = "nvidia,tegra124-mipi", .data = &tegra124_mipi_soc },
|
||||
{ .compatible = "nvidia,tegra132-mipi", .data = &tegra132_mipi_soc },
|
||||
{ .compatible = "nvidia,tegra210-mipi", .data = &tegra210_mipi_soc },
|
||||
{ },
|
||||
};
|
||||
|
||||
|
|
@ -299,6 +511,7 @@ static int tegra_mipi_probe(struct platform_device *pdev)
|
|||
return -ENOMEM;
|
||||
|
||||
mipi->soc = match->data;
|
||||
mipi->dev = &pdev->dev;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
mipi->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
|
|
|
|||
Loading…
Reference in New Issue