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Devicetree updates for v5.7: 

- Unit test for overlays with GPIO hogs
 
 - Improve dma-ranges parsing to handle dma-ranges with multiple entries
 
 - Update dtc to upstream version v1.6.0-2-g87a656ae5ff9
 
 - Improve overlay error reporting
 
 - Device link support for power-domains and hwlocks bindings
 
 - Add vendor prefixes for Beacon, Topwise, ENE, Dell, SG Micro, Elida,
   PocketBook, Xiaomi, Linutronix, OzzMaker, Waveshare Electronics, and
   ITE Tech
 
 - Add deprecated Marvell vendor prefix 'mrvl'
 
 - A bunch of binding conversions to DT schema continues. Of note, the
   common serial and USB connector bindings are converted.
 
 - Add more Arm CPU compatibles
 
 - Drop Mark Rutland as DT maintainer :(
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Merge tag 'devicetree-for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree updates from Rob Herring:

 - Unit test for overlays with GPIO hogs

 - Improve dma-ranges parsing to handle dma-ranges with multiple entries

 - Update dtc to upstream version v1.6.0-2-g87a656ae5ff9

 - Improve overlay error reporting

 - Device link support for power-domains and hwlocks bindings

 - Add vendor prefixes for Beacon, Topwise, ENE, Dell, SG Micro, Elida,
   PocketBook, Xiaomi, Linutronix, OzzMaker, Waveshare Electronics, and
   ITE Tech

 - Add deprecated Marvell vendor prefix 'mrvl'

 - A bunch of binding conversions to DT schema continues. Of note, the
   common serial and USB connector bindings are converted.

 - Add more Arm CPU compatibles

 - Drop Mark Rutland as DT maintainer :(

* tag 'devicetree-for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (106 commits)
  MAINTAINERS: drop an old reference to stm32 pwm timers doc
  MAINTAINERS: dt: update etnaviv file reference
  dt-bindings: usb: dwc2: fix bindings for amlogic, meson-gxbb-usb
  dt-bindings: uniphier-system-bus: fix warning in the example
  dt-bindings: display: meson-vpu: fix indentation of reg-names' "items"
  dt-bindings: iio: Fix adi, ltc2983 uint64-matrix schema constraints
  dt-bindings: power: Fix example for power-domain
  dt-bindings: arm: Add some constraints for PSCI nodes
  of: some unittest overlays not untracked
  of: gpio unittest kfree() wrong object
  dt-bindings: phy: convert phy-rockchip-inno-usb2 bindings to yaml
  dt-bindings: serial: sh-sci: Convert to json-schema
  dt-bindings: serial: Document serialN aliases
  dt-bindings: thermal: tsens: Set 'additionalProperties: false'
  dt-bindings: thermal: tsens: Fix nvmem-cell-names schema
  dt-bindings: vendor-prefixes: Add Beacon vendor prefix
  dt-bindings: vendor-prefixes: Add Topwise
  of: of_private.h: Replace zero-length array with flexible-array member
  docs: dt: fix a broken reference to input.yaml
  docs: dt: fix references to ap806-system-controller.txt
  ...
This commit is contained in:
Linus Torvalds 2020-04-02 17:32:52 -07:00
parent 79f51b7b9c 8967918e7c
commit bef7b2a7be
258 changed files with 5753 additions and 2663 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml
View File

@ -21,6 +21,8 @@ properties:
required:
- compatible
additionalProperties: false
examples:
- |
clkmgr@ffd04000 {

2
Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
View File

@ -43,6 +43,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
ao-secure@140 {

11
Documentation/devicetree/bindings/arm/cpus.yaml
View File

@ -123,11 +123,18 @@ properties:
- arm,cortex-a12
- arm,cortex-a15
- arm,cortex-a17
- arm,cortex-a32
- arm,cortex-a34
- arm,cortex-a35
- arm,cortex-a53
- arm,cortex-a55
- arm,cortex-a57
- arm,cortex-a65
- arm,cortex-a72
- arm,cortex-a73
- arm,cortex-a75
- arm,cortex-a76
- arm,cortex-a77
- arm,cortex-m0
- arm,cortex-m0+
- arm,cortex-m1
@ -136,6 +143,8 @@ properties:
- arm,cortex-r4
- arm,cortex-r5
- arm,cortex-r7
- arm,neoverse-e1
- arm,neoverse-n1
- brcm,brahma-b15
- brcm,brahma-b53
- brcm,vulcan
@ -155,6 +164,8 @@ properties:
- nvidia,tegra194-carmel
- qcom,krait
- qcom,kryo
- qcom,kryo260
- qcom,kryo280
- qcom,kryo385
- qcom,kryo485
- qcom,scorpion

2
Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
View File

@ -164,7 +164,7 @@ Required properties:
- compatible: should be:
"fsl,imx8qxp-sc-key"
followed by "fsl,imx-sc-key";
- linux,keycodes: See Documentation/devicetree/bindings/input/keys.txt
- linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml
Example (imx8qxp):
-------------

45
Documentation/devicetree/bindings/arm/l2c2x0.yaml
View File

@ -29,27 +29,30 @@ allOf:
properties:
compatible:
enum:
- arm,pl310-cache
- arm,l220-cache
- arm,l210-cache
# DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
- bcm,bcm11351-a2-pl310-cache
# For Broadcom bcm11351 chipset where an
# offset needs to be added to the address before passing down to the L2
# cache controller
- brcm,bcm11351-a2-pl310-cache
# Marvell Controller designed to be
# compatible with the ARM one, with system cache mode (meaning
# maintenance operations on L1 are broadcasted to the L2 and L2
# performs the same operation).
- marvell,aurora-system-cache
# Marvell Controller designed to be
# compatible with the ARM one with outer cache mode.
- marvell,aurora-outer-cache
# Marvell Tauros3 cache controller, compatible
# with arm,pl310-cache controller.
- marvell,tauros3-cache
oneOf:
- enum:
- arm,pl310-cache
- arm,l220-cache
- arm,l210-cache
# DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
- bcm,bcm11351-a2-pl310-cache
# For Broadcom bcm11351 chipset where an
# offset needs to be added to the address before passing down to the L2
# cache controller
- brcm,bcm11351-a2-pl310-cache
# Marvell Controller designed to be
# compatible with the ARM one, with system cache mode (meaning
# maintenance operations on L1 are broadcasted to the L2 and L2
# performs the same operation).
- marvell,aurora-system-cache
# Marvell Controller designed to be
# compatible with the ARM one with outer cache mode.
- marvell,aurora-outer-cache
- items:
# Marvell Tauros3 cache controller, compatible
# with arm,pl310-cache controller.
- const: marvell,tauros3-cache
- const: arm,pl310-cache
cache-level:
const: 2

5
Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
View File

@ -28,8 +28,11 @@ properties:
items:
- enum:
- mrvl,mmp2-brownstone
- olpc,xo-1.75
- const: mrvl,mmp2
- description: MMP3 based boards
items:
- const: mrvl,mmp3
- enum:
- dell,wyse-ariel
- const: marvell,mmp3
...

2
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
View File

@ -43,6 +43,8 @@ required:
- reg-names
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>

41
Documentation/devicetree/bindings/arm/pmu.yaml
View File

@ -20,27 +20,36 @@ properties:
items:
- enum:
- apm,potenza-pmu
- arm,armv8-pmuv3
- arm,cortex-a73-pmu
- arm,cortex-a72-pmu
- arm,cortex-a57-pmu
- arm,cortex-a53-pmu
- arm,cortex-a35-pmu
- arm,cortex-a17-pmu
- arm,cortex-a15-pmu
- arm,cortex-a12-pmu
- arm,cortex-a9-pmu
- arm,cortex-a8-pmu
- arm,cortex-a7-pmu
- arm,cortex-a5-pmu
- arm,arm11mpcore-pmu
- arm,arm1176-pmu
- arm,armv8-pmuv3 # Only for s/w models
- arm,arm1136-pmu
- arm,arm1176-pmu
- arm,arm11mpcore-pmu
- arm,cortex-a5-pmu
- arm,cortex-a7-pmu
- arm,cortex-a8-pmu
- arm,cortex-a9-pmu
- arm,cortex-a12-pmu
- arm,cortex-a15-pmu
- arm,cortex-a17-pmu
- arm,cortex-a32-pmu
- arm,cortex-a34-pmu
- arm,cortex-a35-pmu
- arm,cortex-a53-pmu
- arm,cortex-a55-pmu
- arm,cortex-a57-pmu
- arm,cortex-a65-pmu
- arm,cortex-a72-pmu
- arm,cortex-a73-pmu
- arm,cortex-a75-pmu
- arm,cortex-a76-pmu
- arm,cortex-a77-pmu
- arm,neoverse-e1-pmu
- arm,neoverse-n1-pmu
- brcm,vulcan-pmu
- cavium,thunder-pmu
- qcom,krait-pmu
- qcom,scorpion-pmu
- qcom,scorpion-mp-pmu
- qcom,krait-pmu
interrupts:
# Don't know how many CPUs, so no constraints to specify

5
Documentation/devicetree/bindings/arm/psci.yaml
View File

@ -32,6 +32,9 @@ description: |+
http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
properties:
$nodename:
const: psci
compatible:
oneOf:
- description:
@ -141,6 +144,8 @@ allOf:
- cpu_off
- cpu_on
additionalProperties: false
examples:
- |+

2
Documentation/devicetree/bindings/arm/renesas,prr.yaml
View File

@ -27,6 +27,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
prr: chipid@ff000044 {

2
Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml
View File

@ -30,6 +30,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
chipid@10000000 {

2
Documentation/devicetree/bindings/arm/samsung/pmu.yaml
View File

@ -89,6 +89,8 @@ required:
- clock-names
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5250.h>

2
Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml
View File

@ -23,6 +23,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
firmware@203f000 {

60
Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt
View File

@ -1,60 +0,0 @@
UniPhier outer cache controller
UniPhier SoCs are integrated with a full-custom outer cache controller system.
All of them have a level 2 cache controller, and some have a level 3 cache
controller as well.
Required properties:
- compatible: should be "socionext,uniphier-system-cache"
- reg: offsets and lengths of the register sets for the device. It should
contain 3 regions: control register, revision register, operation register,
in this order.
- cache-unified: specifies the cache is a unified cache.
- cache-size: specifies the size in bytes of the cache
- cache-sets: specifies the number of associativity sets of the cache
- cache-line-size: specifies the line size in bytes
- cache-level: specifies the level in the cache hierarchy. The value should
be 2 for L2 cache, 3 for L3 cache, etc.
Optional properties:
- next-level-cache: phandle to the next level cache if present. The next level
cache should be also compatible with "socionext,uniphier-system-cache".
The L2 cache must exist to use the L3 cache; the cache hierarchy must be
indicated correctly with "next-level-cache" properties.
Example 1 (system with L2):
l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
cache-unified;
cache-size = <0x80000>;
cache-sets = <256>;
cache-line-size = <128>;
cache-level = <2>;
};
Example 2 (system with L2 and L3):
l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
cache-unified;
cache-size = <0x200000>;
cache-sets = <512>;
cache-line-size = <128>;
cache-level = <2>;
next-level-cache = <&l3>;
};
l3: l3-cache@500c8000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
<0x506c8000 0x400>;
cache-unified;
cache-size = <0x400000>;
cache-sets = <512>;
cache-line-size = <256>;
cache-level = <3>;
};

102
Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml Normal file
View File

@ -0,0 +1,102 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UniPhier outer cache controller
description: |
UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
controller system. All of them have a level 2 cache controller, and some
have a level 3 cache controller as well.
maintainers:
- Masahiro Yamada <yamada.masahiro@socionext.com>
properties:
compatible:
const: socionext,uniphier-system-cache
reg:
description: |
should contain 3 regions: control register, revision register,
operation register, in this order.
minItems: 3
maxItems: 3
interrupts:
description: |
Interrupts can be used to notify the completion of cache operations.
The number of interrupts should match to the number of CPU cores.
The specified interrupts correspond to CPU0, CPU1, ... in this order.
minItems: 1
maxItems: 4
cache-unified: true
cache-size: true
cache-sets: true
cache-line-size: true
cache-level:
minimum: 2
maximum: 3
next-level-cache: true
allOf:
- $ref: /schemas/cache-controller.yaml#
additionalProperties: false
required:
- compatible
- reg
- interrupts
- cache-unified
- cache-size
- cache-sets
- cache-line-size
- cache-level
examples:
- |
// System with L2.
cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
cache-unified;
cache-size = <0x140000>;
cache-sets = <512>;
cache-line-size = <128>;
cache-level = <2>;
};
- |
// System with L2 and L3.
// L2 should specify the next level cache by 'next-level-cache'.
l2: cache-controller@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
interrupts = <0 190 4>, <0 191 4>;
cache-unified;
cache-size = <0x200000>;
cache-sets = <512>;
cache-line-size = <128>;
cache-level = <2>;
next-level-cache = <&l3>;
};
l3: cache-controller@500c8000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
interrupts = <0 174 4>, <0 175 4>;
cache-unified;
cache-size = <0x200000>;
cache-sets = <512>;
cache-line-size = <256>;
cache-level = <3>;
};

47
Documentation/devicetree/bindings/arm/socionext/uniphier.txt
View File

@ -1,47 +0,0 @@
Socionext UniPhier SoC family
-----------------------------
Required properties in the root node:
- compatible: should contain board and SoC compatible strings
SoC and board compatible strings:
(sorted chronologically)
- LD4 SoC: "socionext,uniphier-ld4"
- Reference Board: "socionext,uniphier-ld4-ref"
- Pro4 SoC: "socionext,uniphier-pro4"
- Reference Board: "socionext,uniphier-pro4-ref"
- Ace Board: "socionext,uniphier-pro4-ace"
- Sanji Board: "socionext,uniphier-pro4-sanji"
- sLD8 SoC: "socionext,uniphier-sld8"
- Reference Board: "socionext,uniphier-sld8-ref"
- PXs2 SoC: "socionext,uniphier-pxs2"
- Gentil Board: "socionext,uniphier-pxs2-gentil"
- Vodka Board: "socionext,uniphier-pxs2-vodka"
- LD6b SoC: "socionext,uniphier-ld6b"
- Reference Board: "socionext,uniphier-ld6b-ref"
- LD11 SoC: "socionext,uniphier-ld11"
- Reference Board: "socionext,uniphier-ld11-ref"
- Global Board: "socionext,uniphier-ld11-global"
- LD20 SoC: "socionext,uniphier-ld20"
- Reference Board: "socionext,uniphier-ld20-ref"
- Global Board: "socionext,uniphier-ld20-global"
- PXs3 SoC: "socionext,uniphier-pxs3"
- Reference Board: "socionext,uniphier-pxs3-ref"
Example:
/dts-v1/;
/ {
compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
...
};

61
Documentation/devicetree/bindings/arm/socionext/uniphier.yaml Normal file
View File

@ -0,0 +1,61 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/socionext/uniphier.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext UniPhier platform device tree bindings
maintainers:
- Masahiro Yamada <yamada.masahiro@socionext.com>
properties:
$nodename:
const: /
compatible:
oneOf:
- description: LD4 SoC boards
items:
- enum:
- socionext,uniphier-ld4-ref
- const: socionext,uniphier-ld4
- description: Pro4 SoC boards
items:
- enum:
- socionext,uniphier-pro4-ace
- socionext,uniphier-pro4-ref
- socionext,uniphier-pro4-sanji
- const: socionext,uniphier-pro4
- description: sLD8 SoC boards
items:
- enum:
- socionext,uniphier-sld8-ref
- const: socionext,uniphier-sld8
- description: PXs2 SoC boards
items:
- enum:
- socionext,uniphier-pxs2-gentil
- socionext,uniphier-pxs2-vodka
- const: socionext,uniphier-pxs2
- description: LD6b SoC boards
items:
- enum:
- socionext,uniphier-ld6b-ref
- const: socionext,uniphier-ld6b
- description: LD11 SoC boards
items:
- enum:
- socionext,uniphier-ld11-global
- socionext,uniphier-ld11-ref
- const: socionext,uniphier-ld11
- description: LD20 SoC boards
items:
- enum:
- socionext,uniphier-ld20-global
- socionext,uniphier-ld20-ref
- const: socionext,uniphier-ld20
- description: PXs3 SoC boards
items:
- enum:
- socionext,uniphier-pxs3-ref
- const: socionext,uniphier-pxs3

2
Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
View File

@ -29,6 +29,8 @@ required:
- reg
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/stm32mp1-clks.h>

71
Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml Normal file
View File

@ -0,0 +1,71 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/ata/renesas,rcar-sata.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Renesas R-Car Serial-ATA Interface
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
properties:
compatible:
oneOf:
- items:
- enum:
- renesas,sata-r8a7779 # R-Car H1
- items:
- enum:
- renesas,sata-r8a7790-es1 # R-Car H2 ES1
- renesas,sata-r8a7790 # R-Car H2 other than ES1
- renesas,sata-r8a7791 # R-Car M2-W
- renesas,sata-r8a7793 # R-Car M2-N
- const: renesas,rcar-gen2-sata # generic R-Car Gen2
- items:
- enum:
- renesas,sata-r8a774b1 # RZ/G2N
- renesas,sata-r8a7795 # R-Car H3
- renesas,sata-r8a77965 # R-Car M3-N
- const: renesas,rcar-gen3-sata # generic R-Car Gen3 or RZ/G2
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
iommus:
maxItems: 1
power-domains:
maxItems: 1
resets:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7791-sysc.h>
sata@ee300000 {
compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
reg = <0xee300000 0x200000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 815>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 815>;
};

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@ -1,36 +0,0 @@
* Renesas R-Car SATA
Required properties:
- compatible : should contain one or more of the following:
- "renesas,sata-r8a774b1" for RZ/G2N
- "renesas,sata-r8a7779" for R-Car H1
- "renesas,sata-r8a7790-es1" for R-Car H2 ES1
- "renesas,sata-r8a7790" for R-Car H2 other than ES1
- "renesas,sata-r8a7791" for R-Car M2-W
- "renesas,sata-r8a7793" for R-Car M2-N
- "renesas,sata-r8a7795" for R-Car H3
- "renesas,sata-r8a77965" for R-Car M3-N
- "renesas,rcar-gen2-sata" for a generic R-Car Gen2
compatible device
- "renesas,rcar-gen3-sata" for a generic R-Car Gen3 or
RZ/G2 compatible device
- "renesas,rcar-sata" is deprecated
When compatible with the generic version nodes
must list the SoC-specific version corresponding
to the platform first followed by the generic
version.
- reg : address and length of the SATA registers;
- interrupts : must consist of one interrupt specifier.
- clocks : must contain a reference to the functional clock.
Example:
sata0: sata@ee300000 {
compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
reg = <0 0xee300000 0 0x2000>;
interrupt-parent = <&gic>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
};

96
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@ -0,0 +1,96 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UniPhier System Bus
description: |
The UniPhier System Bus is an external bus that connects on-board devices to
the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
some control signals. It supports up to 8 banks (chip selects).
Before any access to the bus, the bus controller must be configured; the bus
controller registers provide the control for the translation from the offset
within each bank to the CPU-viewed address. The needed setup includes the
base address, the size of each bank. Optionally, some timing parameters can
be optimized for faster bus access.
maintainers:
- Masahiro Yamada <yamada.masahiro@socionext.com>
properties:
compatible:
const: socionext,uniphier-system-bus
reg:
maxItems: 1
"#address-cells":
description: |
The first cell is the bank number (chip select).
The second cell is the address offset within the bank.
const: 2
"#size-cells":
const: 1
ranges:
description: |
Provide address translation from the System Bus to the parent bus.
Note:
The address region(s) that can be assigned for the System Bus is
implementation defined. Some SoCs can use 0x00000000-0x0fffffff and
0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.
There might be additional limitations depending on SoCs and the boot mode.
The address translation is arbitrary as long as the banks are assigned in
the supported address space with the required alignment and they do not
overlap one another.
For example, it is possible to map:
bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
It is also possible to map:
bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
There is no reason to stick to a particular translation mapping, but the
"ranges" property should provide a "reasonable" default that is known to
work. The software should initialize the bus controller according to it.
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- ranges
examples:
- |
// In this example,
// - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
// mapped to 0x43f00000 of the parent bus.
// - the UART device is connected at the offset 0x00200000 of CS5 and
// mapped to 0x46200000 of the parent bus.
system-bus@58c00000 {
compatible = "socionext,uniphier-system-bus";
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <1 0x00000000 0x42000000 0x02000000>,
<5 0x00000000 0x46000000 0x01000000>;
ethernet@1,01f00000 {
compatible = "smsc,lan9115";
reg = <1 0x01f00000 0x1000>;
interrupts = <0 48 4>;
phy-mode = "mii";
};
uart@5,00200000 {
compatible = "ns16550a";
reg = <5 0x00200000 0x20>;
interrupts = <0 49 4>;
clock-frequency = <12288000>;
};
};

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@ -1,66 +0,0 @@
UniPhier System Bus
The UniPhier System Bus is an external bus that connects on-board devices to
the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
some control signals. It supports up to 8 banks (chip selects).
Before any access to the bus, the bus controller must be configured; the bus
controller registers provide the control for the translation from the offset
within each bank to the CPU-viewed address. The needed setup includes the base
address, the size of each bank. Optionally, some timing parameters can be
optimized for faster bus access.
Required properties:
- compatible: should be "socionext,uniphier-system-bus".
- reg: offset and length of the register set for the bus controller device.
- #address-cells: should be 2. The first cell is the bank number (chip select).
The second cell is the address offset within the bank.
- #size-cells: should be 1.
- ranges: should provide a proper address translation from the System Bus to
the parent bus.
Note:
The address region(s) that can be assigned for the System Bus is implementation
defined. Some SoCs can use 0x00000000-0x0fffffff and 0x40000000-0x4fffffff,
while other SoCs can only use 0x40000000-0x4fffffff. There might be additional
limitations depending on SoCs and the boot mode. The address translation is
arbitrary as long as the banks are assigned in the supported address space with
the required alignment and they do not overlap one another.
For example, it is possible to map:
bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
It is also possible to map:
bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
There is no reason to stick to a particular translation mapping, but the
"ranges" property should provide a "reasonable" default that is known to work.
The software should initialize the bus controller according to it.
Example:
system-bus {
compatible = "socionext,uniphier-system-bus";
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <1 0x00000000 0x42000000 0x02000000
5 0x00000000 0x46000000 0x01000000>;
ethernet@1,01f00000 {
compatible = "smsc,lan9115";
reg = <1 0x01f00000 0x1000>;
interrupts = <0 48 4>
phy-mode = "mii";
};
uart@5,00200000 {
compatible = "ns16550a";
reg = <5 0x00200000 0x20>;
interrupts = <0 49 4>
clock-frequency = <12288000>;
};
};
In this example,
- the Ethernet device is connected at the offset 0x01f00000 of CS1 and
mapped to 0x43f00000 of the parent bus.
- the UART device is connected at the offset 0x00200000 of CS5 and
mapped to 0x46200000 of the parent bus.

54
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@ -0,0 +1,54 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/chrome/google,cros-ec-typec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Google Chrome OS EC(Embedded Controller) Type C port driver.
maintainers:
- Benson Leung <bleung@chromium.org>
- Prashant Malani <pmalani@chromium.org>
description:
Chrome OS devices have an Embedded Controller(EC) which has access to
Type C port state. This node is intended to allow the host to read and
control the Type C ports. The node for this device should be under a
cros-ec node like google,cros-ec-spi.
properties:
compatible:
const: google,cros-ec-typec
connector:
$ref: /schemas/connector/usb-connector.yaml#
required:
- compatible
examples:
- |+
spi0 {
#address-cells = <1>;
#size-cells = <0>;
cros_ec: ec@0 {
compatible = "google,cros-ec-spi";
reg = <0>;
typec {
compatible = "google,cros-ec-typec";
#address-cells = <1>;
#size-cells = <0>;
connector@0 {
compatible = "usb-c-connector";
reg = <0>;
power-role = "dual";
data-role = "dual";
try-power-role = "source";
};
};
};
};

2
Documentation/devicetree/bindings/clock/clock-bindings.txt
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@ -94,7 +94,7 @@ clock is connected to output 0 of the &ref.
/* external oscillator */
osc: oscillator {
compatible = "fixed-clock";
#clock-cells = <1>;
#clock-cells = <0>;
clock-frequency = <32678>;
clock-output-names = "osc";
};

5
Documentation/devicetree/bindings/clock/fsl,plldig.yaml
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@ -21,6 +21,9 @@ properties:
reg:
maxItems: 1
clocks:
maxItems: 1
'#clock-cells':
const: 0
@ -41,6 +44,8 @@ required:
- clocks
- '#clock-cells'
additionalProperties: false
examples:
# Display PIXEL Clock node:
- |

2
Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
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@ -52,6 +52,8 @@ required:
- clock-names
- '#clock-cells'
additionalProperties: false
examples:
# Clock Control Module node:
- |

2
Documentation/devicetree/bindings/clock/imx8mp-clock.yaml
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@ -52,6 +52,8 @@ required:
- clock-names
- '#clock-cells'
additionalProperties: false
examples:
# Clock Control Module node:
- |

2
Documentation/devicetree/bindings/clock/milbeaut-clock.yaml
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@ -35,6 +35,8 @@ required:
- clocks
- '#clock-cells'
additionalProperties: false
examples:
# Clock controller node:
- |

2
Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
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@ -68,6 +68,8 @@ required:
- nvmem-cell-names
- '#thermal-sensor-cells'
additionalProperties: false
examples:
- |
clock-controller@900000 {

2
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
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@ -40,6 +40,8 @@ required:
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
clock-controller@1800000 {

2
Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
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@ -56,6 +56,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
clock-controller@300000 {

2
Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml
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@ -66,6 +66,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>

2
Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml
View File

@ -40,6 +40,8 @@ required:
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
clock-controller@1800000 {

2
Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
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@ -58,6 +58,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>

2
Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
View File

@ -56,6 +56,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>

2
Documentation/devicetree/bindings/clock/qcom,gcc.yaml
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@ -74,6 +74,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
# Example for GCC for MSM8960:
- |

2
Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
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@ -74,6 +74,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
if:
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml
View File

@ -50,6 +50,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8998.h>

2
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
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@ -35,6 +35,8 @@ required:
- compatible
- '#clock-cells'
additionalProperties: false
examples:
# Example for GCC for SDM845: The below node should be defined inside
# &apps_rsc node.

2
Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
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@ -58,6 +58,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc7180.h>

2
Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml
View File

@ -52,6 +52,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc7180.h>

2
Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml
View File

@ -48,6 +48,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>

2
Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml
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@ -67,6 +67,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sdm845.h>

2
Documentation/devicetree/bindings/clock/qcom,sdm845-gpucc.yaml
View File

@ -52,6 +52,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sdm845.h>

2
Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml
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@ -48,6 +48,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>

94
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@ -0,0 +1,94 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/socionext,uniphier-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UniPhier clock controller
maintainers:
- Masahiro Yamada <yamada.masahiro@socionext.com>
properties:
compatible:
oneOf:
- description: System clock
enum:
- socionext,uniphier-ld4-clock
- socionext,uniphier-pro4-clock
- socionext,uniphier-sld8-clock
- socionext,uniphier-pro5-clock
- socionext,uniphier-pxs2-clock
- socionext,uniphier-ld6b-clock
- socionext,uniphier-ld11-clock
- socionext,uniphier-ld20-clock
- socionext,uniphier-pxs3-clock
- description: Media I/O (MIO) clock, SD clock
enum:
- socionext,uniphier-ld4-mio-clock
- socionext,uniphier-pro4-mio-clock
- socionext,uniphier-sld8-mio-clock
- socionext,uniphier-pro5-sd-clock
- socionext,uniphier-pxs2-sd-clock
- socionext,uniphier-ld11-mio-clock
- socionext,uniphier-ld20-sd-clock
- socionext,uniphier-pxs3-sd-clock
- description: Peripheral clock
enum:
- socionext,uniphier-ld4-peri-clock
- socionext,uniphier-pro4-peri-clock
- socionext,uniphier-sld8-peri-clock
- socionext,uniphier-pro5-peri-clock
- socionext,uniphier-pxs2-peri-clock
- socionext,uniphier-ld11-peri-clock
- socionext,uniphier-ld20-peri-clock
- socionext,uniphier-pxs3-peri-clock
"#clock-cells":
const: 1
additionalProperties: false
required:
- compatible
- "#clock-cells"
examples:
- |
sysctrl@61840000 {
compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon";
reg = <0x61840000 0x4000>;
clock {
compatible = "socionext,uniphier-ld11-clock";
#clock-cells = <1>;
};
// other nodes ...
};
- |
mioctrl@59810000 {
compatible = "socionext,uniphier-mioctrl", "simple-mfd", "syscon";
reg = <0x59810000 0x800>;
clock {
compatible = "socionext,uniphier-ld11-mio-clock";
#clock-cells = <1>;
};
// other nodes ...
};
- |
perictrl@59820000 {
compatible = "socionext,uniphier-perictrl", "simple-mfd", "syscon";
reg = <0x59820000 0x200>;
clock {
compatible = "socionext,uniphier-ld11-peri-clock";
#clock-cells = <1>;
};
// other nodes ...
};

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@ -1,132 +0,0 @@
UniPhier clock controller
System clock
------------
Required properties:
- compatible: should be one of the following:
"socionext,uniphier-ld4-clock" - for LD4 SoC.
"socionext,uniphier-pro4-clock" - for Pro4 SoC.
"socionext,uniphier-sld8-clock" - for sLD8 SoC.
"socionext,uniphier-pro5-clock" - for Pro5 SoC.
"socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-clock" - for LD11 SoC.
"socionext,uniphier-ld20-clock" - for LD20 SoC.
"socionext,uniphier-pxs3-clock" - for PXs3 SoC
- #clock-cells: should be 1.
Example:
sysctrl@61840000 {
compatible = "socionext,uniphier-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x4000>;
clock {
compatible = "socionext,uniphier-ld11-clock";
#clock-cells = <1>;
};
other nodes ...
};
Provided clocks:
8: ST DMAC
12: GIO (Giga bit stream I/O)
14: USB3 ch0 host
15: USB3 ch1 host
16: USB3 ch0 PHY0
17: USB3 ch0 PHY1
20: USB3 ch1 PHY0
21: USB3 ch1 PHY1
Media I/O (MIO) clock, SD clock
-------------------------------
Required properties:
- compatible: should be one of the following:
"socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
"socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
"socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
"socionext,uniphier-pro5-sd-clock" - for Pro5 SoC.
"socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
"socionext,uniphier-ld20-sd-clock" - for LD20 SoC.
"socionext,uniphier-pxs3-sd-clock" - for PXs3 SoC
- #clock-cells: should be 1.
Example:
mioctrl@59810000 {
compatible = "socionext,uniphier-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
clock {
compatible = "socionext,uniphier-ld11-mio-clock";
#clock-cells = <1>;
};
other nodes ...
};
Provided clocks:
0: SD ch0 host
1: eMMC host
2: SD ch1 host
7: MIO DMAC
8: USB2 ch0 host
9: USB2 ch1 host
10: USB2 ch2 host
12: USB2 ch0 PHY
13: USB2 ch1 PHY
14: USB2 ch2 PHY
Peripheral clock
----------------
Required properties:
- compatible: should be one of the following:
"socionext,uniphier-ld4-peri-clock" - for LD4 SoC.
"socionext,uniphier-pro4-peri-clock" - for Pro4 SoC.
"socionext,uniphier-sld8-peri-clock" - for sLD8 SoC.
"socionext,uniphier-pro5-peri-clock" - for Pro5 SoC.
"socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-peri-clock" - for LD11 SoC.
"socionext,uniphier-ld20-peri-clock" - for LD20 SoC.
"socionext,uniphier-pxs3-peri-clock" - for PXs3 SoC
- #clock-cells: should be 1.
Example:
perictrl@59820000 {
compatible = "socionext,uniphier-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
clock {
compatible = "socionext,uniphier-ld11-peri-clock";
#clock-cells = <1>;
};
other nodes ...
};
Provided clocks:
0: UART ch0
1: UART ch1
2: UART ch2
3: UART ch3
4: I2C ch0
5: I2C ch1
6: I2C ch2
7: I2C ch3
8: I2C ch4
9: I2C ch5
10: I2C ch6

2
Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt
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@ -19,7 +19,7 @@ Required nodes:
0: High Speed (HS),
3: Mobile High-Definition Link (MHL), specific to 11-pin Samsung micro-USB.
[1]: bindings/connector/usb-connector.txt
[1]: bindings/connector/usb-connector.yaml
Example
-------

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@ -1,135 +0,0 @@
USB Connector
=============
A USB connector node represents a physical USB connector. It should be
a child of a USB interface controller.
Required properties:
- compatible: describes type of the connector, must be one of:
"usb-a-connector",
"usb-b-connector",
"usb-c-connector".
Optional properties:
- label: symbolic name for the connector,
- type: size of the connector, should be specified in case of USB-A, USB-B
non-fullsize connectors: "mini", "micro".
- self-powered: Set this property if the usb device that has its own power
source.
Optional properties for usb-b-connector:
- id-gpios: an input gpio for USB ID pin.
- vbus-gpios: an input gpio for USB VBUS pin, used to detect presence of
VBUS 5V.
see gpio/gpio.txt.
- vbus-supply: a phandle to the regulator for USB VBUS if needed when host
mode or dual role mode is supported.
Particularly, if use an output GPIO to control a VBUS regulator, should
model it as a regulator.
see regulator/fixed-regulator.yaml
- pinctrl-names : a pinctrl state named "default" is optional
- pinctrl-0 : pin control group
see pinctrl/pinctrl-bindings.txt
Optional properties for usb-c-connector:
- power-role: should be one of "source", "sink" or "dual"(DRP) if typec
connector has power support.
- try-power-role: preferred power role if "dual"(DRP) can support Try.SNK
or Try.SRC, should be "sink" for Try.SNK or "source" for Try.SRC.
- data-role: should be one of "host", "device", "dual"(DRD) if typec
connector supports USB data.
Required properties for usb-c-connector with power delivery support:
- source-pdos: An array of u32 with each entry providing supported power
source data object(PDO), the detailed bit definitions of PDO can be found
in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.2
Source_Capabilities Message, the order of each entry(PDO) should follow
the PD spec chapter 6.4.1. Required for power source and power dual role.
User can specify the source PDO array via PDO_FIXED/BATT/VAR/PPS_APDO()
defined in dt-bindings/usb/pd.h.
- sink-pdos: An array of u32 with each entry providing supported power
sink data object(PDO), the detailed bit definitions of PDO can be found
in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.3
Sink Capabilities Message, the order of each entry(PDO) should follow
the PD spec chapter 6.4.1. Required for power sink and power dual role.
User can specify the sink PDO array via PDO_FIXED/BATT/VAR/PPS_APDO() defined
in dt-bindings/usb/pd.h.
- op-sink-microwatt: Sink required operating power in microwatt, if source
can't offer the power, Capability Mismatch is set. Required for power
sink and power dual role.
Required nodes:
- any data bus to the connector should be modeled using the OF graph bindings
specified in bindings/graph.txt, unless the bus is between parent node and
the connector. Since single connector can have multiple data buses every bus
has assigned OF graph port number as follows:
0: High Speed (HS), present in all connectors,
1: Super Speed (SS), present in SS capable connectors,
2: Sideband use (SBU), present in USB-C.
Examples
--------
1. Micro-USB connector with HS lines routed via controller (MUIC):
muic-max77843@66 {
...
usb_con: connector {
compatible = "usb-b-connector";
label = "micro-USB";
type = "micro";
};
};
2. USB-C connector attached to CC controller (s2mm005), HS lines routed
to companion PMIC (max77865), SS lines to USB3 PHY and SBU to DisplayPort.
DisplayPort video lines are routed to the connector via SS mux in USB3 PHY.
ccic: s2mm005@33 {
...
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_con_hs: endpoint {
remote-endpoint = <&max77865_usbc_hs>;
};
};
port@1 {
reg = <1>;
usb_con_ss: endpoint {
remote-endpoint = <&usbdrd_phy_ss>;
};
};
port@2 {
reg = <2>;
usb_con_sbu: endpoint {
remote-endpoint = <&dp_aux>;
};
};
};
};
};
3. USB-C connector attached to a typec port controller(ptn5110), which has
power delivery support and enables drp.
typec: ptn5110@50 {
...
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 12000, 2000)>;
op-sink-microwatt = <10000000>;
};
};

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@ -0,0 +1,206 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/connector/usb-connector.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: USB Connector
maintainers:
- Rob Herring <robh@kernel.org>
description:
A USB connector node represents a physical USB connector. It should be a child
of a USB interface controller.
properties:
compatible:
enum:
- usb-a-connector
- usb-b-connector
- usb-c-connector
label:
description: Symbolic name for the connector.
type:
description: Size of the connector, should be specified in case of
non-fullsize 'usb-a-connector' or 'usb-b-connector' compatible
connectors.
allOf:
- $ref: /schemas/types.yaml#definitions/string
enum:
- mini
- micro
self-powered:
description: Set this property if the USB device has its own power source.
type: boolean
# The following are optional properties for "usb-b-connector".
id-gpios:
description: An input gpio for USB ID pin.
maxItems: 1
vbus-gpios:
description: An input gpio for USB VBus pin, used to detect presence of
VBUS 5V.
maxItems: 1
vbus-supply:
description: A phandle to the regulator for USB VBUS if needed when host
mode or dual role mode is supported.
Particularly, if use an output GPIO to control a VBUS regulator, should
model it as a regulator. See bindings/regulator/fixed-regulator.yaml
# The following are optional properties for "usb-c-connector".
power-role:
description: Determines the power role that the Type C connector will
support. "dual" refers to Dual Role Port (DRP).
allOf:
- $ref: /schemas/types.yaml#definitions/string
enum:
- source
- sink
- dual
try-power-role:
description: Preferred power role.
allOf:
- $ref: /schemas/types.yaml#definitions/string
enum:
- source
- sink
- dual
data-role:
description: Data role if Type C connector supports USB data. "dual" refers
Dual Role Device (DRD).
allOf:
- $ref: /schemas/types.yaml#definitions/string
enum:
- host
- device
- dual
# The following are optional properties for "usb-c-connector" with power
# delivery support.
source-pdos:
description: An array of u32 with each entry providing supported power
source data object(PDO), the detailed bit definitions of PDO can be found
in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.2
Source_Capabilities Message, the order of each entry(PDO) should follow
the PD spec chapter 6.4.1. Required for power source and power dual role.
User can specify the source PDO array via PDO_FIXED/BATT/VAR/PPS_APDO()
defined in dt-bindings/usb/pd.h.
minItems: 1
maxItems: 7
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
sink-pdos:
description: An array of u32 with each entry providing supported power sink
data object(PDO), the detailed bit definitions of PDO can be found in
"Universal Serial Bus Power Delivery Specification" chapter 6.4.1.3
Sink Capabilities Message, the order of each entry(PDO) should follow the
PD spec chapter 6.4.1. Required for power sink and power dual role. User
can specify the sink PDO array via PDO_FIXED/BATT/VAR/PPS_APDO() defined
in dt-bindings/usb/pd.h.
minItems: 1
maxItems: 7
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
op-sink-microwatt:
description: Sink required operating power in microwatt, if source can't
offer the power, Capability Mismatch is set. Required for power sink and
power dual role.
ports:
description: OF graph bindings (specified in bindings/graph.txt) that model
any data bus to the connector unless the bus is between parent node and
the connector. Since a single connector can have multiple data buses every
bus has an assigned OF graph port number as described below.
type: object
properties:
port@0:
type: object
description: High Speed (HS), present in all connectors.
port@1:
type: object
description: Super Speed (SS), present in SS capable connectors.
port@2:
type: object
description: Sideband Use (SBU), present in USB-C. This describes the
alternate mode connection of which SBU is a part.
required:
- port@0
required:
- compatible
examples:
# Micro-USB connector with HS lines routed via controller (MUIC).
- |+
muic-max77843 {
usb_con1: connector {
compatible = "usb-b-connector";
label = "micro-USB";
type = "micro";
};
};
# USB-C connector attached to CC controller (s2mm005), HS lines routed
# to companion PMIC (max77865), SS lines to USB3 PHY and SBU to DisplayPort.
# DisplayPort video lines are routed to the connector via SS mux in USB3 PHY.
- |+
ccic: s2mm005 {
usb_con2: connector {
compatible = "usb-c-connector";
label = "USB-C";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_con_hs: endpoint {
remote-endpoint = <&max77865_usbc_hs>;
};
};
port@1 {
reg = <1>;
usb_con_ss: endpoint {
remote-endpoint = <&usbdrd_phy_ss>;
};
};
port@2 {
reg = <2>;
usb_con_sbu: endpoint {
remote-endpoint = <&dp_aux>;
};
};
};
};
};
# USB-C connector attached to a typec port controller(ptn5110), which has
# power delivery support and enables drp.
- |+
#include <dt-bindings/usb/pd.h>
typec: ptn5110 {
usb_con3: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 12000, 2000)>;
op-sink-microwatt = <10000000>;
};
};

8
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@ -71,9 +71,9 @@ properties:
maxItems: 2
reg-names:
items:
- const: vpu
- const: hhi
items:
- const: vpu
- const: hhi
interrupts:
maxItems: 1
@ -107,6 +107,8 @@ required:
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
vpu: vpu@d0100000 {

36
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@ -1,36 +0,0 @@
Vivante GPU core devices
========================
Required properties:
- compatible: Should be "vivante,gc"
A more specific compatible is not needed, as the cores contain chip
identification registers at fixed locations, which provide all the
necessary information to the driver.
- reg: should be register base and length as documented in the
datasheet
- interrupts: Should contain the cores interrupt line
- clocks: should contain one clock for entry in clock-names
see Documentation/devicetree/bindings/clock/clock-bindings.txt
- clock-names:
- "bus": AXI/master interface clock
- "reg": AHB/slave interface clock
(only required if GPU can gate slave interface independently)
- "core": GPU core clock
- "shader": Shader clock (only required if GPU has feature PIPE_3D)
Optional properties:
- power-domains: a power domain consumer specifier according to
Documentation/devicetree/bindings/power/power_domain.txt
example:
gpu_3d: gpu@130000 {
compatible = "vivante,gc";
reg = <0x00130000 0x4000>;
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
<&clks IMX6QDL_CLK_GPU3D_CORE>,
<&clks IMX6QDL_CLK_GPU3D_SHADER>;
clock-names = "bus", "core", "shader";
power-domains = <&gpc 1>;
};

2
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@ -43,6 +43,8 @@ required:
- interrupts
- '#dma-cells'
additionalProperties: false
examples:
- |
dma@3000000 {

63
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@ -0,0 +1,63 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/socionext,uniphier-mio-dmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UniPhier Media IO DMA controller
description: |
This works as an external DMA engine for SD/eMMC controllers etc.
found in UniPhier LD4, Pro4, sLD8 SoCs.
maintainers:
- Masahiro Yamada <yamada.masahiro@socionext.com>
allOf:
- $ref: "dma-controller.yaml#"
properties:
compatible:
const: socionext,uniphier-mio-dmac
reg:
maxItems: 1
interrupts:
description: |
A list of interrupt specifiers associated with the DMA channels.
The number of interrupt lines is SoC-dependent.
clocks:
maxItems: 1
resets:
maxItems: 1
'#dma-cells':
description: The single cell represents the channel index.
const: 1
required:
- compatible
- reg
- interrupts
- clocks
- '#dma-cells'
additionalProperties: false
examples:
- |
// In the example below, "interrupts = <0 68 4>, <0 68 4>, ..." is not a
// typo. The first two channels share a single interrupt line.
dmac: dma-controller@5a000000 {
compatible = "socionext,uniphier-mio-dmac";
reg = <0x5a000000 0x1000>;
interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
<0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
clocks = <&mio_clk 7>;
resets = <&mio_rst 7>;
#dma-cells = <1>;
};

25
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@ -1,25 +0,0 @@
UniPhier Media IO DMA controller
This works as an external DMA engine for SD/eMMC controllers etc.
found in UniPhier LD4, Pro4, sLD8 SoCs.
Required properties:
- compatible: should be "socionext,uniphier-mio-dmac".
- reg: offset and length of the register set for the device.
- interrupts: a list of interrupt specifiers associated with the DMA channels.
- clocks: a single clock specifier.
- #dma-cells: should be <1>. The single cell represents the channel index.
Example:
dmac: dma-controller@5a000000 {
compatible = "socionext,uniphier-mio-dmac";
reg = <0x5a000000 0x1000>;
interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
<0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
clocks = <&mio_clk 7>;
#dma-cells = <1>;
};
Note:
In the example above, "interrupts = <0 68 4>, <0 68 4>, ..." is not a typo.
The first two channels share a single interrupt line.

2
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@ -68,6 +68,8 @@ required:
- mbox-names
- memory-region
additionalProperties: false
examples:
- |
#include <dt-bindings/firmware/imx/rsrc.h>

2
Documentation/devicetree/bindings/eeprom/at24.yaml
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@ -172,6 +172,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {

4
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@ -7,9 +7,9 @@
# $id is a unique identifier based on the filename. There may or may not be a
# file present at the URL.
$id: "http://devicetree.org/schemas/example-schema.yaml#"
$id: http://devicetree.org/schemas/example-schema.yaml#
# $schema is the meta-schema this schema should be validated with.
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: An example schema annotated with jsonschema details

3
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@ -34,9 +34,12 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
npe@c8006000 {
compatible = "intel,ixp4xx-network-processing-engine";
reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
};
...

2
Documentation/devicetree/bindings/gnss/gnss.txt
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@ -8,7 +8,7 @@ bus (e.g. UART, I2C or SPI).
Please refer to the following documents for generic properties:
Documentation/devicetree/bindings/serial/slave-device.txt
Documentation/devicetree/bindings/serial/serial.yaml
Documentation/devicetree/bindings/spi/spi-bus.txt
Required properties:

2
Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml
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@ -47,6 +47,8 @@ required:
- "#gpio-cells"
- gpio-controller
additionalProperties: false
dependencies:
interrupt-controller: [ interrupts ]

2
Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
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@ -14,7 +14,7 @@ Required properties:
"marvell,armada-8k-gpio" should be used for the Armada 7K and 8K
SoCs (either from AP or CP), see
Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt
for specific details about the offset property.
- reg: Address and length of the register set for the device. Only one

51
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@ -1,51 +0,0 @@
UniPhier GPIO controller
Required properties:
- compatible: Should be "socionext,uniphier-gpio".
- reg: Specifies offset and length of the register set for the device.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be 2. The first cell is the pin number and the second
cell is used to specify optional parameters.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be 2. The first cell defines the interrupt number.
The second cell bits[3:0] is used to specify trigger type as follows:
1 = low-to-high edge triggered
2 = high-to-low edge triggered
4 = active high level-sensitive
8 = active low level-sensitive
Valid combinations are 1, 2, 3, 4, 8.
- ngpios: Specifies the number of GPIO lines.
- gpio-ranges: Mapping to pin controller pins (as described in gpio.txt)
- socionext,interrupt-ranges: Specifies an interrupt number mapping between
this GPIO controller and its interrupt parent, in the form of arbitrary
number of <child-interrupt-base parent-interrupt-base length> triplets.
Optional properties:
- gpio-ranges-group-names: Used for named gpio ranges (as described in gpio.txt)
Example:
gpio: gpio@55000000 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000000 0x200>;
interrupt-parent = <&aidet>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 0>;
gpio-ranges-group-names = "gpio_range";
ngpios = <248>;
socionext,interrupt-ranges = <0 48 16>, <16 154 5>, <21 217 3>;
};
Consumer Example:
sdhci0_pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio UNIPHIER_GPIO_PORT(29, 4) GPIO_ACTIVE_LOW>;
};
Please note UNIPHIER_GPIO_PORT(29, 4) represents PORT294 in the SoC document.
Unfortunately, only the one's place is octal in the port numbering. (That is,
PORT 8, 9, 18, 19, 28, 29, ... are missing.) UNIPHIER_GPIO_PORT() is a helper
macro to calculate 29 * 8 + 4.

94
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@ -0,0 +1,94 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UniPhier GPIO controller
maintainers:
- Masahiro Yamada <yamada.masahiro@socionext.com>
properties:
$nodename:
pattern: "^gpio@[0-9a-f]+$"
compatible:
const: socionext,uniphier-gpio
reg:
maxItems: 1
gpio-controller: true
"#gpio-cells":
const: 2
interrupt-controller: true
"#interrupt-cells":
description: |
The first cell defines the interrupt number.
The second cell bits[3:0] is used to specify trigger type as follows:
1 = low-to-high edge triggered
2 = high-to-low edge triggered
4 = active high level-sensitive
8 = active low level-sensitive
Valid combinations are 1, 2, 3, 4, 8.
const: 2
ngpios:
minimum: 0
maximum: 512
gpio-ranges: true
gpio-ranges-group-names:
$ref: /schemas/types.yaml#/definitions/string-array
socionext,interrupt-ranges:
description: |
Specifies an interrupt number mapping between this GPIO controller and
its interrupt parent, in the form of arbitrary number of
<child-interrupt-base parent-interrupt-base length> triplets.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
- interrupt-controller
- "#interrupt-cells"
- ngpios
- gpio-ranges
- socionext,interrupt-ranges
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
gpio: gpio@55000000 {
compatible = "socionext,uniphier-gpio";
reg = <0x55000000 0x200>;
interrupt-parent = <&aidet>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 0>;
gpio-ranges-group-names = "gpio_range";
ngpios = <248>;
socionext,interrupt-ranges = <0 48 16>, <16 154 5>, <21 217 3>;
};
// Consumer:
// Please note UNIPHIER_GPIO_PORT(29, 4) represents PORT294 in the SoC
// document. Unfortunately, only the one's place is octal in the port
// numbering. (That is, PORT 8, 9, 18, 19, 28, 29, ... do not exist.)
// UNIPHIER_GPIO_PORT() is a helper macro to calculate 29 * 8 + 4.
sdhci0_pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio UNIPHIER_GPIO_PORT(29, 4) GPIO_ACTIVE_LOW>;
};

2
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@ -49,6 +49,8 @@ required:
- "#gpio-cells"
- gpio-controller
additionalProperties: false
examples:
- |
logicvc: logicvc@43c00000 {

8
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@ -43,6 +43,9 @@ properties:
operating-points-v2: true
resets:
maxItems: 2
required:
- compatible
- reg
@ -50,6 +53,8 @@ required:
- interrupt-names
- clocks
additionalProperties: false
allOf:
- if:
properties:
@ -57,9 +62,6 @@ allOf:
contains:
const: amlogic,meson-g12a-mali
then:
properties:
resets:
minItems: 2
required:
- resets

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@ -75,6 +75,9 @@ properties:
mali-supply: true
power-domains:
maxItems: 1
resets:
minItems: 1
maxItems: 2
@ -91,6 +94,8 @@ required:
- interrupt-names
- clocks
additionalProperties: false
allOf:
- if:
properties:

2
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@ -115,6 +115,8 @@ required:
- clocks
- clock-names
additionalProperties: false
allOf:
- if:
properties:

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@ -36,6 +36,8 @@ required:
- clocks
- clock-names
additionalProperties: false
examples:
- |
rotator@12810000 {

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@ -0,0 +1,69 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Vivante GPU Bindings
description: Vivante GPU core devices
maintainers:
- Lucas Stach <l.stach@pengutronix.de>
properties:
compatible:
const: vivante,gc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: AXI/master interface clock
- description: GPU core clock
- description: Shader clock (only required if GPU has feature PIPE_3D)
- description: AHB/slave interface clock (only required if GPU can gate slave interface independently)
minItems: 1
maxItems: 4
clock-names:
items:
enum: [ bus, core, shader, reg ]
minItems: 1
maxItems: 4
resets:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
gpu@130000 {
compatible = "vivante,gc";
reg = <0x00130000 0x4000>;
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
<&clks IMX6QDL_CLK_GPU3D_CORE>,
<&clks IMX6QDL_CLK_GPU3D_SHADER>;
clock-names = "bus", "core", "shader";
power-domains = <&gpc 1>;
};
...

2
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@ -47,6 +47,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>

2
Documentation/devicetree/bindings/hwmon/adi,ltc2947.yaml
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@ -87,6 +87,8 @@ required:
- reg
additionalProperties: false
examples:
- |
spi {

2
Documentation/devicetree/bindings/hwmon/pmbus/ti,ucd90320.yaml
View File

@ -32,6 +32,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {

2
Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml
View File

@ -76,6 +76,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {

68
Documentation/devicetree/bindings/i2c/i2c-rk3x.txt
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@ -1,68 +0,0 @@
* Rockchip RK3xxx I2C controller
This driver interfaces with the native I2C controller present in Rockchip
RK3xxx SoCs.
Required properties :
- reg : Offset and length of the register set for the device
- compatible: should be one of the following:
- "rockchip,rv1108-i2c": for rv1108
- "rockchip,rk3066-i2c": for rk3066
- "rockchip,rk3188-i2c": for rk3188
- "rockchip,rk3228-i2c": for rk3228
- "rockchip,rk3288-i2c": for rk3288
- "rockchip,rk3328-i2c", "rockchip,rk3399-i2c": for rk3328
- "rockchip,rk3399-i2c": for rk3399
- interrupts : interrupt number
- clocks: See ../clock/clock-bindings.txt
- For older hardware (rk3066, rk3188, rk3228, rk3288):
- There is one clock that's used both to derive the functional clock
for the device and as the bus clock.
- For newer hardware (rk3399): specified by name
- "i2c": This is used to derive the functional clock.
- "pclk": This is the bus clock.
Required on RK3066, RK3188 :
- rockchip,grf : the phandle of the syscon node for the general register
file (GRF)
- on those SoCs an alias with the correct I2C bus ID (bit offset in the GRF)
is also required.
Optional properties :
- clock-frequency : SCL frequency to use (in Hz). If omitted, 100kHz is used.
- i2c-scl-rising-time-ns : Number of nanoseconds the SCL signal takes to rise
(t(r) in I2C specification). If not specified this is assumed to be
the maximum the specification allows(1000 ns for Standard-mode,
300 ns for Fast-mode) which might cause slightly slower communication.
- i2c-scl-falling-time-ns : Number of nanoseconds the SCL signal takes to fall
(t(f) in the I2C specification). If not specified this is assumed to
be the maximum the specification allows (300 ns) which might cause
slightly slower communication.
- i2c-sda-falling-time-ns : Number of nanoseconds the SDA signal takes to fall
(t(f) in the I2C specification). If not specified we'll use the SCL
value since they are the same in nearly all cases.
Example:
aliases {
i2c0 = &i2c0;
}
i2c0: i2c@2002d000 {
compatible = "rockchip,rk3188-i2c";
reg = <0x2002d000 0x1000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
rockchip,grf = <&grf>;
clock-names = "i2c";
clocks = <&cru PCLK_I2C0>;
i2c-scl-rising-time-ns = <800>;
i2c-scl-falling-time-ns = <100>;
};

136
Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml Normal file
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@ -0,0 +1,136 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-rk3x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip RK3xxx I2C controller
description:
This driver interfaces with the native I2C controller present in Rockchip
RK3xxx SoCs.
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
maintainers:
- Heiko Stuebner <heiko@sntech.de>
# Everything else is described in the common file
properties:
compatible:
oneOf:
- const: rockchip,rv1108-i2c
- const: rockchip,rk3066-i2c
- const: rockchip,rk3188-i2c
- const: rockchip,rk3228-i2c
- const: rockchip,rk3288-i2c
- const: rockchip,rk3399-i2c
- items:
- enum:
- rockchip,rk3036-i2c
- rockchip,rk3368-i2c
- const: rockchip,rk3288-i2c
- items:
- enum:
- rockchip,px30-i2c
- rockchip,rk3308-i2c
- rockchip,rk3328-i2c
- const: rockchip,rk3399-i2c
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
items:
- description:
For older hardware (rk3066, rk3188, rk3228, rk3288)
there is one clock that is used both to derive the functional clock
for the device and as the bus clock.
For newer hardware (rk3399) this clock is used to derive
the functional clock
- description:
For newer hardware (rk3399) this is the bus clock
clock-names:
minItems: 1
items:
- const: i2c
- const: pclk
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Required on RK3066, RK3188 the phandle of the syscon node for
the general register file (GRF)
On those SoCs an alias with the correct I2C bus ID
(bit offset in the GRF) is also required.
clock-frequency:
default: 100000
description:
SCL frequency to use (in Hz). If omitted, 100kHz is used.
i2c-scl-rising-time-ns:
default: 1000
description:
Number of nanoseconds the SCL signal takes to rise
(t(r) in I2C specification). If not specified this is assumed to be
the maximum the specification allows(1000 ns for Standard-mode,
300 ns for Fast-mode) which might cause slightly slower communication.
i2c-scl-falling-time-ns:
default: 300
description:
Number of nanoseconds the SCL signal takes to fall
(t(f) in the I2C specification). If not specified this is assumed to
be the maximum the specification allows (300 ns) which might cause
slightly slower communication.
i2c-sda-falling-time-ns:
default: 300
description:
Number of nanoseconds the SDA signal takes to fall
(t(f) in the I2C specification). If not specified we will use the SCL
value since they are the same in nearly all cases.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
if:
properties:
compatible:
contains:
enum:
- rockchip,rk3066-i2c
- rockchip,rk3188-i2c
then:
required:
- rockchip,grf
examples:
- |
#include <dt-bindings/clock/rk3188-cru-common.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c0: i2c@2002d000 {
compatible = "rockchip,rk3188-i2c";
reg = <0x2002d000 0x1000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_I2C0>;
clock-names = "i2c";
rockchip,grf = <&grf>;
i2c-scl-falling-time-ns = <100>;
i2c-scl-rising-time-ns = <800>;
#address-cells = <1>;
#size-cells = <0>;
};

25
Documentation/devicetree/bindings/i2c/i2c-uniphier-f.txt
View File

@ -1,25 +0,0 @@
UniPhier I2C controller (FIFO-builtin)
Required properties:
- compatible: should be "socionext,uniphier-fi2c".
- #address-cells: should be 1.
- #size-cells: should be 0.
- reg: offset and length of the register set for the device.
- interrupts: a single interrupt specifier.
- clocks: phandle to the input clock.
Optional properties:
- clock-frequency: desired I2C bus frequency in Hz. The maximum supported
value is 400000. Defaults to 100000 if not specified.
Examples:
i2c0: i2c@58780000 {
compatible = "socionext,uniphier-fi2c";
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 4>;
clocks = <&i2c_clk>;
clock-frequency = <100000>;
};

25
Documentation/devicetree/bindings/i2c/i2c-uniphier.txt
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@ -1,25 +0,0 @@
UniPhier I2C controller (FIFO-less)
Required properties:
- compatible: should be "socionext,uniphier-i2c".
- #address-cells: should be 1.
- #size-cells: should be 0.
- reg: offset and length of the register set for the device.
- interrupts: a single interrupt specifier.
- clocks: phandle to the input clock.
Optional properties:
- clock-frequency: desired I2C bus frequency in Hz. The maximum supported
value is 400000. Defaults to 100000 if not specified.
Examples:
i2c0: i2c@58400000 {
compatible = "socionext,uniphier-i2c";
reg = <0x58400000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 1>;
clocks = <&i2c_clk>;
clock-frequency = <100000>;
};

50
Documentation/devicetree/bindings/i2c/socionext,uniphier-fi2c.yaml Normal file
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@ -0,0 +1,50 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/socionext,uniphier-fi2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UniPhier I2C controller (FIFO-builtin)
maintainers:
- Masahiro Yamada <yamada.masahiro@socionext.com>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
properties:
compatible:
const: socionext,uniphier-fi2c
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-frequency:
minimum: 100000
maximum: 400000
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- interrupts
- clocks
examples:
- |
i2c0: i2c@58780000 {
compatible = "socionext,uniphier-fi2c";
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 4>;
clocks = <&i2c_clk>;
clock-frequency = <100000>;
};

50
Documentation/devicetree/bindings/i2c/socionext,uniphier-i2c.yaml Normal file
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@ -0,0 +1,50 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/socionext,uniphier-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UniPhier I2C controller (FIFO-less)
maintainers:
- Masahiro Yamada <yamada.masahiro@socionext.com>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
properties:
compatible:
const: socionext,uniphier-i2c
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-frequency:
minimum: 100000
maximum: 400000
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- interrupts
- clocks
examples:
- |
i2c0: i2c@58400000 {
compatible = "socionext,uniphier-i2c";
reg = <0x58400000 0x40>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 1>;
clocks = <&i2c_clk>;
clock-frequency = <100000>;
};

10
Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml
View File

@ -17,9 +17,13 @@ description: |
properties:
compatible:
enum:
- adi,adxl345
- adi,adxl375
oneOf:
- items:
- const: adi,adxl346
- const: adi,adxl345
- enum:
- adi,adxl345
- adi,adxl375
reg:
maxItems: 1

2
Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml
View File

@ -36,6 +36,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>

1
Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
View File

@ -106,7 +106,6 @@ examples:
spi-cpha;
clocks = <&ad7192_mclk>;
clock-names = "mclk";
#interrupt-cells = <2>;
interrupts = <25 0x2>;
interrupt-parent = <&gpio>;
dvdd-supply = <&dvdd>;

2
Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml
View File

@ -67,6 +67,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>

2
Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml
View File

@ -53,6 +53,8 @@ required:
- dout-gpios
- avdd-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>

2
Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml
View File

@ -32,6 +32,8 @@ required:
- vref-supply
- reg
additionalProperties: false
examples:
- |
spi {

2
Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml
View File

@ -52,6 +52,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
spi {

2
Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
View File

@ -69,6 +69,8 @@ required:
- "#address-cells"
- "#size-cells"
additionalProperties: false
patternProperties:
"^filter@[0-9]+$":
type: object

2
Documentation/devicetree/bindings/iio/chemical/plantower,pms7003.yaml
View File

@ -38,6 +38,8 @@ required:
- compatible
- vcc-supply
additionalProperties: false
examples:
- |
serial {

2
Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.yaml
View File

@ -24,6 +24,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {

2
Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml
View File

@ -34,6 +34,8 @@ required:
- reg
- vref-supply
additionalProperties: false
examples:
- |
spi {

2
Documentation/devicetree/bindings/iio/light/adux1020.yaml
View File

@ -28,6 +28,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>

2
Documentation/devicetree/bindings/iio/light/bh1750.yaml
View File

@ -28,6 +28,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {

2
Documentation/devicetree/bindings/iio/light/isl29018.yaml
View File

@ -38,6 +38,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>

2
Documentation/devicetree/bindings/iio/light/noa1305.yaml
View File

@ -29,6 +29,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {

2
Documentation/devicetree/bindings/iio/light/stk33xx.yaml
View File

@ -30,6 +30,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>

2
Documentation/devicetree/bindings/iio/light/tsl2583.yaml
View File

@ -32,6 +32,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {

2
Documentation/devicetree/bindings/iio/light/tsl2772.yaml
View File

@ -62,6 +62,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>

2
Documentation/devicetree/bindings/iio/light/veml6030.yaml
View File

@ -45,6 +45,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>

2
Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml
View File

@ -33,6 +33,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>

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