pinctrl: meson: meson8: add the RGMII RXD2/RXD3 and TXD2/TXD3 signals
These are only available on the Meson8m2 SoC (which uses the same DesignWare Ethernet MAC as Meson8b). The "eth_tx_clk_50m" signal either provides a 50MHz clock for the RMII PHYs or the RGMII TX clock (as far as we know the frequency is controlled by the PRG_ETHERNET registers in the Ethernet MAC "glue" IP block). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -299,6 +299,10 @@ static const unsigned int spi_mosi_1_pins[] = { GPIOZ_12 };
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static const unsigned int spi_miso_1_pins[] = { GPIOZ_13 };
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static const unsigned int spi_ss2_1_pins[] = { GPIOZ_14 };
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static const unsigned int eth_txd3_pins[] = { GPIOZ_0 };
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static const unsigned int eth_txd2_pins[] = { GPIOZ_1 };
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static const unsigned int eth_rxd3_pins[] = { GPIOZ_2 };
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static const unsigned int eth_rxd2_pins[] = { GPIOZ_3 };
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static const unsigned int eth_tx_clk_50m_pins[] = { GPIOZ_4 };
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static const unsigned int eth_tx_en_pins[] = { GPIOZ_5 };
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static const unsigned int eth_txd1_pins[] = { GPIOZ_6 };
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@ -650,6 +654,12 @@ static struct meson_pmx_group meson8_cbus_groups[] = {
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GROUP(eth_mdio, 6, 6),
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GROUP(eth_mdc, 6, 5),
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/* NOTE: the following four groups are only available on Meson8m2: */
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GROUP(eth_rxd2, 6, 3),
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GROUP(eth_rxd3, 6, 2),
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GROUP(eth_txd2, 6, 1),
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GROUP(eth_txd3, 6, 0),
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GROUP(i2c_sda_a0, 5, 31),
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GROUP(i2c_sck_a0, 5, 30),
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@ -877,7 +887,8 @@ static const char * const spi_groups[] = {
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static const char * const ethernet_groups[] = {
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"eth_tx_clk_50m", "eth_tx_en", "eth_txd1",
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"eth_txd0", "eth_rx_clk_in", "eth_rx_dv",
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"eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc"
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"eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc", "eth_rxd2",
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"eth_rxd3", "eth_txd2", "eth_txd3"
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};
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static const char * const i2c_a_groups[] = {
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