Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq fixes from Ingo Molnar: "Mostly irqchip driver fixes, plus a symbol export" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: kernel/irq: Export irq_set_parent() irqchip/gic: Add missing \n to CPU IF adjustment message irqchip/jcore: Don't show Kconfig menu item for driver irqchip/eznps: Drop pointless static qualifier in nps400_of_init() irqchip/gic-v3-its: Fix entry size mask for GITS_BASER irqchip/gic-v3-its: Fix 64bit GIC{R,ITS}_TYPER accesses
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commit
bfb7bfef6f
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@ -158,8 +158,8 @@ config PIC32_EVIC
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select IRQ_DOMAIN
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config JCORE_AIC
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bool "J-Core integrated AIC"
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depends on OF && (SUPERH || COMPILE_TEST)
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bool "J-Core integrated AIC" if COMPILE_TEST
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depends on OF
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select IRQ_DOMAIN
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help
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Support for the J-Core integrated AIC.
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@ -135,7 +135,7 @@ static const struct irq_domain_ops nps400_irq_ops = {
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static int __init nps400_of_init(struct device_node *node,
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struct device_node *parent)
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{
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static struct irq_domain *nps400_root_domain;
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struct irq_domain *nps400_root_domain;
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if (parent) {
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pr_err("DeviceTree incore ic not a root irq controller\n");
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@ -1023,7 +1023,7 @@ static void its_free_tables(struct its_node *its)
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static int its_alloc_tables(struct its_node *its)
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{
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u64 typer = readq_relaxed(its->base + GITS_TYPER);
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u64 typer = gic_read_typer(its->base + GITS_TYPER);
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u32 ids = GITS_TYPER_DEVBITS(typer);
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u64 shr = GITS_BASER_InnerShareable;
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u64 cache = GITS_BASER_WaWb;
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@ -1198,7 +1198,7 @@ static void its_cpu_init_collection(void)
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* We now have to bind each collection to its target
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* redistributor.
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*/
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if (readq_relaxed(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
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if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
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/*
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* This ITS wants the physical address of the
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* redistributor.
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@ -1208,7 +1208,7 @@ static void its_cpu_init_collection(void)
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/*
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* This ITS wants a linear CPU number.
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*/
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target = readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER);
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target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
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target = GICR_TYPER_CPU_NUMBER(target) << 16;
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}
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@ -1691,7 +1691,7 @@ static int __init its_probe_one(struct resource *res,
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INIT_LIST_HEAD(&its->its_device_list);
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its->base = its_base;
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its->phys_base = res->start;
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its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1;
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its->ite_size = ((gic_read_typer(its_base + GITS_TYPER) >> 4) & 0xf) + 1;
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its->numa_node = numa_node;
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its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL);
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@ -1763,7 +1763,7 @@ static int __init its_probe_one(struct resource *res,
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static bool gic_rdists_supports_plpis(void)
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{
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return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
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return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
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}
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int its_cpu_init(void)
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@ -1279,7 +1279,7 @@ static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
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*/
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*base += 0xf000;
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cpuif_res.start += 0xf000;
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pr_warn("GIC: Adjusting CPU interface base to %pa",
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pr_warn("GIC: Adjusting CPU interface base to %pa\n",
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&cpuif_res.start);
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}
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@ -290,7 +290,7 @@
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#define GITS_BASER_TYPE_SHIFT (56)
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#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
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#define GITS_BASER_ENTRY_SIZE_SHIFT (48)
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#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0xff) + 1)
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#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
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#define GITS_BASER_SHAREABILITY_SHIFT (10)
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#define GITS_BASER_InnerShareable \
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GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
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@ -721,6 +721,7 @@ int irq_set_parent(int irq, int parent_irq)
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irq_put_desc_unlock(desc, flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(irq_set_parent);
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#endif
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/*
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