ARM: mach-imx: clk-imx51-imx53: Retrieve base address and irq from dt
As mx53 is a dt-only SoC, we should retrieve the gpt base address and irq from the device tree, instead of using the old MX53_IO_ADDRESS method. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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@ -14,6 +14,9 @@
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#include <linux/clk-provider.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of.h>
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#include <linux/err.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include "crm-regs-imx5.h"
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#include "crm-regs-imx5.h"
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#include "clk.h"
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#include "clk.h"
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@ -472,8 +475,9 @@ CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt);
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static void __init mx53_clocks_init(struct device_node *np)
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static void __init mx53_clocks_init(struct device_node *np)
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{
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{
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int i;
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int i, irq;
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unsigned long r;
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unsigned long r;
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void __iomem *base;
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clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
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clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
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clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
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clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
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@ -559,14 +563,17 @@ static void __init mx53_clocks_init(struct device_node *np)
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clk_set_rate(clk[esdhc_a_podf], 200000000);
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clk_set_rate(clk[esdhc_a_podf], 200000000);
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clk_set_rate(clk[esdhc_b_podf], 200000000);
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clk_set_rate(clk[esdhc_b_podf], 200000000);
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/* System timer */
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mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT);
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clk_prepare_enable(clk[iim_gate]);
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clk_prepare_enable(clk[iim_gate]);
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imx_print_silicon_rev("i.MX53", mx53_revision());
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imx_print_silicon_rev("i.MX53", mx53_revision());
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clk_disable_unprepare(clk[iim_gate]);
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clk_disable_unprepare(clk[iim_gate]);
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r = clk_round_rate(clk[usboh3_per_gate], 54000000);
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r = clk_round_rate(clk[usboh3_per_gate], 54000000);
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clk_set_rate(clk[usboh3_per_gate], r);
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clk_set_rate(clk[usboh3_per_gate], r);
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np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt");
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base = of_iomap(np, 0);
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WARN_ON(!base);
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irq = irq_of_parse_and_map(np, 0);
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mxc_timer_init(base, irq);
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}
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}
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CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
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CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
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