Actions Semi ARM SoC for v4.13 #2
This adds SMP code to bring up the remaining S500 CPU cores by reusing a helper factored out of the SPS power domains driver. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABAgAGBQJZTUjlAAoJEPou0S0+fgE/yxgP/1J/t1eSTX9l+NkP6bxmsKNk k4KKCwhch57Mw14iPTysOaezAn/2YNVLEYKSa0JNYOmrUA4Y2gyra0LhAejh7Jd8 Y3FGdYbbgRHTY0DLAK+vMVnRjHrUu7O+Xgngf6bNRdwL4+qBGTxHMvdoFaWRdZZv 6bjKAeDAkCKQ62xXTdT9EaKFSPKzLgYyT+7ey3JE5J6MlKVvzjxyG4HtFm9DYpH5 LvuQ1oZdtVs2Ils8lOF8Z8VRPaKCP4XhnYIqQ4fP9tvaF6lL4R0xYXtMWG4aRpXT +g50M0+iE61BUyvCbBsT8eEUnasmmYxtI9eeAj9/HZ3vOem3zuZ4HxbUv+Ss39fS 39IwQvallLpykKRpykbCXfIyLxIO1XKQk/UQwwSB0nD3QETPmbJB8pbel7LH3VFW /hdF7aDq8HlL5hvXp9PLC9/avNCkuZWrjhyj+qUZePpRaF6xi0VPDybpJLfoGfw2 OPf6JNq317Bw+OII7TNzYMPclCb4UU0+n1wLQyMaDRfc0Riplec8hUQlMTg3aTsZ Oj+5g4+m19yahoQEWf6DyXRLk7JQEpbuKhmD2HzC5wJbsfU1COcx9WN2BZeRWGTS AD++5WYXwaNdskbGt5UpFvqipWmWq6UVAMolid29f5jN1jUyEJ6ychq307kakhWU nYJwn+KDIaICR9KmFy19 =VNDJ -----END PGP SIGNATURE----- Merge tag 'actions-arm-soc+sps-for-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions into next/soc Pull "Actions Semi ARM SoC for v4.13 #2" from Andreas Färber: This adds SMP code to bring up the remaining S500 CPU cores by reusing a helper factored out of the SPS power domains driver. * tag 'actions-arm-soc+sps-for-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions: ARM: owl: smp: Implement SPS power-gating for CPU2 and CPU3 soc: actions: owl-sps: Factor out owl_sps_set_pg() for power-gating soc: actions: Add Owl SPS dt-bindings: power: Add Owl SPS power domains
This commit is contained in:
Arnd Bergmann
commit
c070d6ba25
|
|
@ -0,0 +1,17 @@
|
|||
Actions Semi Owl Smart Power System (SPS)
|
||||
|
||||
Required properties:
|
||||
- compatible : "actions,s500-sps" for S500
|
||||
- reg : Offset and length of the register set for the device.
|
||||
- #power-domain-cells : Must be 1.
|
||||
See macros in:
|
||||
include/dt-bindings/power/owl-s500-powergate.h for S500
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
sps: power-controller@b01b0100 {
|
||||
compatible = "actions,s500-sps";
|
||||
reg = <0xb01b0100 0x100>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
|
@ -10,6 +10,7 @@ menuconfig ARCH_ACTIONS
|
|||
select GENERIC_IRQ_CHIP
|
||||
select HAVE_ARM_SCU if SMP
|
||||
select HAVE_ARM_TWD if SMP
|
||||
select OWL_PM_DOMAINS_HELPER
|
||||
select OWL_TIMER
|
||||
help
|
||||
This enables support for the Actions Semiconductor S500 SoC family.
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/soc/actions/owl-sps.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/smp_scu.h>
|
||||
|
|
@ -28,7 +29,13 @@
|
|||
|
||||
#define OWL_CPUx_FLAG_BOOT 0x55aa
|
||||
|
||||
#define OWL_SPS_PG_CTL_PWR_CPU2 BIT(5)
|
||||
#define OWL_SPS_PG_CTL_PWR_CPU3 BIT(6)
|
||||
#define OWL_SPS_PG_CTL_ACK_CPU2 BIT(21)
|
||||
#define OWL_SPS_PG_CTL_ACK_CPU3 BIT(22)
|
||||
|
||||
static void __iomem *scu_base_addr;
|
||||
static void __iomem *sps_base_addr;
|
||||
static void __iomem *timer_base_addr;
|
||||
static int ncores;
|
||||
|
||||
|
|
@ -58,14 +65,27 @@ void owl_secondary_startup(void);
|
|||
|
||||
static int s500_wakeup_secondary(unsigned int cpu)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (cpu > 3)
|
||||
return -EINVAL;
|
||||
|
||||
/* The generic PM domain driver is not available this early. */
|
||||
switch (cpu) {
|
||||
case 2:
|
||||
ret = owl_sps_set_pg(sps_base_addr,
|
||||
OWL_SPS_PG_CTL_PWR_CPU2,
|
||||
OWL_SPS_PG_CTL_ACK_CPU2, true);
|
||||
if (ret)
|
||||
return ret;
|
||||
break;
|
||||
case 3:
|
||||
/* CPU2/3 are power-gated */
|
||||
return -EINVAL;
|
||||
ret = owl_sps_set_pg(sps_base_addr,
|
||||
OWL_SPS_PG_CTL_PWR_CPU3,
|
||||
OWL_SPS_PG_CTL_ACK_CPU3, true);
|
||||
if (ret)
|
||||
return ret;
|
||||
break;
|
||||
}
|
||||
|
||||
/* wait for CPUx to run to WFE instruction */
|
||||
|
|
@ -133,6 +153,18 @@ static void __init s500_smp_prepare_cpus(unsigned int max_cpus)
|
|||
return;
|
||||
}
|
||||
|
||||
node = of_find_compatible_node(NULL, NULL, "actions,s500-sps");
|
||||
if (!node) {
|
||||
pr_err("%s: missing sps\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
sps_base_addr = of_iomap(node, 0);
|
||||
if (!sps_base_addr) {
|
||||
pr_err("%s: could not map sps registers\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
|
||||
node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
|
||||
if (!node) {
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
menu "SOC (System On Chip) specific Drivers"
|
||||
|
||||
source "drivers/soc/actions/Kconfig"
|
||||
source "drivers/soc/atmel/Kconfig"
|
||||
source "drivers/soc/bcm/Kconfig"
|
||||
source "drivers/soc/fsl/Kconfig"
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
# Makefile for the Linux Kernel SOC specific device drivers.
|
||||
#
|
||||
|
||||
obj-$(CONFIG_ARCH_ACTIONS) += actions/
|
||||
obj-$(CONFIG_ARCH_AT91) += atmel/
|
||||
obj-y += bcm/
|
||||
obj-$(CONFIG_ARCH_DOVE) += dove/
|
||||
|
|
|
|||
|
|
@ -0,0 +1,16 @@
|
|||
if ARCH_ACTIONS || COMPILE_TEST
|
||||
|
||||
config OWL_PM_DOMAINS_HELPER
|
||||
bool
|
||||
|
||||
config OWL_PM_DOMAINS
|
||||
bool "Actions Semi SPS power domains"
|
||||
depends on PM
|
||||
select OWL_PM_DOMAINS_HELPER
|
||||
select PM_GENERIC_DOMAINS
|
||||
help
|
||||
Say 'y' here to enable support for Smart Power System (SPS)
|
||||
power-gating on Actions Semiconductor S500 SoC.
|
||||
If unsure, say 'n'.
|
||||
|
||||
endif
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
obj-$(CONFIG_OWL_PM_DOMAINS_HELPER) += owl-sps-helper.o
|
||||
obj-$(CONFIG_OWL_PM_DOMAINS) += owl-sps.o
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* Actions Semi Owl Smart Power System (SPS) shared helpers
|
||||
*
|
||||
* Copyright 2012 Actions Semi Inc.
|
||||
* Author: Actions Semi, Inc.
|
||||
*
|
||||
* Copyright (c) 2017 Andreas Färber
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#define OWL_SPS_PG_CTL 0x0
|
||||
|
||||
int owl_sps_set_pg(void __iomem *base, u32 pwr_mask, u32 ack_mask, bool enable)
|
||||
{
|
||||
u32 val;
|
||||
bool ack;
|
||||
int timeout;
|
||||
|
||||
val = readl(base + OWL_SPS_PG_CTL);
|
||||
ack = val & ack_mask;
|
||||
if (ack == enable)
|
||||
return 0;
|
||||
|
||||
if (enable)
|
||||
val |= pwr_mask;
|
||||
else
|
||||
val &= ~pwr_mask;
|
||||
|
||||
writel(val, base + OWL_SPS_PG_CTL);
|
||||
|
||||
for (timeout = 5000; timeout > 0; timeout -= 50) {
|
||||
val = readl(base + OWL_SPS_PG_CTL);
|
||||
if ((val & ack_mask) == (enable ? ack_mask : 0))
|
||||
break;
|
||||
udelay(50);
|
||||
}
|
||||
if (timeout <= 0)
|
||||
return -ETIMEDOUT;
|
||||
|
||||
udelay(10);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(owl_sps_set_pg);
|
||||
|
|
@ -0,0 +1,224 @@
|
|||
/*
|
||||
* Actions Semi Owl Smart Power System (SPS)
|
||||
*
|
||||
* Copyright 2012 Actions Semi Inc.
|
||||
* Author: Actions Semi, Inc.
|
||||
*
|
||||
* Copyright (c) 2017 Andreas Färber
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/soc/actions/owl-sps.h>
|
||||
#include <dt-bindings/power/owl-s500-powergate.h>
|
||||
|
||||
struct owl_sps_domain_info {
|
||||
const char *name;
|
||||
int pwr_bit;
|
||||
int ack_bit;
|
||||
unsigned int genpd_flags;
|
||||
};
|
||||
|
||||
struct owl_sps_info {
|
||||
unsigned num_domains;
|
||||
const struct owl_sps_domain_info *domains;
|
||||
};
|
||||
|
||||
struct owl_sps {
|
||||
struct device *dev;
|
||||
const struct owl_sps_info *info;
|
||||
void __iomem *base;
|
||||
struct genpd_onecell_data genpd_data;
|
||||
struct generic_pm_domain *domains[];
|
||||
};
|
||||
|
||||
#define to_owl_pd(gpd) container_of(gpd, struct owl_sps_domain, genpd)
|
||||
|
||||
struct owl_sps_domain {
|
||||
struct generic_pm_domain genpd;
|
||||
const struct owl_sps_domain_info *info;
|
||||
struct owl_sps *sps;
|
||||
};
|
||||
|
||||
static int owl_sps_set_power(struct owl_sps_domain *pd, bool enable)
|
||||
{
|
||||
u32 pwr_mask, ack_mask;
|
||||
|
||||
ack_mask = BIT(pd->info->ack_bit);
|
||||
pwr_mask = BIT(pd->info->pwr_bit);
|
||||
|
||||
return owl_sps_set_pg(pd->sps->base, pwr_mask, ack_mask, enable);
|
||||
}
|
||||
|
||||
static int owl_sps_power_on(struct generic_pm_domain *domain)
|
||||
{
|
||||
struct owl_sps_domain *pd = to_owl_pd(domain);
|
||||
|
||||
dev_dbg(pd->sps->dev, "%s power on", pd->info->name);
|
||||
|
||||
return owl_sps_set_power(pd, true);
|
||||
}
|
||||
|
||||
static int owl_sps_power_off(struct generic_pm_domain *domain)
|
||||
{
|
||||
struct owl_sps_domain *pd = to_owl_pd(domain);
|
||||
|
||||
dev_dbg(pd->sps->dev, "%s power off", pd->info->name);
|
||||
|
||||
return owl_sps_set_power(pd, false);
|
||||
}
|
||||
|
||||
static int owl_sps_init_domain(struct owl_sps *sps, int index)
|
||||
{
|
||||
struct owl_sps_domain *pd;
|
||||
|
||||
pd = devm_kzalloc(sps->dev, sizeof(*pd), GFP_KERNEL);
|
||||
if (!pd)
|
||||
return -ENOMEM;
|
||||
|
||||
pd->info = &sps->info->domains[index];
|
||||
pd->sps = sps;
|
||||
|
||||
pd->genpd.name = pd->info->name;
|
||||
pd->genpd.power_on = owl_sps_power_on;
|
||||
pd->genpd.power_off = owl_sps_power_off;
|
||||
pd->genpd.flags = pd->info->genpd_flags;
|
||||
pm_genpd_init(&pd->genpd, NULL, false);
|
||||
|
||||
sps->genpd_data.domains[index] = &pd->genpd;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int owl_sps_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
const struct owl_sps_info *sps_info;
|
||||
struct owl_sps *sps;
|
||||
int i, ret;
|
||||
|
||||
if (!pdev->dev.of_node) {
|
||||
dev_err(&pdev->dev, "no device node\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
match = of_match_device(pdev->dev.driver->of_match_table, &pdev->dev);
|
||||
if (!match || !match->data) {
|
||||
dev_err(&pdev->dev, "unknown compatible or missing data\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
sps_info = match->data;
|
||||
|
||||
sps = devm_kzalloc(&pdev->dev, sizeof(*sps) +
|
||||
sps_info->num_domains * sizeof(sps->domains[0]),
|
||||
GFP_KERNEL);
|
||||
if (!sps)
|
||||
return -ENOMEM;
|
||||
|
||||
sps->base = of_io_request_and_map(pdev->dev.of_node, 0, "owl-sps");
|
||||
if (IS_ERR(sps->base)) {
|
||||
dev_err(&pdev->dev, "failed to map sps registers\n");
|
||||
return PTR_ERR(sps->base);
|
||||
}
|
||||
|
||||
sps->dev = &pdev->dev;
|
||||
sps->info = sps_info;
|
||||
sps->genpd_data.domains = sps->domains;
|
||||
sps->genpd_data.num_domains = sps_info->num_domains;
|
||||
|
||||
for (i = 0; i < sps_info->num_domains; i++) {
|
||||
ret = owl_sps_init_domain(sps, i);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = of_genpd_add_provider_onecell(pdev->dev.of_node, &sps->genpd_data);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to add provider (%d)", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct owl_sps_domain_info s500_sps_domains[] = {
|
||||
[S500_PD_VDE] = {
|
||||
.name = "VDE",
|
||||
.pwr_bit = 0,
|
||||
.ack_bit = 16,
|
||||
},
|
||||
[S500_PD_VCE_SI] = {
|
||||
.name = "VCE_SI",
|
||||
.pwr_bit = 1,
|
||||
.ack_bit = 17,
|
||||
},
|
||||
[S500_PD_USB2_1] = {
|
||||
.name = "USB2_1",
|
||||
.pwr_bit = 2,
|
||||
.ack_bit = 18,
|
||||
},
|
||||
[S500_PD_CPU2] = {
|
||||
.name = "CPU2",
|
||||
.pwr_bit = 5,
|
||||
.ack_bit = 21,
|
||||
.genpd_flags = GENPD_FLAG_ALWAYS_ON,
|
||||
},
|
||||
[S500_PD_CPU3] = {
|
||||
.name = "CPU3",
|
||||
.pwr_bit = 6,
|
||||
.ack_bit = 22,
|
||||
.genpd_flags = GENPD_FLAG_ALWAYS_ON,
|
||||
},
|
||||
[S500_PD_DMA] = {
|
||||
.name = "DMA",
|
||||
.pwr_bit = 8,
|
||||
.ack_bit = 12,
|
||||
},
|
||||
[S500_PD_DS] = {
|
||||
.name = "DS",
|
||||
.pwr_bit = 9,
|
||||
.ack_bit = 13,
|
||||
},
|
||||
[S500_PD_USB3] = {
|
||||
.name = "USB3",
|
||||
.pwr_bit = 10,
|
||||
.ack_bit = 14,
|
||||
},
|
||||
[S500_PD_USB2_0] = {
|
||||
.name = "USB2_0",
|
||||
.pwr_bit = 11,
|
||||
.ack_bit = 15,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct owl_sps_info s500_sps_info = {
|
||||
.num_domains = ARRAY_SIZE(s500_sps_domains),
|
||||
.domains = s500_sps_domains,
|
||||
};
|
||||
|
||||
static const struct of_device_id owl_sps_of_matches[] = {
|
||||
{ .compatible = "actions,s500-sps", .data = &s500_sps_info },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver owl_sps_platform_driver = {
|
||||
.probe = owl_sps_probe,
|
||||
.driver = {
|
||||
.name = "owl-sps",
|
||||
.of_match_table = owl_sps_of_matches,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init owl_sps_init(void)
|
||||
{
|
||||
return platform_driver_register(&owl_sps_platform_driver);
|
||||
}
|
||||
postcore_initcall(owl_sps_init);
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Andreas Färber
|
||||
*
|
||||
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
*/
|
||||
#ifndef DT_BINDINGS_POWER_OWL_S500_POWERGATE_H
|
||||
#define DT_BINDINGS_POWER_OWL_S500_POWERGATE_H
|
||||
|
||||
#define S500_PD_VDE 0
|
||||
#define S500_PD_VCE_SI 1
|
||||
#define S500_PD_USB2_1 2
|
||||
#define S500_PD_CPU2 3
|
||||
#define S500_PD_CPU3 4
|
||||
#define S500_PD_DMA 5
|
||||
#define S500_PD_DS 6
|
||||
#define S500_PD_USB3 7
|
||||
#define S500_PD_USB2_0 8
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Andreas Färber
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#ifndef SOC_ACTIONS_OWL_SPS_H
|
||||
#define SOC_ACTIONS_OWL_SPS_H
|
||||
|
||||
int owl_sps_set_pg(void __iomem *base, u32 pwr_mask, u32 ack_mask, bool enable);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue