arm64: locking: Replace ticket lock implementation with qspinlock
It's fair to say that our ticket lock has served us well over time, but it's time to bite the bullet and start using the generic qspinlock code so we can make use of explicit MCS queuing and potentially better PV performance in future. Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Will Deacon
parent
598865c5f3
commit
c11090474d
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@ -44,6 +44,7 @@ config ARM64
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select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
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select ARCH_USE_CMPXCHG_LOCKREF
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select ARCH_USE_QUEUED_RWLOCKS
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select ARCH_USE_QUEUED_SPINLOCKS
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select ARCH_SUPPORTS_MEMORY_FAILURE
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select ARCH_SUPPORTS_ATOMIC_RMW
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select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
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@ -16,6 +16,7 @@ generic-y += mm-arch-hooks.h
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generic-y += msi.h
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generic-y += preempt.h
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generic-y += qrwlock.h
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generic-y += qspinlock.h
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generic-y += rwsem.h
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generic-y += segment.h
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generic-y += serial.h
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@ -16,123 +16,8 @@
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#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#include <asm/lse.h>
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#include <asm/spinlock_types.h>
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#include <asm/processor.h>
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/*
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* Spinlock implementation.
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*
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* The memory barriers are implicit with the load-acquire and store-release
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* instructions.
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*/
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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unsigned int tmp;
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arch_spinlock_t lockval, newval;
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asm volatile(
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/* Atomically increment the next ticket. */
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ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" prfm pstl1strm, %3\n"
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"1: ldaxr %w0, %3\n"
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" add %w1, %w0, %w5\n"
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" stxr %w2, %w1, %3\n"
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" cbnz %w2, 1b\n",
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/* LSE atomics */
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" mov %w2, %w5\n"
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" ldadda %w2, %w0, %3\n"
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__nops(3)
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)
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/* Did we get the lock? */
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" eor %w1, %w0, %w0, ror #16\n"
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" cbz %w1, 3f\n"
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/*
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* No: spin on the owner. Send a local event to avoid missing an
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* unlock before the exclusive load.
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*/
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" sevl\n"
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"2: wfe\n"
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" ldaxrh %w2, %4\n"
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" eor %w1, %w2, %w0, lsr #16\n"
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" cbnz %w1, 2b\n"
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/* We got the lock. Critical section starts here. */
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"3:"
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: "=&r" (lockval), "=&r" (newval), "=&r" (tmp), "+Q" (*lock)
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: "Q" (lock->owner), "I" (1 << TICKET_SHIFT)
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: "memory");
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}
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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unsigned int tmp;
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arch_spinlock_t lockval;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" prfm pstl1strm, %2\n"
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"1: ldaxr %w0, %2\n"
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" eor %w1, %w0, %w0, ror #16\n"
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" cbnz %w1, 2f\n"
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" add %w0, %w0, %3\n"
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" stxr %w1, %w0, %2\n"
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" cbnz %w1, 1b\n"
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"2:",
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/* LSE atomics */
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" ldr %w0, %2\n"
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" eor %w1, %w0, %w0, ror #16\n"
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" cbnz %w1, 1f\n"
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" add %w1, %w0, %3\n"
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" casa %w0, %w1, %2\n"
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" sub %w1, %w1, %3\n"
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" eor %w1, %w1, %w0\n"
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"1:")
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: "=&r" (lockval), "=&r" (tmp), "+Q" (*lock)
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: "I" (1 << TICKET_SHIFT)
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: "memory");
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return !tmp;
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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unsigned long tmp;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" ldrh %w1, %0\n"
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" add %w1, %w1, #1\n"
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" stlrh %w1, %0",
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/* LSE atomics */
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" mov %w1, #1\n"
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" staddlh %w1, %0\n"
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__nops(1))
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: "=Q" (lock->owner), "=&r" (tmp)
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:
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: "memory");
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}
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static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
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{
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return lock.owner == lock.next;
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}
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static inline int arch_spin_is_locked(arch_spinlock_t *lock)
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{
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return !arch_spin_value_unlocked(READ_ONCE(*lock));
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}
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static inline int arch_spin_is_contended(arch_spinlock_t *lock)
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{
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arch_spinlock_t lockval = READ_ONCE(*lock);
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return (lockval.next - lockval.owner) > 1;
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}
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#define arch_spin_is_contended arch_spin_is_contended
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#include <asm/qrwlock.h>
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#include <asm/qspinlock.h>
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/* See include/linux/spinlock.h */
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#define smp_mb__after_spinlock() smp_mb()
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@ -20,22 +20,7 @@
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# error "please don't include this file directly"
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#endif
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#include <linux/types.h>
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#define TICKET_SHIFT 16
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typedef struct {
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#ifdef __AARCH64EB__
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u16 next;
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u16 owner;
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#else
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u16 owner;
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u16 next;
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#endif
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} __aligned(4) arch_spinlock_t;
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#define __ARCH_SPIN_LOCK_UNLOCKED { 0 , 0 }
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#include <asm-generic/qspinlock_types.h>
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#include <asm-generic/qrwlock_types.h>
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#endif
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