mediatek-drm maintainers and gamma correction
- add MAINTAINERS entry for mediatek-drm driver - add support for AAL and GAMMA engines - hook up gamma correction LUT - add support for temporal dithering to OD and GAMMA engines -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJXrXDqAAoJEFDCiBxwnmDrWFkP/RtEAKhOm5mzNksZb7FPv5Cd ngh/jN/9+q7JFoMstj/k9j0cUh3FOBQ2kh3AqKjH6R9PgZt9H9FGCgQWgVI7BNps yGZBSPogy3n+T9uZP0HTJRWXCnvaJbK5otNsmHmpdwHnXjUu6Li4aNDeg22MRiEI qQTE4UPm2Ry8FCRnQHYYXFMJFzYQQwWco5aq6Oja2YBvOunHuS/TcWQmW41kuPTc /V2XbF3Zx5RTfoOpBEvp5/tay3dKc2kE0FtggdzGBvJ4+b/Hx6c7ZvXH568C3nBw EqUC9+c3r/LA+KP3vALYF59gtt1ZzTsLB2sArGoo4UkNHNMjzqjjbANJDekezVhZ M8nbLgRWY/zF0u4/3xdr8t6VlPeUSUN85NW+8e2tN+CQu40crr/TRa7qB+JtNrLu 09SjQ9qKkByvGA27jrQmjF5xtqrnxnB0XDh1GiAiesMGeHXCBeserCHS6tsKhgMX aa4uhuMW1TeBHNvfmjYJ4Vrl2OlqOk84mCyTFjsByMfJAOav8QGepasmbtE000PZ 6IgtRn2E40Ml2zRBDOUm+B1EKLkJ5GGlwdkFTwBN15C7SDvobsdvKxN0KqLqbLhH mKBEepexdeNSYN7SpuXLXKyO+4JDaEW77qGy482D/0vUjvsogYhcCU6yvW53bOlQ QU7yz2Vm2oMdzhULwHrg =rl4u -----END PGP SIGNATURE----- Merge tag 'mediatek-drm-next-2016-08-12' of git://git.pengutronix.de/git/pza/linux into drm-next mediatek-drm maintainers and gamma correction - add MAINTAINERS entry for mediatek-drm driver - add support for AAL and GAMMA engines - hook up gamma correction LUT - add support for temporal dithering to OD and GAMMA engines * tag 'mediatek-drm-next-2016-08-12' of git://git.pengutronix.de/git/pza/linux: drm/mediatek: set mt8173 dithering function drm/mediatek: Add gamma correction. drm/mediatek: Add GAMMA engine basic function drm/mediatek: Add AAL engine basic function drm: mediatek: add Maintainers entry for Mediatek DRM drivers
This commit is contained in:
Dave Airlie
commit
c13eb9315f
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@ -4064,6 +4064,14 @@ S: Orphan / Obsolete
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F: drivers/gpu/drm/i810/
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F: include/uapi/drm/i810_drm.h
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DRM DRIVERS FOR MEDIATEK
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M: CK Hu <ck.hu@mediatek.com>
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M: Philipp Zabel <p.zabel@pengutronix.de>
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L: dri-devel@lists.freedesktop.org
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S: Supported
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F: drivers/gpu/drm/mediatek/
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F: Documentation/devicetree/bindings/display/mediatek/
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DRM DRIVER FOR MSM ADRENO GPU
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M: Rob Clark <robdclark@gmail.com>
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L: linux-arm-msm@vger.kernel.org
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@ -103,7 +103,8 @@ static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
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}
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static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w,
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unsigned int h, unsigned int vrefresh)
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unsigned int h, unsigned int vrefresh,
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unsigned int bpc)
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{
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if (w != 0 && h != 0)
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writel_relaxed(h << 16 | w, comp->regs + DISP_REG_OVL_ROI_SIZE);
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@ -106,7 +106,8 @@ static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
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}
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static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
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unsigned int height, unsigned int vrefresh)
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unsigned int height, unsigned int vrefresh,
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unsigned int bpc)
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{
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unsigned int threshold;
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unsigned int reg;
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@ -222,7 +222,9 @@ static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
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static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
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{
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struct drm_crtc *crtc = &mtk_crtc->base;
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unsigned int width, height, vrefresh;
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struct drm_connector *connector;
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struct drm_encoder *encoder;
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unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
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int ret;
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int i;
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@ -234,6 +236,19 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
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height = crtc->state->adjusted_mode.vdisplay;
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vrefresh = crtc->state->adjusted_mode.vrefresh;
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drm_for_each_encoder(encoder, crtc->dev) {
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if (encoder->crtc != crtc)
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continue;
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drm_for_each_connector(connector, crtc->dev) {
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if (connector->encoder != encoder)
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continue;
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if (connector->display_info.bpc != 0 &&
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bpc > connector->display_info.bpc)
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bpc = connector->display_info.bpc;
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}
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}
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ret = pm_runtime_get_sync(crtc->dev->dev);
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if (ret < 0) {
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DRM_ERROR("Failed to enable power domain: %d\n", ret);
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@ -266,7 +281,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
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for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
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struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
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mtk_ddp_comp_config(comp, width, height, vrefresh);
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mtk_ddp_comp_config(comp, width, height, vrefresh, bpc);
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mtk_ddp_comp_start(comp);
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}
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@ -409,6 +424,9 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
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}
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if (pending_planes)
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mtk_crtc->pending_planes = true;
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if (crtc->state->color_mgmt_changed)
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for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
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mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
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}
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static const struct drm_crtc_funcs mtk_crtc_funcs = {
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@ -418,6 +436,7 @@ static const struct drm_crtc_funcs mtk_crtc_funcs = {
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.reset = mtk_drm_crtc_reset,
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.atomic_duplicate_state = mtk_drm_crtc_duplicate_state,
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.atomic_destroy_state = mtk_drm_crtc_destroy_state,
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.gamma_set = drm_atomic_helper_legacy_gamma_set,
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};
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static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
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@ -464,7 +483,7 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl)
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if (state->pending_config) {
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mtk_ddp_comp_config(ovl, state->pending_width,
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state->pending_height,
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state->pending_vrefresh);
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state->pending_vrefresh, 0);
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state->pending_config = false;
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}
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@ -568,7 +587,8 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
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&mtk_crtc->planes[1].base, pipe);
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if (ret < 0)
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goto unprepare;
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drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);
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drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
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priv->crtc[pipe] = &mtk_crtc->base;
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priv->num_pipes++;
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@ -19,6 +19,9 @@
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#include "mtk_drm_plane.h"
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#define OVL_LAYER_NR 4
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#define MTK_LUT_SIZE 512
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#define MTK_MAX_BPC 10
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#define MTK_MIN_BPC 3
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int mtk_drm_crtc_enable_vblank(struct drm_device *drm, unsigned int pipe);
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void mtk_drm_crtc_disable_vblank(struct drm_device *drm, unsigned int pipe);
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@ -24,12 +24,17 @@
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#include "mtk_drm_drv.h"
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#include "mtk_drm_plane.h"
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#include "mtk_drm_ddp_comp.h"
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#include "mtk_drm_crtc.h"
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#define DISP_OD_EN 0x0000
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#define DISP_OD_INTEN 0x0008
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#define DISP_OD_INTSTA 0x000c
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#define DISP_OD_CFG 0x0020
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#define DISP_OD_SIZE 0x0030
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#define DISP_DITHER_5 0x0114
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#define DISP_DITHER_7 0x011c
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#define DISP_DITHER_15 0x013c
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#define DISP_DITHER_16 0x0140
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#define DISP_REG_UFO_START 0x0000
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@ -38,15 +43,69 @@
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#define DISP_COLOR_WIDTH 0x0c50
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#define DISP_COLOR_HEIGHT 0x0c54
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#define OD_RELAY_MODE BIT(0)
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#define DISP_AAL_EN 0x0000
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#define DISP_AAL_SIZE 0x0030
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#define UFO_BYPASS BIT(2)
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#define DISP_GAMMA_EN 0x0000
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#define DISP_GAMMA_CFG 0x0020
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#define DISP_GAMMA_SIZE 0x0030
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#define DISP_GAMMA_LUT 0x0700
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#define COLOR_BYPASS_ALL BIT(7)
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#define COLOR_SEQ_SEL BIT(13)
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#define LUT_10BIT_MASK 0x03ff
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#define COLOR_BYPASS_ALL BIT(7)
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#define COLOR_SEQ_SEL BIT(13)
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#define OD_RELAYMODE BIT(0)
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#define UFO_BYPASS BIT(2)
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#define AAL_EN BIT(0)
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#define GAMMA_EN BIT(0)
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#define GAMMA_LUT_EN BIT(1)
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#define DISP_DITHERING BIT(2)
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#define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
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#define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24)
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#define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
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#define DITHER_ADD_RSHIFT_R(x) (((x) & 0x7) << 16)
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#define DITHER_NEW_BIT_MODE BIT(0)
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#define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
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#define DITHER_OVFLW_BIT_B(x) (((x) & 0x7) << 24)
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#define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
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#define DITHER_ADD_RSHIFT_B(x) (((x) & 0x7) << 16)
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#define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
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#define DITHER_OVFLW_BIT_G(x) (((x) & 0x7) << 8)
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#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
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#define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0)
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void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc,
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unsigned int CFG)
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{
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/* If bpc equal to 0, the dithering function didn't be enabled */
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if (bpc == 0)
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return;
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if (bpc >= MTK_MIN_BPC) {
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writel(0, comp->regs + DISP_DITHER_5);
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writel(0, comp->regs + DISP_DITHER_7);
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writel(DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
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DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
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DITHER_NEW_BIT_MODE,
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comp->regs + DISP_DITHER_15);
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writel(DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
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DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
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DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
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DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
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comp->regs + DISP_DITHER_16);
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writel(DISP_DITHERING, comp->regs + CFG);
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}
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}
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static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,
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unsigned int h, unsigned int vrefresh)
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unsigned int h, unsigned int vrefresh,
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unsigned int bpc)
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{
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writel(w, comp->regs + DISP_COLOR_WIDTH);
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writel(h, comp->regs + DISP_COLOR_HEIGHT);
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@ -60,14 +119,16 @@ static void mtk_color_start(struct mtk_ddp_comp *comp)
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}
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static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
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unsigned int h, unsigned int vrefresh)
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unsigned int h, unsigned int vrefresh,
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unsigned int bpc)
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{
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writel(w << 16 | h, comp->regs + DISP_OD_SIZE);
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writel(OD_RELAYMODE, comp->regs + OD_RELAYMODE);
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mtk_dither_set(comp, bpc, DISP_OD_CFG);
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}
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static void mtk_od_start(struct mtk_ddp_comp *comp)
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{
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writel(OD_RELAY_MODE, comp->regs + DISP_OD_CFG);
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writel(1, comp->regs + DISP_OD_EN);
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}
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@ -76,6 +137,78 @@ static void mtk_ufoe_start(struct mtk_ddp_comp *comp)
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writel(UFO_BYPASS, comp->regs + DISP_REG_UFO_START);
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}
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static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
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unsigned int h, unsigned int vrefresh,
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unsigned int bpc)
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{
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writel(h << 16 | w, comp->regs + DISP_AAL_SIZE);
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}
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static void mtk_aal_start(struct mtk_ddp_comp *comp)
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{
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writel(AAL_EN, comp->regs + DISP_AAL_EN);
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}
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static void mtk_aal_stop(struct mtk_ddp_comp *comp)
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{
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writel_relaxed(0x0, comp->regs + DISP_AAL_EN);
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}
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static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
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unsigned int h, unsigned int vrefresh,
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unsigned int bpc)
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{
|
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writel(h << 16 | w, comp->regs + DISP_GAMMA_SIZE);
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mtk_dither_set(comp, bpc, DISP_GAMMA_CFG);
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}
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static void mtk_gamma_start(struct mtk_ddp_comp *comp)
|
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{
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writel(GAMMA_EN, comp->regs + DISP_GAMMA_EN);
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}
|
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|
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static void mtk_gamma_stop(struct mtk_ddp_comp *comp)
|
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{
|
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writel_relaxed(0x0, comp->regs + DISP_GAMMA_EN);
|
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}
|
||||
|
||||
static void mtk_gamma_set(struct mtk_ddp_comp *comp,
|
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struct drm_crtc_state *state)
|
||||
{
|
||||
unsigned int i, reg;
|
||||
struct drm_color_lut *lut;
|
||||
void __iomem *lut_base;
|
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u32 word;
|
||||
|
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if (state->gamma_lut) {
|
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reg = readl(comp->regs + DISP_GAMMA_CFG);
|
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reg = reg | GAMMA_LUT_EN;
|
||||
writel(reg, comp->regs + DISP_GAMMA_CFG);
|
||||
lut_base = comp->regs + DISP_GAMMA_LUT;
|
||||
lut = (struct drm_color_lut *)state->gamma_lut->data;
|
||||
for (i = 0; i < MTK_LUT_SIZE; i++) {
|
||||
word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) +
|
||||
(((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) +
|
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((lut[i].blue >> 6) & LUT_10BIT_MASK);
|
||||
writel(word, (lut_base + i * 4));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static const struct mtk_ddp_comp_funcs ddp_aal = {
|
||||
.gamma_set = mtk_gamma_set,
|
||||
.config = mtk_aal_config,
|
||||
.start = mtk_aal_start,
|
||||
.stop = mtk_aal_stop,
|
||||
};
|
||||
|
||||
static const struct mtk_ddp_comp_funcs ddp_gamma = {
|
||||
.gamma_set = mtk_gamma_set,
|
||||
.config = mtk_gamma_config,
|
||||
.start = mtk_gamma_start,
|
||||
.stop = mtk_gamma_stop,
|
||||
};
|
||||
|
||||
static const struct mtk_ddp_comp_funcs ddp_color = {
|
||||
.config = mtk_color_config,
|
||||
.start = mtk_color_start,
|
||||
|
|
@ -112,13 +245,13 @@ struct mtk_ddp_comp_match {
|
|||
};
|
||||
|
||||
static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
|
||||
[DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, NULL },
|
||||
[DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal },
|
||||
[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
|
||||
[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
|
||||
[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL },
|
||||
[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL },
|
||||
[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL },
|
||||
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, NULL },
|
||||
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
|
||||
[DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od },
|
||||
[DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL },
|
||||
[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL },
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@ struct device_node;
|
|||
struct drm_crtc;
|
||||
struct drm_device;
|
||||
struct mtk_plane_state;
|
||||
struct drm_crtc_state;
|
||||
|
||||
enum mtk_ddp_comp_type {
|
||||
MTK_DISP_OVL,
|
||||
|
|
@ -64,7 +65,7 @@ struct mtk_ddp_comp;
|
|||
|
||||
struct mtk_ddp_comp_funcs {
|
||||
void (*config)(struct mtk_ddp_comp *comp, unsigned int w,
|
||||
unsigned int h, unsigned int vrefresh);
|
||||
unsigned int h, unsigned int vrefresh, unsigned int bpc);
|
||||
void (*start)(struct mtk_ddp_comp *comp);
|
||||
void (*stop)(struct mtk_ddp_comp *comp);
|
||||
void (*enable_vblank)(struct mtk_ddp_comp *comp, struct drm_crtc *crtc);
|
||||
|
|
@ -73,6 +74,8 @@ struct mtk_ddp_comp_funcs {
|
|||
void (*layer_off)(struct mtk_ddp_comp *comp, unsigned int idx);
|
||||
void (*layer_config)(struct mtk_ddp_comp *comp, unsigned int idx,
|
||||
struct mtk_plane_state *state);
|
||||
void (*gamma_set)(struct mtk_ddp_comp *comp,
|
||||
struct drm_crtc_state *state);
|
||||
};
|
||||
|
||||
struct mtk_ddp_comp {
|
||||
|
|
@ -86,10 +89,10 @@ struct mtk_ddp_comp {
|
|||
|
||||
static inline void mtk_ddp_comp_config(struct mtk_ddp_comp *comp,
|
||||
unsigned int w, unsigned int h,
|
||||
unsigned int vrefresh)
|
||||
unsigned int vrefresh, unsigned int bpc)
|
||||
{
|
||||
if (comp->funcs && comp->funcs->config)
|
||||
comp->funcs->config(comp, w, h, vrefresh);
|
||||
comp->funcs->config(comp, w, h, vrefresh, bpc);
|
||||
}
|
||||
|
||||
static inline void mtk_ddp_comp_start(struct mtk_ddp_comp *comp)
|
||||
|
|
@ -139,6 +142,13 @@ static inline void mtk_ddp_comp_layer_config(struct mtk_ddp_comp *comp,
|
|||
comp->funcs->layer_config(comp, idx, state);
|
||||
}
|
||||
|
||||
static inline void mtk_ddp_gamma_set(struct mtk_ddp_comp *comp,
|
||||
struct drm_crtc_state *state)
|
||||
{
|
||||
if (comp->funcs && comp->funcs->gamma_set)
|
||||
comp->funcs->gamma_set(comp, state);
|
||||
}
|
||||
|
||||
int mtk_ddp_comp_get_id(struct device_node *node,
|
||||
enum mtk_ddp_comp_type comp_type);
|
||||
int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
|
||||
|
|
@ -146,5 +156,7 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
|
|||
const struct mtk_ddp_comp_funcs *funcs);
|
||||
int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp);
|
||||
void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp);
|
||||
void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc,
|
||||
unsigned int CFG);
|
||||
|
||||
#endif /* MTK_DRM_DDP_COMP_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue