clk: samsung: exynos4: add missing smmu_g2d clock and update comments
This patch adds missing smmu_g2d clock implementation and updates comment about Exynos4 clocks from 278-282 range. Those clocks are available on all Exynos4 SoC series, so the misleading comment has been removed. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
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c142543001
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@ -1183,6 +1183,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
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GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
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CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
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GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
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GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0),
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GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
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0),
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};
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@ -115,11 +115,11 @@
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#define CLK_SMMU_MFCR 275
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#define CLK_G3D 276
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#define CLK_G2D 277
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#define CLK_ROTATOR 278 /* Exynos4210 only */
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#define CLK_MDMA 279 /* Exynos4210 only */
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#define CLK_SMMU_G2D 280 /* Exynos4210 only */
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#define CLK_SMMU_ROTATOR 281 /* Exynos4210 only */
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#define CLK_SMMU_MDMA 282 /* Exynos4210 only */
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#define CLK_ROTATOR 278
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#define CLK_MDMA 279
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#define CLK_SMMU_G2D 280
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#define CLK_SMMU_ROTATOR 281
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#define CLK_SMMU_MDMA 282
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#define CLK_FIMD0 283
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#define CLK_MIE0 284
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#define CLK_MDNIE0 285 /* Exynos4412 only */
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