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drm/omap: move HDMI PLL calc function to pll.c 

Move hdmi_pll_compute(), used to calculate the config for HDMI PLL, from
hdmi_pll.c to pll.c, with the name of dss_pll_calc_b(), to make it
available to non-HDMI users.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Tomi Valkeinen 2016-05-18 10:45:20 +03:00
parent cd0715ffba
commit c17dc0e3a1
6 changed files with 67 additions and 64 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/omapdrm/dss/dss.h
View File

@ -441,6 +441,10 @@ bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
unsigned long pll_min, unsigned long pll_max,
dss_pll_calc_func func, void *data);
bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
unsigned long target_tmds, struct dss_pll_clock_info *cinfo);
int dss_pll_write_config_type_a(struct dss_pll *pll,
const struct dss_pll_clock_info *cinfo);
int dss_pll_write_config_type_b(struct dss_pll *pll,

2
drivers/gpu/drm/omapdrm/dss/hdmi.h
View File

@ -307,8 +307,6 @@ phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp);
/* HDMI PLL funcs */
void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
void hdmi_pll_compute(struct hdmi_pll_data *pll,
unsigned long target_tmds, struct dss_pll_clock_info *pi);
int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
struct hdmi_wp_data *wp);
void hdmi_pll_uninit(struct hdmi_pll_data *hpll);

3
drivers/gpu/drm/omapdrm/dss/hdmi4.c
View File

@ -186,7 +186,8 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
if (p->double_pixel)
pc *= 2;
hdmi_pll_compute(&hdmi.pll, pc, &hdmi_cinfo);
dss_pll_calc_b(&hdmi.pll.pll, clk_get_rate(hdmi.pll.pll.clkin),
pc, &hdmi_cinfo);
r = dss_pll_enable(&hdmi.pll.pll);
if (r) {

3
drivers/gpu/drm/omapdrm/dss/hdmi5.c
View File

@ -198,7 +198,8 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
if (p->double_pixel)
pc *= 2;
hdmi_pll_compute(&hdmi.pll, pc, &hdmi_cinfo);
dss_pll_calc_b(&hdmi.pll.pll, clk_get_rate(hdmi.pll.pll.clkin),
pc, &hdmi_cinfo);
/* disable and clear irqs */
hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);

60
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
View File

@ -39,66 +39,6 @@ void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
DUMPPLL(PLLCTRL_CFG4);
}
void hdmi_pll_compute(struct hdmi_pll_data *pll,
unsigned long target_tmds, struct dss_pll_clock_info *pi)
{
unsigned long fint, clkdco, clkout;
unsigned long target_bitclk, target_clkdco;
unsigned long min_dco;
unsigned n, m, mf, m2, sd;
unsigned long clkin;
const struct dss_pll_hw *hw = pll->pll.hw;
clkin = clk_get_rate(pll->pll.clkin);
DSSDBG("clkin %lu, target tmds %lu\n", clkin, target_tmds);
target_bitclk = target_tmds * 10;
/* Fint */
n = DIV_ROUND_UP(clkin, hw->fint_max);
fint = clkin / n;
/* adjust m2 so that the clkdco will be high enough */
min_dco = roundup(hw->clkdco_min, fint);
m2 = DIV_ROUND_UP(min_dco, target_bitclk);
if (m2 == 0)
m2 = 1;
target_clkdco = target_bitclk * m2;
m = target_clkdco / fint;
clkdco = fint * m;
/* adjust clkdco with fractional mf */
if (WARN_ON(target_clkdco - clkdco > fint))
mf = 0;
else
mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint);
if (mf > 0)
clkdco += (u32)div_u64((u64)mf * fint, 262144);
clkout = clkdco / m2;
/* sigma-delta */
sd = DIV_ROUND_UP(fint * m, 250000000);
DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n",
n, m, mf, m2, sd);
DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout);
pi->n = n;
pi->m = m;
pi->mf = mf;
pi->mX[0] = m2;
pi->sd = sd;
pi->fint = fint;
pi->clkdco = clkdco;
pi->clkout[0] = clkout;
}
static int hdmi_pll_enable(struct dss_pll *dsspll)
{
struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);

59
drivers/gpu/drm/omapdrm/dss/pll.c
View File

@ -248,6 +248,65 @@ bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
return false;
}
bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
unsigned long target_tmds, struct dss_pll_clock_info *cinfo)
{
unsigned long fint, clkdco, clkout;
unsigned long target_bitclk, target_clkdco;
unsigned long min_dco;
unsigned n, m, mf, m2, sd;
const struct dss_pll_hw *hw = pll->hw;
DSSDBG("clkin %lu, target tmds %lu\n", clkin, target_tmds);
target_bitclk = target_tmds * 10;
/* Fint */
n = DIV_ROUND_UP(clkin, hw->fint_max);
fint = clkin / n;
/* adjust m2 so that the clkdco will be high enough */
min_dco = roundup(hw->clkdco_min, fint);
m2 = DIV_ROUND_UP(min_dco, target_bitclk);
if (m2 == 0)
m2 = 1;
target_clkdco = target_bitclk * m2;
m = target_clkdco / fint;
clkdco = fint * m;
/* adjust clkdco with fractional mf */
if (WARN_ON(target_clkdco - clkdco > fint))
mf = 0;
else
mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint);
if (mf > 0)
clkdco += (u32)div_u64((u64)mf * fint, 262144);
clkout = clkdco / m2;
/* sigma-delta */
sd = DIV_ROUND_UP(fint * m, 250000000);
DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n",
n, m, mf, m2, sd);
DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout);
cinfo->n = n;
cinfo->m = m;
cinfo->mf = mf;
cinfo->mX[0] = m2;
cinfo->sd = sd;
cinfo->fint = fint;
cinfo->clkdco = clkdco;
cinfo->clkout[0] = clkout;
return true;
}
static int wait_for_bit_change(void __iomem *reg, int bitnum, int value)
{
unsigned long timeout;