pci-v4.11-fixes-4
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commit
c2eb7beac7
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@ -89,6 +89,7 @@ config PCI_HISI
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIEPORTBUS
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select PCIE_DW_HOST
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select PCI_HOST_COMMON
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help
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Say Y here if you want PCIe controller support on HiSilicon
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Hip05 and Hip06 SoCs
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@ -234,6 +234,9 @@ static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
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return 0;
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}
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static const struct dw_pcie_ops dw_pcie_ops = {
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};
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static int artpec6_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@ -252,6 +255,7 @@ static int artpec6_pcie_probe(struct platform_device *pdev)
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return -ENOMEM;
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pci->dev = dev;
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pci->ops = &dw_pcie_ops;
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artpec6_pcie->pci = pci;
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@ -86,6 +86,9 @@ static int dw_plat_add_pcie_port(struct pcie_port *pp,
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return 0;
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}
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static const struct dw_pcie_ops dw_pcie_ops = {
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};
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static int dw_plat_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@ -103,6 +106,7 @@ static int dw_plat_pcie_probe(struct platform_device *pdev)
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return -ENOMEM;
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pci->dev = dev;
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pci->ops = &dw_pcie_ops;
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dw_plat_pcie->pci = pci;
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@ -375,7 +375,6 @@ static void thunder_pem_legacy_fw(struct acpi_pci_root *root,
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index -= node * PEM_MAX_DOM_IN_NODE;
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res_pem->start = PEM_RES_BASE | FIELD_PREP(PEM_NODE_MASK, node) |
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FIELD_PREP(PEM_INDX_MASK, index);
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res_pem->end = res_pem->start + SZ_16M - 1;
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res_pem->flags = IORESOURCE_MEM;
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}
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@ -399,8 +398,15 @@ static int thunder_pem_acpi_init(struct pci_config_window *cfg)
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*/
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if (ret) {
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thunder_pem_legacy_fw(root, res_pem);
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/* Reserve PEM-specific resources and PCI configuration space */
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/*
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* Reserve 64K size PEM specific resources. The full 16M range
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* size is required for thunder_pem_init() call.
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*/
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res_pem->end = res_pem->start + SZ_64K - 1;
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thunder_pem_reserve_range(dev, root->segment, res_pem);
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res_pem->end = res_pem->start + SZ_16M - 1;
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/* Reserve PCI configuration space as well. */
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thunder_pem_reserve_range(dev, root->segment, &cfg->res);
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}
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