UniPhier ARM64 SoC DT updates for v4.14 (2nd)
- add reset controller node of analog amplifier - add AIDET irqchip device nodes - fix size of sdctrl node - support new SoC PXs3 and its reference development board -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZpDOFAAoJED2LAQed4NsGJ00P/0Y6jAaPwpUjrsqvNEYYD8cr doLGQz5/tQmTPdNSM9rbqKeIoEQcm0tJGlrEZg5n1lrdlTrifQwsHC1SWM7xw8GD Qjv8Euyi84aj11uSgnU7jvlC5Rm1UZKt8M4PY2uhOS9FZFzHr7KMjqVHDN2CLh63 39j5XRL+S+cqfLSyIV+ThsqVkTv6NBschZyWiDJeYRlVzeKXPhtbiOBi+9eNL74T 2Sd0d6wsWdXkhS5z6rWD8KMj9ozPM566Hf52Dq3h8nIDsGQD//yFPv+pIf/Bpgxp US9o1yag+zmPBy/I9l3p7p3H+1xRvVn7EnUH2rVe+rloUW9aDGZdcIWuTksxtdpS 52kBM82LOm1JCa5Xr1L/lHhT+gdF/Jhnx21eCS94cLSMQPEtT2bNGbOgY3CwtcOx Aci+tLhVH3w4K1I5Lkebc/RJOUc0cmHNX1nk+x7sol94FfeBO+RizmKPu6B2DZOH uzsQoIHfAyAye8MmYVAKkHldybq72Wr9OFjbOQFke662EMLIVWeix9kVBC0yoML7 9KrsOlB4Hcjm5ZtyqCfuL6+/560fYk7sZmqSM+Al8jTkstsYZjz7S2vV8encqiYb L+okYF8fmUmAeN5RB3hKu3mD/KwSucX+VGAUmuLz4BTZksKdxH6C2dCtf9rC/epC wqsK9t78KRc+wZp7YsLW =uOTL -----END PGP SIGNATURE----- Merge tag 'uniphier-dt64-v4.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt64 UniPhier ARM64 SoC DT updates for v4.14 (2nd) - add reset controller node of analog amplifier - add AIDET irqchip device nodes - fix size of sdctrl node - support new SoC PXs3 and its reference development board * tag 'uniphier-dt64-v4.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier: arm64: dts: uniphier: add PXs3 SoC support arm64: dts: uniphier: fix size of sdctrl node arm64: dts: uniphier: add AIDET nodes arm64: dts: uniphier: add reset controller node of analog amplifier Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
c338aa5deb
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@ -2,7 +2,8 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
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uniphier-ld11-global.dtb \
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uniphier-ld11-ref.dtb \
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uniphier-ld20-global.dtb \
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uniphier-ld20-ref.dtb
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uniphier-ld20-ref.dtb \
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uniphier-pxs3-ref.dtb
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always := $(dtb-y)
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clean-files := *.dtb
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@ -150,6 +150,17 @@ serial3: serial@54006b00 {
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clocks = <&peri_clk 3>;
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};
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adamv@57920000 {
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compatible = "socionext,uniphier-ld11-adamv",
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"simple-mfd", "syscon";
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reg = <0x57920000 0x1000>;
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adamv_rst: reset {
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compatible = "socionext,uniphier-ld11-adamv-reset";
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#reset-cells = <1>;
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};
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};
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i2c0: i2c@58780000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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@ -344,6 +355,13 @@ pinctrl: pinctrl {
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};
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};
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aidet: aidet@5fc20000 {
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compatible = "socionext,uniphier-ld11-aidet";
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reg = <0x5fc20000 0x200>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gic: interrupt-controller@5fe00000 {
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compatible = "arm,gic-v3";
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reg = <0x5fe00000 0x10000>, /* GICD */
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@ -219,6 +219,17 @@ serial3: serial@54006b00 {
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clocks = <&peri_clk 3>;
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};
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adamv@57920000 {
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compatible = "socionext,uniphier-ld20-adamv",
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"simple-mfd", "syscon";
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reg = <0x57920000 0x1000>;
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adamv_rst: reset {
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compatible = "socionext,uniphier-ld20-adamv-reset";
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#reset-cells = <1>;
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};
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};
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i2c0: i2c@58780000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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@ -309,7 +320,7 @@ smpctrl@59801000 {
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sdctrl@59810000 {
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compatible = "socionext,uniphier-ld20-sdctrl",
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"simple-mfd", "syscon";
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reg = <0x59810000 0x800>;
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reg = <0x59810000 0x400>;
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sd_clk: clock {
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compatible = "socionext,uniphier-ld20-sd-clock";
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@ -365,6 +376,13 @@ pinctrl: pinctrl {
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};
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};
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aidet: aidet@5fc20000 {
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compatible = "socionext,uniphier-ld20-aidet";
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reg = <0x5fc20000 0x200>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gic: interrupt-controller@5fe00000 {
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compatible = "arm,gic-v3";
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reg = <0x5fe00000 0x10000>, /* GICD */
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@ -0,0 +1,62 @@
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/*
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* Device Tree Source for UniPhier PXs3 Reference Board
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*
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* Copyright (C) 2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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/dts-v1/;
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#include "uniphier-pxs3.dtsi"
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#include "uniphier-support-card.dtsi"
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/ {
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model = "UniPhier PXs3 Reference Board";
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compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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serial2 = &serial2;
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serial3 = &serial3;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c6 = &i2c6;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0 0x80000000 0 0xa0000000>;
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};
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};
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ðsc {
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interrupts = <0 52 4>;
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};
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&serial0 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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};
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&i2c2 {
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status = "okay";
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};
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&i2c3 {
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status = "okay";
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};
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@ -0,0 +1,367 @@
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/*
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* Device Tree Source for UniPhier PXs3 SoC
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*
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* Copyright (C) 2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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/memreserve/ 0x80000000 0x02000000;
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/ {
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compatible = "socionext,uniphier-pxs3";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x000>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x001>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x002>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x003>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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operating-points-v2 = <&cluster0_opp>;
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};
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};
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cluster0_opp: opp_table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-250000000 {
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opp-hz = /bits/ 64 <250000000>;
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clock-latency-ns = <300>;
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};
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opp-325000000 {
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opp-hz = /bits/ 64 <325000000>;
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clock-latency-ns = <300>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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clock-latency-ns = <300>;
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};
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opp-650000000 {
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opp-hz = /bits/ 64 <650000000>;
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clock-latency-ns = <300>;
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};
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opp-666667000 {
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opp-hz = /bits/ 64 <666667000>;
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clock-latency-ns = <300>;
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};
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opp-866667000 {
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opp-hz = /bits/ 64 <866667000>;
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clock-latency-ns = <300>;
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};
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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clock-latency-ns = <300>;
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};
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opp-1300000000 {
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opp-hz = /bits/ 64 <1300000000>;
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clock-latency-ns = <300>;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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clocks {
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refclk: ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 4>,
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<1 14 4>,
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<1 11 4>,
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<1 10 4>;
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006800 0x40>;
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interrupts = <0 33 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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clocks = <&peri_clk 0>;
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};
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serial1: serial@54006900 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006900 0x40>;
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interrupts = <0 35 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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clocks = <&peri_clk 1>;
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};
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serial2: serial@54006a00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006a00 0x40>;
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interrupts = <0 37 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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clocks = <&peri_clk 2>;
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};
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serial3: serial@54006b00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006b00 0x40>;
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interrupts = <0 177 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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clocks = <&peri_clk 3>;
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};
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i2c0: i2c@58780000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58780000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 41 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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clocks = <&peri_clk 4>;
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clock-frequency = <100000>;
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};
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i2c1: i2c@58781000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58781000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 42 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clocks = <&peri_clk 5>;
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clock-frequency = <100000>;
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};
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i2c2: i2c@58782000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58782000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 43 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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clocks = <&peri_clk 6>;
|
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clock-frequency = <100000>;
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||||
};
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i2c3: i2c@58783000 {
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compatible = "socionext,uniphier-fi2c";
|
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status = "disabled";
|
||||
reg = <0x58783000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
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interrupts = <0 44 4>;
|
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pinctrl-names = "default";
|
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pinctrl-0 = <&pinctrl_i2c3>;
|
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clocks = <&peri_clk 7>;
|
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clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
/* chip-internal connection for HDMI */
|
||||
i2c6: i2c@58786000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
reg = <0x58786000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 26 4>;
|
||||
clocks = <&peri_clk 10>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
system_bus: system-bus@58c00000 {
|
||||
compatible = "socionext,uniphier-system-bus";
|
||||
status = "disabled";
|
||||
reg = <0x58c00000 0x400>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_system_bus>;
|
||||
};
|
||||
|
||||
smpctrl@59801000 {
|
||||
compatible = "socionext,uniphier-smpctrl";
|
||||
reg = <0x59801000 0x400>;
|
||||
};
|
||||
|
||||
sdctrl@59810000 {
|
||||
compatible = "socionext,uniphier-pxs3-sdctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59810000 0x400>;
|
||||
|
||||
sd_clk: clock {
|
||||
compatible = "socionext,uniphier-pxs3-sd-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sd_rst: reset {
|
||||
compatible = "socionext,uniphier-pxs3-sd-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
perictrl@59820000 {
|
||||
compatible = "socionext,uniphier-pxs3-perictrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x59820000 0x200>;
|
||||
|
||||
peri_clk: clock {
|
||||
compatible = "socionext,uniphier-pxs3-peri-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
peri_rst: reset {
|
||||
compatible = "socionext,uniphier-pxs3-peri-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
emmc: sdhc@5a000000 {
|
||||
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
|
||||
reg = <0x5a000000 0x400>;
|
||||
interrupts = <0 78 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_emmc>;
|
||||
clocks = <&sys_clk 4>;
|
||||
bus-width = <8>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
cdns,phy-input-delay-legacy = <4>;
|
||||
cdns,phy-input-delay-mmc-highspeed = <2>;
|
||||
cdns,phy-input-delay-mmc-ddr = <3>;
|
||||
cdns,phy-dll-delay-sdclk = <21>;
|
||||
cdns,phy-dll-delay-sdclk-hsmmc = <21>;
|
||||
};
|
||||
|
||||
soc-glue@5f800000 {
|
||||
compatible = "socionext,uniphier-pxs3-soc-glue",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x5f800000 0x2000>;
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "socionext,uniphier-pxs3-pinctrl";
|
||||
};
|
||||
};
|
||||
|
||||
aidet: aidet@5fc20000 {
|
||||
compatible = "socionext,uniphier-pxs3-aidet";
|
||||
reg = <0x5fc20000 0x200>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@5fe00000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x5fe00000 0x10000>, /* GICD */
|
||||
<0x5fe80000 0x80000>; /* GICR */
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupts = <1 9 4>;
|
||||
};
|
||||
|
||||
sysctrl@61840000 {
|
||||
compatible = "socionext,uniphier-pxs3-sysctrl",
|
||||
"simple-mfd", "syscon";
|
||||
reg = <0x61840000 0x10000>;
|
||||
|
||||
sys_clk: clock {
|
||||
compatible = "socionext,uniphier-pxs3-clock";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sys_rst: reset {
|
||||
compatible = "socionext,uniphier-pxs3-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "socionext,uniphier-wdt";
|
||||
};
|
||||
};
|
||||
|
||||
nand: nand@68000000 {
|
||||
compatible = "socionext,uniphier-denali-nand-v5b";
|
||||
status = "disabled";
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
||||
interrupts = <0 65 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand>;
|
||||
clocks = <&sys_clk 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "uniphier-pinctrl.dtsi"
|
||||
Loading…
Reference in New Issue