[media] smiapp-pll: The clock tree values are unsigned --- fix debug prints
These values are unsigned, so use %u instead of %d. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
This commit is contained in:
Sakari Ailus
Mauro Carvalho Chehab
parent
bc47150ab9
commit
c37f9bf919
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@ -65,26 +65,26 @@ static int bounds_check(struct device *dev, uint32_t val,
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static void print_pll(struct device *dev, struct smiapp_pll *pll)
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{
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dev_dbg(dev, "pre_pll_clk_div\t%d\n", pll->pre_pll_clk_div);
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dev_dbg(dev, "pll_multiplier \t%d\n", pll->pll_multiplier);
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dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->pre_pll_clk_div);
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dev_dbg(dev, "pll_multiplier \t%u\n", pll->pll_multiplier);
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if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) {
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dev_dbg(dev, "op_sys_clk_div \t%d\n", pll->op_sys_clk_div);
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dev_dbg(dev, "op_pix_clk_div \t%d\n", pll->op_pix_clk_div);
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dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op_sys_clk_div);
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dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op_pix_clk_div);
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}
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dev_dbg(dev, "vt_sys_clk_div \t%d\n", pll->vt_sys_clk_div);
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dev_dbg(dev, "vt_pix_clk_div \t%d\n", pll->vt_pix_clk_div);
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dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt_sys_clk_div);
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dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt_pix_clk_div);
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dev_dbg(dev, "ext_clk_freq_hz \t%d\n", pll->ext_clk_freq_hz);
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dev_dbg(dev, "pll_ip_clk_freq_hz \t%d\n", pll->pll_ip_clk_freq_hz);
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dev_dbg(dev, "pll_op_clk_freq_hz \t%d\n", pll->pll_op_clk_freq_hz);
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dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz);
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dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->pll_ip_clk_freq_hz);
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dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->pll_op_clk_freq_hz);
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if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) {
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dev_dbg(dev, "op_sys_clk_freq_hz \t%d\n",
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dev_dbg(dev, "op_sys_clk_freq_hz \t%u\n",
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pll->op_sys_clk_freq_hz);
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dev_dbg(dev, "op_pix_clk_freq_hz \t%d\n",
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dev_dbg(dev, "op_pix_clk_freq_hz \t%u\n",
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pll->op_pix_clk_freq_hz);
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}
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dev_dbg(dev, "vt_sys_clk_freq_hz \t%d\n", pll->vt_sys_clk_freq_hz);
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dev_dbg(dev, "vt_pix_clk_freq_hz \t%d\n", pll->vt_pix_clk_freq_hz);
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dev_dbg(dev, "vt_sys_clk_freq_hz \t%u\n", pll->vt_sys_clk_freq_hz);
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dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt_pix_clk_freq_hz);
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}
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/*
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@ -123,11 +123,11 @@ static int __smiapp_pll_calculate(struct device *dev,
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* Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be
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* too high.
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*/
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dev_dbg(dev, "pre_pll_clk_div %d\n", pll->pre_pll_clk_div);
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dev_dbg(dev, "pre_pll_clk_div %u\n", pll->pre_pll_clk_div);
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/* Don't go above max pll multiplier. */
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more_mul_max = limits->max_pll_multiplier / mul;
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dev_dbg(dev, "more_mul_max: max_pll_multiplier check: %d\n",
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dev_dbg(dev, "more_mul_max: max_pll_multiplier check: %u\n",
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more_mul_max);
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/* Don't go above max pll op frequency. */
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more_mul_max =
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@ -135,30 +135,30 @@ static int __smiapp_pll_calculate(struct device *dev,
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more_mul_max,
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limits->max_pll_op_freq_hz
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/ (pll->ext_clk_freq_hz / pll->pre_pll_clk_div * mul));
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dev_dbg(dev, "more_mul_max: max_pll_op_freq_hz check: %d\n",
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dev_dbg(dev, "more_mul_max: max_pll_op_freq_hz check: %u\n",
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more_mul_max);
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/* Don't go above the division capability of op sys clock divider. */
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more_mul_max = min(more_mul_max,
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limits->op.max_sys_clk_div * pll->pre_pll_clk_div
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/ div);
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dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %d\n",
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dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n",
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more_mul_max);
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/* Ensure we won't go above min_pll_multiplier. */
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more_mul_max = min(more_mul_max,
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DIV_ROUND_UP(limits->max_pll_multiplier, mul));
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dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %d\n",
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dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n",
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more_mul_max);
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/* Ensure we won't go below min_pll_op_freq_hz. */
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more_mul_min = DIV_ROUND_UP(limits->min_pll_op_freq_hz,
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pll->ext_clk_freq_hz / pll->pre_pll_clk_div
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* mul);
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dev_dbg(dev, "more_mul_min: min_pll_op_freq_hz check: %d\n",
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dev_dbg(dev, "more_mul_min: min_pll_op_freq_hz check: %u\n",
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more_mul_min);
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/* Ensure we won't go below min_pll_multiplier. */
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more_mul_min = max(more_mul_min,
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DIV_ROUND_UP(limits->min_pll_multiplier, mul));
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dev_dbg(dev, "more_mul_min: min_pll_multiplier check: %d\n",
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dev_dbg(dev, "more_mul_min: min_pll_multiplier check: %u\n",
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more_mul_min);
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if (more_mul_min > more_mul_max) {
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@ -168,23 +168,23 @@ static int __smiapp_pll_calculate(struct device *dev,
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}
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more_mul_factor = lcm(div, pll->pre_pll_clk_div) / div;
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dev_dbg(dev, "more_mul_factor: %d\n", more_mul_factor);
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dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor);
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more_mul_factor = lcm(more_mul_factor, limits->op.min_sys_clk_div);
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dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n",
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dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %u\n",
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more_mul_factor);
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i = roundup(more_mul_min, more_mul_factor);
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if (!is_one_or_even(i))
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i <<= 1;
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dev_dbg(dev, "final more_mul: %d\n", i);
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dev_dbg(dev, "final more_mul: %u\n", i);
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if (i > more_mul_max) {
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dev_dbg(dev, "final more_mul is bad, max %d\n", more_mul_max);
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dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max);
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return -EINVAL;
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}
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pll->pll_multiplier = mul * i;
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pll->op_sys_clk_div = div * i / pll->pre_pll_clk_div;
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dev_dbg(dev, "op_sys_clk_div: %d\n", pll->op_sys_clk_div);
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dev_dbg(dev, "op_sys_clk_div: %u\n", pll->op_sys_clk_div);
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pll->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz
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/ pll->pre_pll_clk_div;
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@ -197,7 +197,7 @@ static int __smiapp_pll_calculate(struct device *dev,
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pll->pll_op_clk_freq_hz / pll->op_sys_clk_div;
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pll->op_pix_clk_div = pll->bits_per_pixel;
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dev_dbg(dev, "op_pix_clk_div: %d\n", pll->op_pix_clk_div);
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dev_dbg(dev, "op_pix_clk_div: %u\n", pll->op_pix_clk_div);
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pll->op_pix_clk_freq_hz =
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pll->op_sys_clk_freq_hz / pll->op_pix_clk_div;
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@ -214,7 +214,7 @@ static int __smiapp_pll_calculate(struct device *dev,
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vt_op_binning_div = pll->binning_horizontal;
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else
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vt_op_binning_div = 1;
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dev_dbg(dev, "vt_op_binning_div: %d\n", vt_op_binning_div);
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dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div);
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/*
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* Profile 2 supports vt_pix_clk_div E [4, 10]
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@ -227,30 +227,30 @@ static int __smiapp_pll_calculate(struct device *dev,
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*
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* Find absolute limits for the factor of vt divider.
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*/
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dev_dbg(dev, "scale_m: %d\n", pll->scale_m);
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dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
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min_vt_div = DIV_ROUND_UP(pll->op_pix_clk_div * pll->op_sys_clk_div
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* pll->scale_n,
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lane_op_clock_ratio * vt_op_binning_div
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* pll->scale_m);
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/* Find smallest and biggest allowed vt divisor. */
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dev_dbg(dev, "min_vt_div: %d\n", min_vt_div);
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dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
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min_vt_div = max(min_vt_div,
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DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
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limits->vt.max_pix_clk_freq_hz));
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dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %d\n",
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dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n",
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min_vt_div);
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min_vt_div = max_t(uint32_t, min_vt_div,
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limits->vt.min_pix_clk_div
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* limits->vt.min_sys_clk_div);
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dev_dbg(dev, "min_vt_div: min_vt_clk_div: %d\n", min_vt_div);
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dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div);
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max_vt_div = limits->vt.max_sys_clk_div * limits->vt.max_pix_clk_div;
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dev_dbg(dev, "max_vt_div: %d\n", max_vt_div);
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dev_dbg(dev, "max_vt_div: %u\n", max_vt_div);
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max_vt_div = min(max_vt_div,
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DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
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limits->vt.min_pix_clk_freq_hz));
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dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %d\n",
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dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n",
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max_vt_div);
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/*
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@ -258,28 +258,28 @@ static int __smiapp_pll_calculate(struct device *dev,
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* with all values of pix_clk_div.
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*/
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min_sys_div = limits->vt.min_sys_clk_div;
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dev_dbg(dev, "min_sys_div: %d\n", min_sys_div);
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dev_dbg(dev, "min_sys_div: %u\n", min_sys_div);
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min_sys_div = max(min_sys_div,
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DIV_ROUND_UP(min_vt_div,
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limits->vt.max_pix_clk_div));
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dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %d\n", min_sys_div);
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dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div);
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min_sys_div = max(min_sys_div,
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pll->pll_op_clk_freq_hz
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/ limits->vt.max_sys_clk_freq_hz);
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dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %d\n", min_sys_div);
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dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div);
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min_sys_div = clk_div_even_up(min_sys_div);
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dev_dbg(dev, "min_sys_div: one or even: %d\n", min_sys_div);
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dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div);
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max_sys_div = limits->vt.max_sys_clk_div;
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dev_dbg(dev, "max_sys_div: %d\n", max_sys_div);
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dev_dbg(dev, "max_sys_div: %u\n", max_sys_div);
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max_sys_div = min(max_sys_div,
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DIV_ROUND_UP(max_vt_div,
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limits->vt.min_pix_clk_div));
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dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %d\n", max_sys_div);
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dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div);
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max_sys_div = min(max_sys_div,
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DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
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limits->vt.min_pix_clk_freq_hz));
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dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %d\n", max_sys_div);
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dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div);
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/*
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* Find pix_div such that a legal pix_div * sys_div results
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@ -296,7 +296,7 @@ static int __smiapp_pll_calculate(struct device *dev,
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if (pix_div < limits->vt.min_pix_clk_div
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|| pix_div > limits->vt.max_pix_clk_div) {
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dev_dbg(dev,
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"pix_div %d too small or too big (%d--%d)\n",
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"pix_div %u too small or too big (%u--%u)\n",
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pix_div,
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limits->vt.min_pix_clk_div,
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limits->vt.max_pix_clk_div);
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@ -390,9 +390,9 @@ int smiapp_pll_calculate(struct device *dev,
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lane_op_clock_ratio = pll->csi2.lanes;
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else
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lane_op_clock_ratio = 1;
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dev_dbg(dev, "lane_op_clock_ratio: %d\n", lane_op_clock_ratio);
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dev_dbg(dev, "lane_op_clock_ratio: %u\n", lane_op_clock_ratio);
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dev_dbg(dev, "binning: %dx%d\n", pll->binning_horizontal,
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dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal,
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pll->binning_vertical);
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switch (pll->bus_type) {
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@ -411,7 +411,7 @@ int smiapp_pll_calculate(struct device *dev,
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}
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/* Figure out limits for pre-pll divider based on extclk */
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dev_dbg(dev, "min / max pre_pll_clk_div: %d / %d\n",
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dev_dbg(dev, "min / max pre_pll_clk_div: %u / %u\n",
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limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);
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max_pre_pll_clk_div =
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min_t(uint16_t, limits->max_pre_pll_clk_div,
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@ -422,20 +422,20 @@ int smiapp_pll_calculate(struct device *dev,
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clk_div_even_up(
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DIV_ROUND_UP(pll->ext_clk_freq_hz,
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limits->max_pll_ip_freq_hz)));
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dev_dbg(dev, "pre-pll check: min / max pre_pll_clk_div: %d / %d\n",
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dev_dbg(dev, "pre-pll check: min / max pre_pll_clk_div: %u / %u\n",
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min_pre_pll_clk_div, max_pre_pll_clk_div);
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i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);
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mul = div_u64(pll->pll_op_clk_freq_hz, i);
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div = pll->ext_clk_freq_hz / i;
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dev_dbg(dev, "mul %d / div %d\n", mul, div);
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dev_dbg(dev, "mul %u / div %u\n", mul, div);
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min_pre_pll_clk_div =
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max_t(uint16_t, min_pre_pll_clk_div,
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clk_div_even_up(
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DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,
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limits->max_pll_op_freq_hz)));
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dev_dbg(dev, "pll_op check: min / max pre_pll_clk_div: %d / %d\n",
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dev_dbg(dev, "pll_op check: min / max pre_pll_clk_div: %u / %u\n",
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min_pre_pll_clk_div, max_pre_pll_clk_div);
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for (pll->pre_pll_clk_div = min_pre_pll_clk_div;
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