spi: spi-mem: add stm32 qspi controller
The qspi controller is a specialized communication interface targeting single, dual or quad SPI Flash memories (NOR/NAND). It can operate in any of the following modes: -indirect mode: all the operations are performed using the quadspi registers -read memory-mapped mode: the external Flash memory is mapped to the microcontroller address space and is seen by the system as if it was an internal memory tested on: -NOR: mx66l51235l -NAND: MT29F2G01ABAGD Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Ludovic Barre
Mark Brown
parent
c3e6845ea0
commit
c530cd1d9d
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@ -647,6 +647,15 @@ config SPI_STM32
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is not available, the driver automatically falls back to
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PIO mode.
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config SPI_STM32_QSPI
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tristate "STMicroelectronics STM32 QUAD SPI controller"
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depends on ARCH_STM32 || COMPILE_TEST
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depends on OF
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help
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This enables support for the Quad SPI controller in master mode.
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This driver does not support generic SPI. The implementation only
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supports spi-mem interface.
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config SPI_ST_SSC4
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tristate "STMicroelectronics SPI SSC-based driver"
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depends on ARCH_STI || COMPILE_TEST
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@ -94,6 +94,7 @@ obj-$(CONFIG_SPI_SLAVE_MT27XX) += spi-slave-mt27xx.o
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obj-$(CONFIG_SPI_SPRD) += spi-sprd.o
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obj-$(CONFIG_SPI_SPRD_ADI) += spi-sprd-adi.o
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obj-$(CONFIG_SPI_STM32) += spi-stm32.o
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obj-$(CONFIG_SPI_STM32_QSPI) += spi-stm32-qspi.o
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obj-$(CONFIG_SPI_ST_SSC4) += spi-st-ssc4.o
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obj-$(CONFIG_SPI_SUN4I) += spi-sun4i.o
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obj-$(CONFIG_SPI_SUN6I) += spi-sun6i.o
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@ -0,0 +1,512 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
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* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/sizes.h>
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#include <linux/spi/spi-mem.h>
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#define QSPI_CR 0x00
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#define CR_EN BIT(0)
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#define CR_ABORT BIT(1)
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#define CR_DMAEN BIT(2)
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#define CR_TCEN BIT(3)
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#define CR_SSHIFT BIT(4)
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#define CR_DFM BIT(6)
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#define CR_FSEL BIT(7)
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#define CR_FTHRES_MASK GENMASK(12, 8)
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#define CR_TEIE BIT(16)
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#define CR_TCIE BIT(17)
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#define CR_FTIE BIT(18)
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#define CR_SMIE BIT(19)
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#define CR_TOIE BIT(20)
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#define CR_PRESC_MASK GENMASK(31, 24)
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#define QSPI_DCR 0x04
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#define DCR_FSIZE_MASK GENMASK(20, 16)
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#define QSPI_SR 0x08
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#define SR_TEF BIT(0)
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#define SR_TCF BIT(1)
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#define SR_FTF BIT(2)
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#define SR_SMF BIT(3)
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#define SR_TOF BIT(4)
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#define SR_BUSY BIT(5)
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#define SR_FLEVEL_MASK GENMASK(13, 8)
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#define QSPI_FCR 0x0c
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#define FCR_CTEF BIT(0)
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#define FCR_CTCF BIT(1)
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#define QSPI_DLR 0x10
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#define QSPI_CCR 0x14
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#define CCR_INST_MASK GENMASK(7, 0)
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#define CCR_IMODE_MASK GENMASK(9, 8)
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#define CCR_ADMODE_MASK GENMASK(11, 10)
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#define CCR_ADSIZE_MASK GENMASK(13, 12)
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#define CCR_DCYC_MASK GENMASK(22, 18)
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#define CCR_DMODE_MASK GENMASK(25, 24)
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#define CCR_FMODE_MASK GENMASK(27, 26)
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#define CCR_FMODE_INDW (0U << 26)
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#define CCR_FMODE_INDR (1U << 26)
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#define CCR_FMODE_APM (2U << 26)
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#define CCR_FMODE_MM (3U << 26)
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#define CCR_BUSWIDTH_0 0x0
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#define CCR_BUSWIDTH_1 0x1
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#define CCR_BUSWIDTH_2 0x2
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#define CCR_BUSWIDTH_4 0x3
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#define QSPI_AR 0x18
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#define QSPI_ABR 0x1c
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#define QSPI_DR 0x20
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#define QSPI_PSMKR 0x24
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#define QSPI_PSMAR 0x28
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#define QSPI_PIR 0x2c
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#define QSPI_LPTR 0x30
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#define LPTR_DFT_TIMEOUT 0x10
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#define STM32_QSPI_MAX_MMAP_SZ SZ_256M
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#define STM32_QSPI_MAX_NORCHIP 2
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#define STM32_FIFO_TIMEOUT_US 30000
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#define STM32_BUSY_TIMEOUT_US 100000
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#define STM32_ABT_TIMEOUT_US 100000
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struct stm32_qspi_flash {
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struct stm32_qspi *qspi;
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u32 cs;
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u32 presc;
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};
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struct stm32_qspi {
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struct device *dev;
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void __iomem *io_base;
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void __iomem *mm_base;
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resource_size_t mm_size;
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struct clk *clk;
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u32 clk_rate;
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struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP];
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struct completion data_completion;
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u32 fmode;
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/*
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* to protect device configuration, could be different between
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* 2 flash access (bk1, bk2)
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*/
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struct mutex lock;
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};
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static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
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{
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struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
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u32 cr, sr;
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sr = readl_relaxed(qspi->io_base + QSPI_SR);
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if (sr & (SR_TEF | SR_TCF)) {
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/* disable irq */
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cr = readl_relaxed(qspi->io_base + QSPI_CR);
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cr &= ~CR_TCIE & ~CR_TEIE;
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writel_relaxed(cr, qspi->io_base + QSPI_CR);
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complete(&qspi->data_completion);
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}
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return IRQ_HANDLED;
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}
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static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
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{
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*val = readb_relaxed(addr);
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}
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static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
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{
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writeb_relaxed(*val, addr);
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}
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static int stm32_qspi_tx_poll(struct stm32_qspi *qspi,
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const struct spi_mem_op *op)
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{
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void (*tx_fifo)(u8 *val, void __iomem *addr);
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u32 len = op->data.nbytes, sr;
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u8 *buf;
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int ret;
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if (op->data.dir == SPI_MEM_DATA_IN) {
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tx_fifo = stm32_qspi_read_fifo;
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buf = op->data.buf.in;
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} else {
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tx_fifo = stm32_qspi_write_fifo;
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buf = (u8 *)op->data.buf.out;
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}
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while (len--) {
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ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR,
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sr, (sr & SR_FTF), 1,
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STM32_FIFO_TIMEOUT_US);
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if (ret) {
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dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n",
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len, sr);
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return ret;
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}
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tx_fifo(buf++, qspi->io_base + QSPI_DR);
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}
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return 0;
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}
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static int stm32_qspi_tx_mm(struct stm32_qspi *qspi,
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const struct spi_mem_op *op)
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{
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memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val,
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op->data.nbytes);
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return 0;
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}
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static int stm32_qspi_tx(struct stm32_qspi *qspi, const struct spi_mem_op *op)
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{
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if (!op->data.nbytes)
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return 0;
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if (qspi->fmode == CCR_FMODE_MM)
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return stm32_qspi_tx_mm(qspi, op);
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return stm32_qspi_tx_poll(qspi, op);
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}
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static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi)
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{
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u32 sr;
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return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr,
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!(sr & SR_BUSY), 1,
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STM32_BUSY_TIMEOUT_US);
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}
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static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi,
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const struct spi_mem_op *op)
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{
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u32 cr, sr;
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int err = 0;
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if (!op->data.nbytes)
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return stm32_qspi_wait_nobusy(qspi);
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if (readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF)
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goto out;
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reinit_completion(&qspi->data_completion);
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cr = readl_relaxed(qspi->io_base + QSPI_CR);
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writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR);
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if (!wait_for_completion_interruptible_timeout(&qspi->data_completion,
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msecs_to_jiffies(1000))) {
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err = -ETIMEDOUT;
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} else {
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sr = readl_relaxed(qspi->io_base + QSPI_SR);
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if (sr & SR_TEF)
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err = -EIO;
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}
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out:
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/* clear flags */
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writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR);
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return err;
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}
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static int stm32_qspi_get_mode(struct stm32_qspi *qspi, u8 buswidth)
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{
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if (buswidth == 4)
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return CCR_BUSWIDTH_4;
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return buswidth;
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}
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static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
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struct stm32_qspi_flash *flash = &qspi->flash[mem->spi->chip_select];
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u32 ccr, cr, addr_max;
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int timeout, err = 0;
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dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
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op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
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op->dummy.buswidth, op->data.buswidth,
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op->addr.val, op->data.nbytes);
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err = stm32_qspi_wait_nobusy(qspi);
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if (err)
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goto abort;
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addr_max = op->addr.val + op->data.nbytes + 1;
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if (op->data.dir == SPI_MEM_DATA_IN) {
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if (addr_max < qspi->mm_size &&
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op->addr.buswidth)
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qspi->fmode = CCR_FMODE_MM;
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else
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qspi->fmode = CCR_FMODE_INDR;
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} else {
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qspi->fmode = CCR_FMODE_INDW;
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}
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cr = readl_relaxed(qspi->io_base + QSPI_CR);
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cr &= ~CR_PRESC_MASK & ~CR_FSEL;
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cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc);
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cr |= FIELD_PREP(CR_FSEL, flash->cs);
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writel_relaxed(cr, qspi->io_base + QSPI_CR);
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if (op->data.nbytes)
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writel_relaxed(op->data.nbytes - 1,
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qspi->io_base + QSPI_DLR);
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else
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qspi->fmode = CCR_FMODE_INDW;
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ccr = qspi->fmode;
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ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode);
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ccr |= FIELD_PREP(CCR_IMODE_MASK,
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stm32_qspi_get_mode(qspi, op->cmd.buswidth));
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if (op->addr.nbytes) {
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ccr |= FIELD_PREP(CCR_ADMODE_MASK,
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stm32_qspi_get_mode(qspi, op->addr.buswidth));
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ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1);
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}
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if (op->dummy.buswidth && op->dummy.nbytes)
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ccr |= FIELD_PREP(CCR_DCYC_MASK,
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op->dummy.nbytes * 8 / op->dummy.buswidth);
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if (op->data.nbytes) {
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ccr |= FIELD_PREP(CCR_DMODE_MASK,
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stm32_qspi_get_mode(qspi, op->data.buswidth));
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}
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writel_relaxed(ccr, qspi->io_base + QSPI_CCR);
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if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM)
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writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR);
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err = stm32_qspi_tx(qspi, op);
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/*
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* Abort in:
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* -error case
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* -read memory map: prefetching must be stopped if we read the last
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* byte of device (device size - fifo size). like device size is not
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* knows, the prefetching is always stop.
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*/
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if (err || qspi->fmode == CCR_FMODE_MM)
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goto abort;
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/* wait end of tx in indirect mode */
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err = stm32_qspi_wait_cmd(qspi, op);
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if (err)
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goto abort;
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return 0;
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abort:
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cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT;
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writel_relaxed(cr, qspi->io_base + QSPI_CR);
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/* wait clear of abort bit by hw */
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timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR,
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cr, !(cr & CR_ABORT), 1,
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STM32_ABT_TIMEOUT_US);
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writel_relaxed(FCR_CTCF, qspi->io_base + QSPI_FCR);
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if (err || timeout)
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dev_err(qspi->dev, "%s err:%d abort timeout:%d\n",
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__func__, err, timeout);
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return err;
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}
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static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
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int ret;
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mutex_lock(&qspi->lock);
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ret = stm32_qspi_send(mem, op);
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mutex_unlock(&qspi->lock);
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return ret;
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}
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static int stm32_qspi_setup(struct spi_device *spi)
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{
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struct spi_controller *ctrl = spi->master;
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struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl);
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struct stm32_qspi_flash *flash;
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u32 cr, presc;
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if (ctrl->busy)
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return -EBUSY;
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if (!spi->max_speed_hz)
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return -EINVAL;
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presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1;
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flash = &qspi->flash[spi->chip_select];
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flash->qspi = qspi;
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flash->cs = spi->chip_select;
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flash->presc = presc;
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mutex_lock(&qspi->lock);
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writel_relaxed(LPTR_DFT_TIMEOUT, qspi->io_base + QSPI_LPTR);
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cr = FIELD_PREP(CR_FTHRES_MASK, 3) | CR_TCEN | CR_SSHIFT | CR_EN;
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writel_relaxed(cr, qspi->io_base + QSPI_CR);
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/* set dcr fsize to max address */
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writel_relaxed(DCR_FSIZE_MASK, qspi->io_base + QSPI_DCR);
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mutex_unlock(&qspi->lock);
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return 0;
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}
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/*
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* no special host constraint, so use default spi_mem_default_supports_op
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* to check supported mode.
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*/
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static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
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.exec_op = stm32_qspi_exec_op,
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};
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static void stm32_qspi_release(struct stm32_qspi *qspi)
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{
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/* disable qspi */
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writel_relaxed(0, qspi->io_base + QSPI_CR);
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mutex_destroy(&qspi->lock);
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clk_disable_unprepare(qspi->clk);
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}
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static int stm32_qspi_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct spi_controller *ctrl;
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struct reset_control *rstc;
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struct stm32_qspi *qspi;
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struct resource *res;
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int ret, irq;
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ctrl = spi_alloc_master(dev, sizeof(*qspi));
|
||||
if (!ctrl)
|
||||
return -ENOMEM;
|
||||
|
||||
qspi = spi_controller_get_devdata(ctrl);
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
|
||||
qspi->io_base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(qspi->io_base))
|
||||
return PTR_ERR(qspi->io_base);
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
|
||||
qspi->mm_base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(qspi->mm_base))
|
||||
return PTR_ERR(qspi->mm_base);
|
||||
|
||||
qspi->mm_size = resource_size(res);
|
||||
if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ)
|
||||
return -EINVAL;
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
|
||||
dev_name(dev), qspi);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to request irq\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
init_completion(&qspi->data_completion);
|
||||
|
||||
qspi->clk = devm_clk_get(dev, NULL);
|
||||
if (IS_ERR(qspi->clk))
|
||||
return PTR_ERR(qspi->clk);
|
||||
|
||||
qspi->clk_rate = clk_get_rate(qspi->clk);
|
||||
if (!qspi->clk_rate)
|
||||
return -EINVAL;
|
||||
|
||||
ret = clk_prepare_enable(qspi->clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "can not enable the clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
rstc = devm_reset_control_get_exclusive(dev, NULL);
|
||||
if (!IS_ERR(rstc)) {
|
||||
reset_control_assert(rstc);
|
||||
udelay(2);
|
||||
reset_control_deassert(rstc);
|
||||
}
|
||||
|
||||
qspi->dev = dev;
|
||||
platform_set_drvdata(pdev, qspi);
|
||||
mutex_init(&qspi->lock);
|
||||
|
||||
ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD
|
||||
| SPI_TX_DUAL | SPI_TX_QUAD;
|
||||
ctrl->setup = stm32_qspi_setup;
|
||||
ctrl->bus_num = -1;
|
||||
ctrl->mem_ops = &stm32_qspi_mem_ops;
|
||||
ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP;
|
||||
ctrl->dev.of_node = dev->of_node;
|
||||
|
||||
ret = devm_spi_register_master(dev, ctrl);
|
||||
if (ret)
|
||||
goto err_spi_register;
|
||||
|
||||
return 0;
|
||||
|
||||
err_spi_register:
|
||||
stm32_qspi_release(qspi);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32_qspi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct stm32_qspi *qspi = platform_get_drvdata(pdev);
|
||||
|
||||
stm32_qspi_release(qspi);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id stm32_qspi_match[] = {
|
||||
{.compatible = "st,stm32f469-qspi"},
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, stm32_qspi_match);
|
||||
|
||||
static struct platform_driver stm32_qspi_driver = {
|
||||
.probe = stm32_qspi_probe,
|
||||
.remove = stm32_qspi_remove,
|
||||
.driver = {
|
||||
.name = "stm32-qspi",
|
||||
.of_match_table = stm32_qspi_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(stm32_qspi_driver);
|
||||
|
||||
MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
|
||||
MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue