p71924506
/
linux_old1
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

i2c: stm32f7: fix documentation typo 

Some data structure members were either misspelled or missing.

Fixes: aeb068c572 ("i2c: i2c-stm32f7: add driver")
Fixes: 380b8a85e7 ("i2c: i2c-stm32f7: Add initial SMBus protocols support")
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Pierre-Yves MORDRET 2018-05-11 10:20:25 +02:00 committed by Wolfram Sang
parent 4b2f9bd5e3
commit c599eb4ff6
1 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/i2c/busses/i2c-stm32f7.c
View File

@ -211,11 +211,12 @@ struct stm32f7_i2c_setup {
/** /**
* struct stm32f7_i2c_timings - private I2C output parameters * struct stm32f7_i2c_timings - private I2C output parameters
* @prec: Prescaler value * @node: List entry
* @presc: Prescaler value
* @scldel: Data setup time * @scldel: Data setup time
* @sdadel: Data hold time * @sdadel: Data hold time
* @sclh: SCL high period (master mode) * @sclh: SCL high period (master mode)
* @sclh: SCL low period (master mode) * @scll: SCL low period (master mode)
*/ */
struct stm32f7_i2c_timings { struct stm32f7_i2c_timings {
struct list_head node; struct list_head node;
@ -237,7 +238,7 @@ struct stm32f7_i2c_timings {
* @size: type of SMBus protocol * @size: type of SMBus protocol
* @read_write: direction of SMBus protocol * @read_write: direction of SMBus protocol
* SMBus block read and SMBus block write - block read process call protocols * SMBus block read and SMBus block write - block read process call protocols
* @smbus_buff: buffer to be used for SMBus protocol transfer. It will * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
* contain a maximum of 32 bytes of data + byte command + byte count + PEC * contain a maximum of 32 bytes of data + byte command + byte count + PEC
* This buffer has to be 32-bit aligned to be compliant with memory address * This buffer has to be 32-bit aligned to be compliant with memory address
* register in DMA mode. * register in DMA mode.