mmc: dw_mmc: exynos: adjust the clock rate with speed mode
Exynos's host has divider logic before 'cclk_in' to controller core. It means that actual clock rate of ciu clock comes from this divider value. So, source clock should be adjusted along with 'ciu_div' which indicates the host's divider ratio. Setting clock rate basically fits the required speed. Specially, 'cclk_in' should have double rate of target speed in case of DDR 8-bit mode. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
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@ -56,6 +56,8 @@
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#define DWMCI_MPSCTRL_ENCRYPTION BIT(1)
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#define DWMCI_MPSCTRL_ENCRYPTION BIT(1)
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#define DWMCI_MPSCTRL_VALID BIT(0)
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#define DWMCI_MPSCTRL_VALID BIT(0)
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#define EXYNOS_CCLKIN_MIN 50000000 /* unit: HZ */
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/* Variations in Exynos specific dw-mshc controller */
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/* Variations in Exynos specific dw-mshc controller */
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enum dw_mci_exynos_type {
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enum dw_mci_exynos_type {
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DW_MCI_TYPE_EXYNOS4210,
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DW_MCI_TYPE_EXYNOS4210,
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@ -71,6 +73,7 @@ struct dw_mci_exynos_priv_data {
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u8 ciu_div;
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u8 ciu_div;
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u32 sdr_timing;
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u32 sdr_timing;
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u32 ddr_timing;
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u32 ddr_timing;
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u32 cur_speed;
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};
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};
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static struct dw_mci_exynos_compatible {
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static struct dw_mci_exynos_compatible {
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@ -114,16 +117,9 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
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static int dw_mci_exynos_setup_clock(struct dw_mci *host)
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static int dw_mci_exynos_setup_clock(struct dw_mci *host)
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{
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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struct dw_mci_exynos_priv_data *priv = host->priv;
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unsigned long rate = clk_get_rate(host->ciu_clk);
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5250 ||
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host->bus_hz = rate / (priv->ciu_div + 1);
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU)
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host->bus_hz /= (priv->ciu_div + 1);
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else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
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host->bus_hz /= EXYNOS4412_FIXED_CIU_CLK_DIV;
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else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
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host->bus_hz /= EXYNOS4210_FIXED_CIU_CLK_DIV;
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return 0;
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return 0;
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}
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}
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@ -187,11 +183,38 @@ static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
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static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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{
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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struct dw_mci_exynos_priv_data *priv = host->priv;
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unsigned int wanted = ios->clock;
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unsigned long actual;
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u8 div = priv->ciu_div + 1;
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if (ios->timing == MMC_TIMING_UHS_DDR50)
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if (ios->timing == MMC_TIMING_UHS_DDR50) {
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mci_writel(host, CLKSEL, priv->ddr_timing);
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mci_writel(host, CLKSEL, priv->ddr_timing);
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else
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/* Should be double rate for DDR mode */
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if (ios->bus_width == MMC_BUS_WIDTH_8)
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wanted <<= 1;
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} else {
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mci_writel(host, CLKSEL, priv->sdr_timing);
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mci_writel(host, CLKSEL, priv->sdr_timing);
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}
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/* Don't care if wanted clock is zero */
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if (!wanted)
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return;
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/* Guaranteed minimum frequency for cclkin */
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if (wanted < EXYNOS_CCLKIN_MIN)
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wanted = EXYNOS_CCLKIN_MIN;
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if (wanted != priv->cur_speed) {
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int ret = clk_set_rate(host->ciu_clk, wanted * div);
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if (ret)
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dev_warn(host->dev,
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"failed to set clk-rate %u error: %d\n",
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wanted * div, ret);
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actual = clk_get_rate(host->ciu_clk);
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host->bus_hz = actual / div;
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priv->cur_speed = wanted;
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host->current_speed = 0;
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}
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}
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}
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static int dw_mci_exynos_parse_dt(struct dw_mci *host)
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static int dw_mci_exynos_parse_dt(struct dw_mci *host)
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@ -214,8 +237,14 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
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priv->ctrl_type = exynos_compat[idx].ctrl_type;
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priv->ctrl_type = exynos_compat[idx].ctrl_type;
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}
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}
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of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
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priv->ciu_div = div;
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priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1;
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else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
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priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1;
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else {
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of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
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priv->ciu_div = div;
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}
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ret = of_property_read_u32_array(np,
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ret = of_property_read_u32_array(np,
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"samsung,dw-mshc-sdr-timing", timing, 2);
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"samsung,dw-mshc-sdr-timing", timing, 2);
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