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ARM: shmobile: sh73a0 dtsi: Add L2 cache-controller node 

Add the missing L2 cache-controller node, and link the CPU nodes to it.
This will allow migration to the generic l2c OF initialization.

The L2 cache is an ARM L2C-310 (r3p1), of size 512 KiB (64 KiB x 8
ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven 2015-11-23 14:56:00 +01:00 committed by Simon Horman
parent 374e70075e
commit c8d9fdbe2d
1 changed files with 14 additions and 0 deletions
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14
arch/arm/boot/dts/sh73a0.dtsi
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@ -28,6 +28,7 @@ cpu@0 {
reg = <0>; reg = <0>;
clock-frequency = <1196000000>; clock-frequency = <1196000000>;
power-domains = <&pd_a2sl>; power-domains = <&pd_a2sl>;
next-level-cache = <&L2>;
}; };
cpu@1 { cpu@1 {
device_type = "cpu"; device_type = "cpu";
@ -35,6 +36,7 @@ cpu@1 {
reg = <1>; reg = <1>;
clock-frequency = <1196000000>; clock-frequency = <1196000000>;
power-domains = <&pd_a2sl>; power-domains = <&pd_a2sl>;
next-level-cache = <&L2>;
}; };
}; };
@ -53,6 +55,18 @@ gic: interrupt-controller@f0001000 {
<0xf0000100 0x100>; <0xf0000100 0x100>;
}; };
L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0xf0100000 0x1000>;
interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_a3sm>;
arm,data-latency = <3 3 3>;
arm,tag-latency = <2 2 2>;
arm,shared-override;
cache-unified;
cache-level = <2>;
};
sbsc2: memory-controller@fb400000 { sbsc2: memory-controller@fb400000 {
compatible = "renesas,sbsc-sh73a0"; compatible = "renesas,sbsc-sh73a0";
reg = <0xfb400000 0x400>; reg = <0xfb400000 0x400>;