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Our usual round of DT patches for the 5.17 merge window, with: 

- Introduction of the chassis-type property
   - I2C, SPDIF support for the Tanix TX6
   - Memory frequency scaling for the A64 and H5
   - Hantro G2 support for the H6
   - New Board: Tanix TX6 Mini
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Merge tag 'sunxi-dt-for-5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt

Our usual round of DT patches for the 5.17 merge window, with:
  - Introduction of the chassis-type property
  - I2C, SPDIF support for the Tanix TX6
  - Memory frequency scaling for the A64 and H5
  - Hantro G2 support for the H6
  - New Board: Tanix TX6 Mini

* tag 'sunxi-dt-for-5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: dts: allwinner: h6: Add Hantro G2 node
  arm64: dts: allwinner: h6: tanix-tx6: Enable bluetooth
  arm64: dts: allwinner: h6: tanix: Add MMC1 node
  arm64: dts: allwinner: h6: Add Tanix TX6 mini dts
  dt-bindings: arm: sunxi: Add Tanix TX6 mini
  arm64: dts: allwinner: h6: tanix-tx6: Split to DT and DTSI
  ARM: dts: sun8i: Adjust power key nodes
  arm64: dts: allwinner: a64: Update MBUS node
  ARM: dts: sunxi: h3/h5: Update MBUS node
  dt-bindings: arm: sunxi: Add H5 MBUS compatible
  dt-bindings: arm: sunxi: Expand MBUS binding
  dt-bindings: clock: sunxi: Export CLK_DRAM for devfreq
  dt-bindings: crypto: Add optional dma properties
  ARM: dts: sun8i: h3: beelink-x2: Add GPIO CEC node
  ARM: dts: sunxi: Add CEC clock to DW-HDMI
  arm64: dts: allwinner: a64: Add CEC clock to HDMI
  ARM: dts: sun8i: h3: beelink-x2: Sort nodes
  arm64: dts: allwinner: h6: tanix-tx6: Add I2C node
  arm64: dts: allwinner: h6: tanix-tx6: Add SPDIF
  arm64: dts: allwinner: add 'chassis-type' property

Link: https://lore.kernel.org/r/ef385139-6fd4-42d2-9bfe-a4dda7ac76c9.lettre@localhost
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2021-12-17 15:52:07 +01:00
parent 365ee80331 0baddea60e
commit c9074c9151
28 changed files with 394 additions and 166 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
Documentation/devicetree/bindings/arm/sunxi.yaml
View File

@ -808,6 +808,11 @@ properties:
- const: oranth,tanix-tx6
- const: allwinner,sun50i-h6
- description: Tanix TX6 mini
items:
- const: oranth,tanix-tx6-mini
- const: allwinner,sun50i-h6
- description: TBS A711 Tablet
items:
- const: tbs-biometrics,a711

91
Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
View File

@ -32,12 +32,38 @@ properties:
- allwinner,sun8i-h3-mbus
- allwinner,sun8i-r40-mbus
- allwinner,sun50i-a64-mbus
- allwinner,sun50i-h5-mbus
reg:
maxItems: 1
minItems: 1
items:
- description: MBUS interconnect/bandwidth limit/PMU registers
- description: DRAM controller/PHY registers
reg-names:
minItems: 1
items:
- const: mbus
- const: dram
clocks:
minItems: 1
items:
- description: MBUS interconnect module clock
- description: DRAM controller/PHY module clock
- description: Register bus clock, shared by MBUS and DRAM
clock-names:
minItems: 1
items:
- const: mbus
- const: dram
- const: bus
interrupts:
maxItems: 1
description:
MBUS PMU activity interrupt.
dma-ranges:
description:
@ -54,13 +80,55 @@ required:
- clocks
- dma-ranges
if:
properties:
compatible:
contains:
enum:
- allwinner,sun8i-h3-mbus
- allwinner,sun50i-a64-mbus
- allwinner,sun50i-h5-mbus
then:
properties:
reg:
minItems: 2
reg-names:
minItems: 2
clocks:
minItems: 3
clock-names:
minItems: 3
required:
- reg-names
- clock-names
else:
properties:
reg:
maxItems: 1
reg-names:
maxItems: 1
clocks:
maxItems: 1
clock-names:
maxItems: 1
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/sun5i-ccu.h>
#include <dt-bindings/clock/sun50i-a64-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
mbus: dram-controller@1c01000 {
dram-controller@1c01000 {
compatible = "allwinner,sun5i-a13-mbus";
reg = <0x01c01000 0x1000>;
clocks = <&ccu CLK_MBUS>;
@ -70,4 +138,21 @@ examples:
#interconnect-cells = <1>;
};
- |
dram-controller@1c62000 {
compatible = "allwinner,sun50i-a64-mbus";
reg = <0x01c62000 0x1000>,
<0x01c63000 0x1000>;
reg-names = "mbus", "dram";
clocks = <&ccu CLK_MBUS>,
<&ccu CLK_DRAM>,
<&ccu CLK_BUS_DRAM>;
clock-names = "mbus", "dram", "bus";
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x00000000 0x40000000 0xc0000000>;
#interconnect-cells = <1>;
};
...

10
Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml
View File

@ -44,6 +44,16 @@ properties:
- const: ahb
- const: mod
dmas:
items:
- description: RX DMA Channel
- description: TX DMA Channel
dma-names:
items:
- const: rx
- const: tx
resets:
maxItems: 1

3
arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
View File

@ -52,8 +52,9 @@ gpio_keys {
sw4 {
label = "power";
linux,code = <BTN_0>;
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};

34
arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
View File

@ -57,6 +57,12 @@ aliases {
ethernet1 = &sdiowifi;
};
cec-gpio {
compatible = "cec-gpio";
cec-gpios = <&pio 0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PA14 */
hdmi-phandle = <&hdmi>;
};
chosen {
stdout-path = "serial0:115200n8";
};
@ -87,11 +93,15 @@ led-1 {
};
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
clocks = <&rtc 1>;
clock-names = "ext_clock";
r-gpio-keys {
compatible = "gpio-keys";
power {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
sound_spdif {
@ -112,15 +122,11 @@ spdif_out: spdif-out {
compatible = "linux,spdif-dit";
};
r-gpio-keys {
compatible = "gpio-keys";
power {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
wakeup-source;
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
clocks = <&rtc 1>;
clock-names = "ext_clock";
};
};

1
arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
View File

@ -81,6 +81,7 @@ k1 {
label = "k1";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
};

3
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
View File

@ -99,8 +99,9 @@ sw2 {
sw4 {
label = "sw4";
linux,code = <BTN_0>;
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};

3
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
View File

@ -91,8 +91,9 @@ r_gpio_keys {
sw4 {
label = "sw4";
linux,code = <BTN_0>;
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
};

4
arch/arm/boot/dts/sun8i-h3.dtsi
View File

@ -282,6 +282,10 @@ &display_clocks {
compatible = "allwinner,sun8i-h3-de2-clk";
};
&mbus {
compatible = "allwinner,sun8i-h3-mbus";
};
&mmc0 {
compatible = "allwinner,sun7i-a20-mmc";
clocks = <&ccu CLK_BUS_MMC0>,

4
arch/arm/boot/dts/sun8i-r40.dtsi
View File

@ -1212,8 +1212,8 @@ hdmi: hdmi@1ee0000 {
reg-io-width = <1>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
<&ccu CLK_HDMI>;
clock-names = "iahb", "isfr", "tmds";
<&ccu CLK_HDMI>, <&rtc 0>;
clock-names = "iahb", "isfr", "tmds", "cec";
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
phys = <&hdmi_phy>;

3
arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
View File

@ -82,8 +82,9 @@ gpio_keys {
sw4 {
label = "power";
linux,code = <BTN_0>;
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};

15
arch/arm/boot/dts/sunxi-h3-h5.dtsi
View File

@ -568,9 +568,14 @@ external_mdio: mdio@2 {
};
mbus: dram-controller@1c62000 {
compatible = "allwinner,sun8i-h3-mbus";
reg = <0x01c62000 0x1000>;
clocks = <&ccu CLK_MBUS>;
/* compatible is in per SoC .dtsi file */
reg = <0x01c62000 0x1000>,
<0x01c63000 0x1000>;
reg-names = "mbus", "dram";
clocks = <&ccu CLK_MBUS>,
<&ccu CLK_DRAM>,
<&ccu CLK_BUS_DRAM>;
clock-names = "mbus", "dram", "bus";
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x00000000 0x40000000 0xc0000000>;
@ -813,8 +818,8 @@ hdmi: hdmi@1ee0000 {
reg-io-width = <1>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
<&ccu CLK_HDMI>;
clock-names = "iahb", "isfr", "tmds";
<&ccu CLK_HDMI>, <&rtc 0>;
clock-names = "iahb", "isfr", "tmds", "cec";
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
phys = <&hdmi_phy>;

1
arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi
View File

@ -49,6 +49,7 @@ power {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
wakeup-source;
};
};

1
arch/arm64/boot/dts/allwinner/Makefile
View File

@ -37,3 +37,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb

1
arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
View File

@ -15,6 +15,7 @@
/ {
model = "Pinebook";
compatible = "pine64,pinebook", "allwinner,sun50i-a64";
chassis-type = "laptop";
aliases {
serial0 = &uart0;

2
arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
View File

@ -12,6 +12,8 @@
#include <dt-bindings/pwm/pwm.h>
/ {
chassis-type = "handset";
aliases {
ethernet0 = &rtl8723cs;
serial0 = &uart0;

1
arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
View File

@ -16,6 +16,7 @@
/ {
model = "PineTab, Development Sample";
compatible = "pine64,pinetab", "allwinner,sun50i-a64";
chassis-type = "tablet";
aliases {
serial0 = &uart0;

1
arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
View File

@ -14,6 +14,7 @@
/ {
model = "Olimex A64 Teres-I";
compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64";
chassis-type = "laptop";
aliases {
serial0 = &uart0;

14
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
View File

@ -1146,8 +1146,14 @@ pwm: pwm@1c21400 {
mbus: dram-controller@1c62000 {
compatible = "allwinner,sun50i-a64-mbus";
reg = <0x01c62000 0x1000>;
clocks = <&ccu 112>;
reg = <0x01c62000 0x1000>,
<0x01c63000 0x1000>;
reg-names = "mbus", "dram";
clocks = <&ccu CLK_MBUS>,
<&ccu CLK_DRAM>,
<&ccu CLK_BUS_DRAM>;
clock-names = "mbus", "dram", "bus";
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x00000000 0x40000000 0xc0000000>;
@ -1220,8 +1226,8 @@ hdmi: hdmi@1ee0000 {
reg-io-width = <1>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
<&ccu CLK_HDMI>;
clock-names = "iahb", "isfr", "tmds";
<&ccu CLK_HDMI>, <&rtc 0>;
clock-names = "iahb", "isfr", "tmds", "cec";
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
phys = <&hdmi_phy>;

4
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
View File

@ -233,6 +233,10 @@ &display_clocks {
compatible = "allwinner,sun50i-h5-de2-clk";
};
&mbus {
compatible = "allwinner,sun50i-h5-mbus";
};
&mmc0 {
compatible = "allwinner,sun50i-h5-mmc",
"allwinner,sun50i-a64-mmc";

15
arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (c) 2021 Jernej Skrabec <jernej.skrabec@gmail.com>
/dts-v1/;
#include "sun50i-h6-tanix.dtsi"
/ {
model = "Tanix TX6 mini";
compatible = "oranth,tanix-tx6-mini", "allwinner,sun50i-h6";
};
&r_ir {
linux,rc-map-name = "rc-tanix-tx3mini";
};

138
arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
View File

@ -3,145 +3,27 @@
/dts-v1/;
#include "sun50i-h6.dtsi"
#include "sun50i-h6-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include "sun50i-h6-tanix.dtsi"
/ {
model = "Tanix TX6";
compatible = "oranth,tanix-tx6", "allwinner,sun50i-h6";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
connector {
compatible = "hdmi-connector";
ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
reg_vcc1v8: regulator-vcc1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_vcc3v3: regulator-vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu {
compatible = "regulator-fixed";
regulator-name = "vdd-cpu-gpu";
regulator-min-microvolt = <1135000>;
regulator-max-microvolt = <1135000>;
};
};
&cpu0 {
cpu-supply = <&reg_vdd_cpu_gpu>;
};
&de {
status = "okay";
};
&dwc3 {
status = "okay";
};
&ehci0 {
status = "okay";
};
&ehci3 {
status = "okay";
};
&gpu {
mali-supply = <&reg_vdd_cpu_gpu>;
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_vcc3v3>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
&mmc2 {
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc1v8>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
mmc-hs200-1_8v;
status = "okay";
};
&ohci0 {
status = "okay";
};
&ohci3 {
status = "okay";
};
&pio {
vcc-pc-supply = <&reg_vcc1v8>;
vcc-pd-supply = <&reg_vcc3v3>;
vcc-pg-supply = <&reg_vcc1v8>;
};
&r_ir {
linux,rc-map-name = "rc-tanix-tx5max";
status = "okay";
};
&uart0 {
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
uart-has-rtscts;
status = "okay";
};
&usb2otg {
dr_mode = "host";
status = "okay";
};
&usb2phy {
status = "okay";
};
&usb3phy {
status = "okay";
bluetooth {
compatible = "realtek,rtl8822cs-bt";
device-wake-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */
host-wake-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */
enable-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */
};
};

189
arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi Normal file
View File

@ -0,0 +1,189 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (c) 2019 Jernej Skrabec <jernej.skrabec@siol.net>
/dts-v1/;
#include "sun50i-h6.dtsi"
#include "sun50i-h6-cpu-opp.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
connector {
compatible = "hdmi-connector";
ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
/* used for FD650 LED display driver */
i2c {
compatible = "i2c-gpio";
sda-gpios = <&pio 7 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PH6 */
scl-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PH5 */
i2c-gpio,delay-us = <5>;
};
reg_vcc1v8: regulator-vcc1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_vcc3v3: regulator-vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu {
compatible = "regulator-fixed";
regulator-name = "vdd-cpu-gpu";
regulator-min-microvolt = <1135000>;
regulator-max-microvolt = <1135000>;
};
sound-spdif {
compatible = "simple-audio-card";
simple-audio-card,name = "sun50i-h6-spdif";
simple-audio-card,cpu {
sound-dai = <&spdif>;
};
simple-audio-card,codec {
sound-dai = <&spdif_out>;
};
};
spdif_out: spdif-out {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rtc 1>;
clock-names = "ext_clock";
reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
};
};
&cpu0 {
cpu-supply = <&reg_vdd_cpu_gpu>;
};
&de {
status = "okay";
};
&dwc3 {
status = "okay";
};
&ehci0 {
status = "okay";
};
&ehci3 {
status = "okay";
};
&gpu {
mali-supply = <&reg_vdd_cpu_gpu>;
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_vcc3v3>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
&mmc1 {
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc1v8>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
};
&mmc2 {
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc1v8>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
mmc-hs200-1_8v;
status = "okay";
};
&ohci0 {
status = "okay";
};
&ohci3 {
status = "okay";
};
&pio {
vcc-pc-supply = <&reg_vcc1v8>;
vcc-pd-supply = <&reg_vcc3v3>;
vcc-pg-supply = <&reg_vcc1v8>;
};
&r_ir {
status = "okay";
};
&spdif {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
&usb2otg {
dr_mode = "host";
status = "okay";
};
&usb2phy {
status = "okay";
};
&usb3phy {
status = "okay";
};

9
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
View File

@ -153,6 +153,15 @@ mixer0_out_tcon_top_mixer0: endpoint {
};
};
video-codec-g2@1c00000 {
compatible = "allwinner,sun50i-h6-vpu-g2";
reg = <0x01c00000 0x1000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>;
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_VP9>;
};
video-codec@1c0e000 {
compatible = "allwinner,sun50i-h6-video-engine";
reg = <0x01c0e000 0x2000>;

2
drivers/clk/sunxi-ng/ccu-sun50i-a64.h
View File

@ -51,8 +51,6 @@
#define CLK_USB_OHCI1_12M 92
#define CLK_DRAM 94
/* All the DRAM gates are exported */
/* And the DSI and GPU module clock is exported */

2
drivers/clk/sunxi-ng/ccu-sun8i-h3.h
View File

@ -42,8 +42,6 @@
/* The first bunch of module clocks are exported */
#define CLK_DRAM 96
/* All the DRAM gates are exported */
/* Some more module clocks are exported */

2
include/dt-bindings/clock/sun50i-a64-ccu.h
View File

@ -113,7 +113,7 @@
#define CLK_USB_OHCI0 91
#define CLK_USB_OHCI1 93
#define CLK_DRAM 94
#define CLK_DRAM_VE 95
#define CLK_DRAM_CSI 96
#define CLK_DRAM_DEINTERLACE 97

2
include/dt-bindings/clock/sun8i-h3-ccu.h
View File

@ -126,7 +126,7 @@
#define CLK_USB_OHCI1 93
#define CLK_USB_OHCI2 94
#define CLK_USB_OHCI3 95
#define CLK_DRAM 96
#define CLK_DRAM_VE 97
#define CLK_DRAM_CSI 98
#define CLK_DRAM_DEINTERLACE 99