imx-drm fixes and color format updates
- Some correctness fixes found by coccinelle - Add drivers/gpu/ipu-v3 directory to MAINTAINERS - Add support for more color formats - Fix a regression, making displays larger than FullHD work again -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWM5loAAoJEFDCiBxwnmDrLwkQAOd2iOsgGemyffmh8shGwGq4 pVgw/2Z9FzdlLXe21R9B8rYOsvq/QR74m49blNGSwlNO6c2L3+65BBkyc2VQoI6t c3GX0w2mnjqfHOZYiBT1Ca84FT1DBXjOprhljVbCBBZOr0xK4jRY3YBtlk30r8Yv RlithxYNWjoCBidf4w7FyCKM7tIN7bNXXGtyysAMzNuXU7Mq3dfhF8/qYucYFmYP XHOxFFX/q4EYchcQBCQi56kxEgEHtaFc+pwzM7mCwN5OVETcVeHw0EoTm56AjQrL zHwBXvP4ryKpuNFCUqsMdy9KZw+4inHycAjfEKwD2s72llycx+W+Kbg/00Ve8rWn 6/Iv4Q0SuSSuRn4fWfioWSdQqHBZig3Y0AWCQ8BVCdTL2K2KIyxcT45vamo/zQhw uxRVxQzEUle4ZJJ4DOt5h4ZHF70eQNM9TDGYYSKUqtfQcbZ6pr6mz36J9PgyQuh7 lTOfC5OZstTmS1iK+dqb5zbxhC76ff+v1lS8oTyJPK207f0hwt5OXTki9i7TueUH DXbPmrotajFWoNOkgFPcBBQaI6P5+29lzFqXE2z43Qk6UoYmR4T+UbpD2nNKaj+I qsIvgn4Zkg2RkxXehVQxRqynxx7XzfXVBXmtpbDfm50PoWsQMQa7fUiqWTyAp493 zQybk9I0eNexJNFIzyie =EqNE -----END PGP SIGNATURE----- Merge tag 'imx-drm-next-2015-10-30' of git://git.pengutronix.de/git/pza/linux into drm-next imx-drm fixes and color format updates - Some correctness fixes found by coccinelle - Add drivers/gpu/ipu-v3 directory to MAINTAINERS - Add support for more color formats - Fix a regression, making displays larger than FullHD work again * tag 'imx-drm-next-2015-10-30' of git://git.pengutronix.de/git/pza/linux: drm/imx: hdmi: fix HDMI setup to allow modes larger than FullHD gpu: ipu-v3: fix div_ratio type gpu: ipu-v3: csi: add support for 8 bpp grayscale sensors. drm/imx: enable ARGB4444 16-bit color format gpu: ipu-v3: add support for ARGB4444 16-bit color format drm/imx: ipuv3-plane: enable support for RGBX8888 and RGBA8888 pixel formats gpu: ipu-v3: add support for RGBX8888 and RGBA8888 pixel formats drm/imx: enable 15-bit RGB with 1-bit alpha formats gpu: ipu-v3: add support for 15-bit RGB with 1-bit alpha formats MAINTAINERS: Add IPUv3 core driver to the i.MX DRM driver section gpu: ipu-v3: ipu-csi: bool test doesn't need a comparison to false
This commit is contained in:
Dave Airlie
commit
cb0fb27121
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@ -3618,6 +3618,7 @@ M: Philipp Zabel <p.zabel@pengutronix.de>
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L: dri-devel@lists.freedesktop.org
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S: Maintained
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F: drivers/gpu/drm/imx/
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F: drivers/gpu/ipu-v3/
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F: Documentation/devicetree/bindings/drm/imx/
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DRM DRIVERS FOR NVIDIA TEGRA
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@ -48,11 +48,17 @@ static const struct dw_hdmi_mpll_config imx_mpll_cfg[] = {
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{ 0x40a2, 0x000a },
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},
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}, {
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~0UL, {
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216000000, {
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{ 0x00a0, 0x000a },
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{ 0x2001, 0x000f },
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{ 0x4002, 0x000f },
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},
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}, {
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~0UL, {
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{ 0x0000, 0x0000 },
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{ 0x0000, 0x0000 },
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{ 0x0000, 0x0000 },
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},
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}
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};
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@ -82,7 +88,7 @@ static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = {
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*/
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static const struct dw_hdmi_phy_config imx_phy_config[] = {
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/*pixelclk symbol term vlev */
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{ 148500000, 0x800d, 0x0005, 0x01ad},
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{ 216000000, 0x800d, 0x0005, 0x01ad},
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{ ~0UL, 0x0000, 0x0000, 0x0000}
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};
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@ -148,7 +154,8 @@ static enum drm_mode_status imx6q_hdmi_mode_valid(struct drm_connector *con,
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{
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if (mode->clock < 13500)
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return MODE_CLOCK_LOW;
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if (mode->clock > 266000)
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/* FIXME: Hardware is capable of 266MHz, but setup data is missing. */
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if (mode->clock > 216000)
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return MODE_CLOCK_HIGH;
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return MODE_OK;
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@ -159,7 +166,8 @@ static enum drm_mode_status imx6dl_hdmi_mode_valid(struct drm_connector *con,
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{
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if (mode->clock < 13500)
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return MODE_CLOCK_LOW;
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if (mode->clock > 270000)
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/* FIXME: Hardware is capable of 270MHz, but setup data is missing. */
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if (mode->clock > 216000)
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return MODE_CLOCK_HIGH;
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return MODE_OK;
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@ -23,12 +23,21 @@
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#define to_ipu_plane(x) container_of(x, struct ipu_plane, base)
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static const uint32_t ipu_plane_formats[] = {
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DRM_FORMAT_ARGB1555,
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DRM_FORMAT_XRGB1555,
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DRM_FORMAT_ABGR1555,
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DRM_FORMAT_XBGR1555,
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DRM_FORMAT_RGBA5551,
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DRM_FORMAT_BGRA5551,
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DRM_FORMAT_ARGB4444,
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_ABGR8888,
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_RGBA8888,
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DRM_FORMAT_RGBX8888,
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DRM_FORMAT_BGRA8888,
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DRM_FORMAT_BGRA8888,
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DRM_FORMAT_YUYV,
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DRM_FORMAT_YVYU,
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DRM_FORMAT_YUV420,
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@ -175,8 +184,15 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
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ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y);
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/* Enable local alpha on partial plane */
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switch (fb->pixel_format) {
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case DRM_FORMAT_ARGB1555:
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case DRM_FORMAT_ABGR1555:
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case DRM_FORMAT_RGBA5551:
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case DRM_FORMAT_BGRA5551:
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case DRM_FORMAT_ARGB4444:
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case DRM_FORMAT_ARGB8888:
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case DRM_FORMAT_ABGR8888:
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case DRM_FORMAT_RGBA8888:
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case DRM_FORMAT_BGRA8888:
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ipu_dp_set_global_alpha(ipu_plane->dp, false, 0, false);
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break;
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default:
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@ -57,10 +57,15 @@ EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
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enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
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{
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switch (drm_fourcc) {
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case DRM_FORMAT_ARGB1555:
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case DRM_FORMAT_ABGR1555:
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case DRM_FORMAT_RGBA5551:
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case DRM_FORMAT_BGRA5551:
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case DRM_FORMAT_RGB565:
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case DRM_FORMAT_BGR565:
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case DRM_FORMAT_RGB888:
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case DRM_FORMAT_BGR888:
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case DRM_FORMAT_ARGB4444:
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_RGBX8888:
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@ -452,7 +452,7 @@ void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
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}
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EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar);
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static const struct ipu_rgb def_rgb_32 = {
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static const struct ipu_rgb def_xrgb_32 = {
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.red = { .offset = 16, .length = 8, },
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.green = { .offset = 8, .length = 8, },
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.blue = { .offset = 0, .length = 8, },
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@ -460,7 +460,7 @@ static const struct ipu_rgb def_rgb_32 = {
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.bits_per_pixel = 32,
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};
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static const struct ipu_rgb def_bgr_32 = {
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static const struct ipu_rgb def_xbgr_32 = {
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.red = { .offset = 0, .length = 8, },
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.green = { .offset = 8, .length = 8, },
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.blue = { .offset = 16, .length = 8, },
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@ -468,6 +468,22 @@ static const struct ipu_rgb def_bgr_32 = {
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.bits_per_pixel = 32,
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};
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static const struct ipu_rgb def_rgbx_32 = {
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.red = { .offset = 24, .length = 8, },
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.green = { .offset = 16, .length = 8, },
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.blue = { .offset = 8, .length = 8, },
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.transp = { .offset = 0, .length = 8, },
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.bits_per_pixel = 32,
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};
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static const struct ipu_rgb def_bgrx_32 = {
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.red = { .offset = 8, .length = 8, },
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.green = { .offset = 16, .length = 8, },
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.blue = { .offset = 24, .length = 8, },
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.transp = { .offset = 0, .length = 8, },
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.bits_per_pixel = 32,
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};
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static const struct ipu_rgb def_rgb_24 = {
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.red = { .offset = 16, .length = 8, },
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.green = { .offset = 8, .length = 8, },
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@ -500,6 +516,46 @@ static const struct ipu_rgb def_bgr_16 = {
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.bits_per_pixel = 16,
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};
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static const struct ipu_rgb def_argb_16 = {
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.red = { .offset = 10, .length = 5, },
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.green = { .offset = 5, .length = 5, },
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.blue = { .offset = 0, .length = 5, },
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.transp = { .offset = 15, .length = 1, },
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.bits_per_pixel = 16,
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};
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static const struct ipu_rgb def_argb_16_4444 = {
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.red = { .offset = 8, .length = 4, },
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.green = { .offset = 4, .length = 4, },
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.blue = { .offset = 0, .length = 4, },
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.transp = { .offset = 12, .length = 4, },
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.bits_per_pixel = 16,
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};
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static const struct ipu_rgb def_abgr_16 = {
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.red = { .offset = 0, .length = 5, },
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.green = { .offset = 5, .length = 5, },
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.blue = { .offset = 10, .length = 5, },
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.transp = { .offset = 15, .length = 1, },
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.bits_per_pixel = 16,
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};
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static const struct ipu_rgb def_rgba_16 = {
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.red = { .offset = 11, .length = 5, },
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.green = { .offset = 6, .length = 5, },
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.blue = { .offset = 1, .length = 5, },
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.transp = { .offset = 0, .length = 1, },
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.bits_per_pixel = 16,
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};
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static const struct ipu_rgb def_bgra_16 = {
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.red = { .offset = 1, .length = 5, },
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.green = { .offset = 6, .length = 5, },
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.blue = { .offset = 11, .length = 5, },
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.transp = { .offset = 0, .length = 1, },
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.bits_per_pixel = 16,
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};
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#define Y_OFFSET(pix, x, y) ((x) + pix->width * (y))
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#define U_OFFSET(pix, x, y) ((pix->width * pix->height) + \
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(pix->width * (y) / 4) + (x) / 2)
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@ -563,11 +619,19 @@ int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc)
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break;
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case DRM_FORMAT_ABGR8888:
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case DRM_FORMAT_XBGR8888:
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ipu_cpmem_set_format_rgb(ch, &def_bgr_32);
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ipu_cpmem_set_format_rgb(ch, &def_xbgr_32);
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break;
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case DRM_FORMAT_ARGB8888:
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case DRM_FORMAT_XRGB8888:
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ipu_cpmem_set_format_rgb(ch, &def_rgb_32);
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ipu_cpmem_set_format_rgb(ch, &def_xrgb_32);
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break;
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case DRM_FORMAT_RGBA8888:
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case DRM_FORMAT_RGBX8888:
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ipu_cpmem_set_format_rgb(ch, &def_rgbx_32);
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break;
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case DRM_FORMAT_BGRA8888:
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case DRM_FORMAT_BGRX8888:
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ipu_cpmem_set_format_rgb(ch, &def_bgrx_32);
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break;
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case DRM_FORMAT_BGR888:
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ipu_cpmem_set_format_rgb(ch, &def_bgr_24);
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@ -581,6 +645,21 @@ int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc)
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case DRM_FORMAT_BGR565:
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ipu_cpmem_set_format_rgb(ch, &def_bgr_16);
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break;
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case DRM_FORMAT_ARGB1555:
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ipu_cpmem_set_format_rgb(ch, &def_argb_16);
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break;
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case DRM_FORMAT_ABGR1555:
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ipu_cpmem_set_format_rgb(ch, &def_abgr_16);
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break;
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case DRM_FORMAT_RGBA5551:
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ipu_cpmem_set_format_rgb(ch, &def_rgba_16);
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break;
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case DRM_FORMAT_BGRA5551:
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ipu_cpmem_set_format_rgb(ch, &def_bgra_16);
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break;
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case DRM_FORMAT_ARGB4444:
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ipu_cpmem_set_format_rgb(ch, &def_argb_16_4444);
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break;
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default:
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return -EINVAL;
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}
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@ -202,7 +202,7 @@ static int ipu_csi_set_testgen_mclk(struct ipu_csi *csi, u32 pixel_clk,
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u32 ipu_clk)
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{
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u32 temp;
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u32 div_ratio;
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int div_ratio;
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div_ratio = (ipu_clk / pixel_clk) - 1;
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@ -271,6 +271,7 @@ static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code)
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case MEDIA_BUS_FMT_SGBRG8_1X8:
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case MEDIA_BUS_FMT_SGRBG8_1X8:
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case MEDIA_BUS_FMT_SRGGB8_1X8:
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case MEDIA_BUS_FMT_Y8_1X8:
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cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
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cfg->mipi_dt = MIPI_DT_RAW8;
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cfg->data_width = IPU_CSI_DATA_WIDTH_8;
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@ -538,7 +539,7 @@ void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
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temp = ipu_csi_read(csi, CSI_TST_CTRL);
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if (active == false) {
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if (!active) {
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temp &= ~CSI_TEST_GEN_MODE_EN;
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ipu_csi_write(csi, temp, CSI_TST_CTRL);
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} else {
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