powerpc/mm: Delete booke bits from book3s
We also move __ASSEMBLY__ towards the end of header. This avoid having #ifndef __ASSEMBLY___ all over the header Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Aneesh Kumar K.V
Michael Ellerman
parent
ab537dca2f
commit
cbbb8683fb
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@ -3,18 +3,10 @@
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#include <asm-generic/pgtable-nopmd.h>
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#ifndef __ASSEMBLY__
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#include <linux/sched.h>
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#include <linux/threads.h>
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#include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */
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#include <asm/book3s/32/hash.h>
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extern unsigned long ioremap_bot;
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#ifdef CONFIG_44x
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extern int icache_44x_need_flush;
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#endif
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#endif /* __ASSEMBLY__ */
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/* And here we include common definitions */
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#include <asm/pte-common.h>
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/*
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* The normal case is that PTEs are 32-bits and we have a 1-page
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@ -31,28 +23,11 @@ extern int icache_44x_need_flush;
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/*
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* entries per page directory level: our page-table tree is two-level, so
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* we don't really have any PMD directory.
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*/
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#ifndef __ASSEMBLY__
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#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_SHIFT)
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#define PGD_TABLE_SIZE (sizeof(pgd_t) << (32 - PGDIR_SHIFT))
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#endif /* __ASSEMBLY__ */
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#define PTRS_PER_PTE (1 << PTE_SHIFT)
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#define PTRS_PER_PMD 1
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#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
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#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
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#define FIRST_USER_ADDRESS 0UL
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#define pte_ERROR(e) \
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pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
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(unsigned long long)pte_val(e))
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#define pgd_ERROR(e) \
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pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
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/*
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* This is the bottom of the PKMAP area with HIGHMEM or an arbitrary
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* value (for now) on others, from where we can start layout kernel
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@ -100,30 +75,30 @@ extern int icache_44x_need_flush;
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#endif
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#define VMALLOC_END ioremap_bot
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#ifndef __ASSEMBLY__
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#include <linux/sched.h>
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#include <linux/threads.h>
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#include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */
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extern unsigned long ioremap_bot;
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/*
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* entries per page directory level: our page-table tree is two-level, so
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* we don't really have any PMD directory.
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*/
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#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_SHIFT)
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#define PGD_TABLE_SIZE (sizeof(pgd_t) << (32 - PGDIR_SHIFT))
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#define pte_ERROR(e) \
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pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
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(unsigned long long)pte_val(e))
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#define pgd_ERROR(e) \
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pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
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/*
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* Bits in a linux-style PTE. These match the bits in the
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* (hardware-defined) PowerPC PTE as closely as possible.
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*/
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#if defined(CONFIG_40x)
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#include <asm/pte-40x.h>
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#elif defined(CONFIG_44x)
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#include <asm/pte-44x.h>
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#elif defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
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#include <asm/pte-book3e.h>
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#elif defined(CONFIG_FSL_BOOKE)
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#include <asm/pte-fsl-booke.h>
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#elif defined(CONFIG_8xx)
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#include <asm/pte-8xx.h>
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#else /* CONFIG_6xx */
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#include <asm/book3s/32/hash.h>
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#endif
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/* And here we include common definitions */
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#include <asm/pte-common.h>
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#ifndef __ASSEMBLY__
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#define pte_clear(mm, addr, ptep) \
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do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
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@ -167,7 +142,6 @@ static inline unsigned long pte_update(pte_t *p,
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unsigned long clr,
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unsigned long set)
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{
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#ifdef PTE_ATOMIC_UPDATES
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unsigned long old, tmp;
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__asm__ __volatile__("\
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@ -180,15 +154,7 @@ static inline unsigned long pte_update(pte_t *p,
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: "=&r" (old), "=&r" (tmp), "=m" (*p)
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: "r" (p), "r" (clr), "r" (set), "m" (*p)
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: "cc" );
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#else /* PTE_ATOMIC_UPDATES */
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unsigned long old = pte_val(*p);
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*p = __pte((old & ~clr) | set);
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#endif /* !PTE_ATOMIC_UPDATES */
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#ifdef CONFIG_44x
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if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
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icache_44x_need_flush = 1;
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#endif
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return old;
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}
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#else /* CONFIG_PTE_64BIT */
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@ -196,7 +162,6 @@ static inline unsigned long long pte_update(pte_t *p,
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unsigned long clr,
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unsigned long set)
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{
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#ifdef PTE_ATOMIC_UPDATES
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unsigned long long old;
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unsigned long tmp;
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@ -211,15 +176,7 @@ static inline unsigned long long pte_update(pte_t *p,
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: "=&r" (old), "=&r" (tmp), "=m" (*p)
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: "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
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: "cc" );
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#else /* PTE_ATOMIC_UPDATES */
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unsigned long long old = pte_val(*p);
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*p = __pte((old & ~(unsigned long long)clr) | set);
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#endif /* !PTE_ATOMIC_UPDATES */
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#ifdef CONFIG_44x
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if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
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icache_44x_need_flush = 1;
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#endif
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return old;
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}
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#endif /* CONFIG_PTE_64BIT */
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@ -233,12 +190,10 @@ static inline int __ptep_test_and_clear_young(unsigned int context, unsigned lon
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{
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unsigned long old;
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old = pte_update(ptep, _PAGE_ACCESSED, 0);
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#if _PAGE_HASHPTE != 0
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if (old & _PAGE_HASHPTE) {
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unsigned long ptephys = __pa(ptep) & PAGE_MASK;
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flush_hash_pages(context, addr, ptephys, 1);
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}
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#endif
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return (old & _PAGE_ACCESSED) != 0;
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}
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#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
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@ -8,7 +8,6 @@
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#include <asm/book3s/64/hash.h>
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#include <asm/barrier.h>
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#define FIRST_USER_ADDRESS 0UL
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/*
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* Size of EA range mapped by our pagetables.
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@ -25,27 +24,16 @@
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/*
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* Define the address range of the kernel non-linear virtual area
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*/
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#ifdef CONFIG_PPC_BOOK3E
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#define KERN_VIRT_START ASM_CONST(0x8000000000000000)
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#else
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#define KERN_VIRT_START ASM_CONST(0xD000000000000000)
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#endif
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#define KERN_VIRT_SIZE ASM_CONST(0x0000100000000000)
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/*
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* The vmalloc space starts at the beginning of that region, and
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* occupies half of it on hash CPUs and a quarter of it on Book3E
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* (we keep a quarter for the virtual memmap)
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*/
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#define VMALLOC_START KERN_VIRT_START
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#ifdef CONFIG_PPC_BOOK3E
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#define VMALLOC_SIZE (KERN_VIRT_SIZE >> 2)
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#else
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#define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1)
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#endif
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#define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE)
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/*
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* The second half of the kernel virtual space is used for IO mappings,
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* it's itself carved into the PIO region (ISA and PHB IO space) and
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@ -64,7 +52,6 @@
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#define IOREMAP_BASE (PHB_IO_END)
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#define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
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/*
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* Region IDs
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*/
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@ -79,32 +66,39 @@
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/*
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* Defines the address of the vmemap area, in its own region on
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* hash table CPUs and after the vmalloc space on Book3E
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* hash table CPUs.
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*/
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#ifdef CONFIG_PPC_BOOK3E
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#define VMEMMAP_BASE VMALLOC_END
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#define VMEMMAP_END KERN_IO_START
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#else
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#define VMEMMAP_BASE (VMEMMAP_REGION_ID << REGION_SHIFT)
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#endif
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#define vmemmap ((struct page *)VMEMMAP_BASE)
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/*
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* Include the PTE bits definitions
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*/
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#ifdef CONFIG_PPC_BOOK3S
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#include <asm/book3s/64/hash.h>
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#else
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#include <asm/pte-book3e.h>
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#endif
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#include <asm/pte-common.h>
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#ifdef CONFIG_PPC_MM_SLICES
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#define HAVE_ARCH_UNMAPPED_AREA
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#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
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#endif /* CONFIG_PPC_MM_SLICES */
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/*
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* THP pages can't be special. So use the _PAGE_SPECIAL
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*/
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#define _PAGE_SPLITTING _PAGE_SPECIAL
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/*
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* We need to differentiate between explicit huge page and THP huge
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* page, since THP huge page also need to track real subpage details
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*/
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#define _PAGE_THP_HUGE _PAGE_4K_PFN
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/*
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* set of bits not changed in pmd_modify.
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*/
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#define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | \
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_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_SPLITTING | \
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_PAGE_THP_HUGE)
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/*
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* Default defines for things which we don't use.
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* We should get this removed.
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*/
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#include <asm/pte-common.h>
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#ifndef __ASSEMBLY__
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/*
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@ -144,7 +138,7 @@
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#define PMD_BAD_BITS (PTE_TABLE_SIZE-1)
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#define PUD_BAD_BITS (PMD_TABLE_SIZE-1)
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#define pmd_set(pmdp, pmdval) (pmd_val(*(pmdp)) = (pmdval))
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#define pmd_set(pmdp, pmdval) (pmd_val(*(pmdp)) = (pmdval))
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#define pmd_none(pmd) (!pmd_val(pmd))
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#define pmd_bad(pmd) (!is_kernel_addr(pmd_val(pmd)) \
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|| (pmd_val(pmd) & PMD_BAD_BITS))
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@ -206,7 +200,6 @@ static inline unsigned long pte_update(struct mm_struct *mm,
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unsigned long set,
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int huge)
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{
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#ifdef PTE_ATOMIC_UPDATES
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unsigned long old, tmp;
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__asm__ __volatile__(
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@ -220,18 +213,12 @@ static inline unsigned long pte_update(struct mm_struct *mm,
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: "=&r" (old), "=&r" (tmp), "=m" (*ptep)
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: "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY), "r" (set)
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: "cc" );
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#else
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unsigned long old = pte_val(*ptep);
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*ptep = __pte((old & ~clr) | set);
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#endif
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/* huge pages use the old page table lock */
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if (!huge)
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assert_pte_locked(mm, addr);
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#ifdef CONFIG_PPC_STD_MMU_64
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if (old & _PAGE_HASHPTE)
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hpte_need_flush(mm, addr, ptep, old, huge);
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#endif
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return old;
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}
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@ -313,7 +300,6 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
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unsigned long bits = pte_val(entry) &
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(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
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#ifdef PTE_ATOMIC_UPDATES
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unsigned long old, tmp;
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__asm__ __volatile__(
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@ -326,10 +312,6 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
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:"=&r" (old), "=&r" (tmp), "=m" (*ptep)
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:"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
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:"cc");
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#else
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unsigned long old = pte_val(*ptep);
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*ptep = __pte(old | bits);
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#endif
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}
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#define __HAVE_ARCH_PTE_SAME
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@ -367,27 +349,7 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
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void pgtable_cache_add(unsigned shift, void (*ctor)(void *));
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void pgtable_cache_init(void);
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#endif /* __ASSEMBLY__ */
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/*
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* THP pages can't be special. So use the _PAGE_SPECIAL
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*/
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#define _PAGE_SPLITTING _PAGE_SPECIAL
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/*
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* We need to differentiate between explicit huge page and THP huge
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* page, since THP huge page also need to track real subpage details
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*/
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#define _PAGE_THP_HUGE _PAGE_4K_PFN
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/*
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* set of bits not changed in pmd_modify.
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*/
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#define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | \
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_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_SPLITTING | \
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_PAGE_THP_HUGE)
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#ifndef __ASSEMBLY__
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/*
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* The linux hugepage PMD now include the pmd entries followed by the address
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* to the stashed pgtable_t. The stashed pgtable_t contains the hpte bits.
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@ -7,4 +7,5 @@
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#include <asm/book3s/32/pgtable.h>
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#endif
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#define FIRST_USER_ADDRESS 0UL
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#endif
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