arm: dts: mediatek: add basic support for MT7629 SoC
This adds basic support for MT7629 reference board. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Ryder Lee
Matthias Brugger
parent
5f9e832c13
commit
cc212241df
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@ -1262,6 +1262,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt7623a-rfb-nand.dtb \
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mt7623n-rfb-emmc.dtb \
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mt7623n-bananapi-bpi-r2.dtb \
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mt7629-rfb.dtb \
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mt8127-moose.dtb \
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mt8135-evbp1.dtb
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dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb
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@ -0,0 +1,263 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include "mt7629.dtsi"
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/ {
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model = "MediaTek MT7629 reference board";
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compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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gpio-keys {
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compatible = "gpio-keys";
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reset {
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label = "factory";
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linux,code = <KEY_RESTART>;
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gpios = <&pio 60 GPIO_ACTIVE_LOW>;
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};
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wps {
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label = "wps";
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linux,code = <KEY_WPS_BUTTON>;
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gpios = <&pio 58 GPIO_ACTIVE_LOW>;
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};
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x40000000 0x10000000>;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_5v: regulator-5v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-5V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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ð {
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pinctrl-names = "default";
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pinctrl-0 = <ð_pins>;
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pinctrl-1 = <&ephy_leds_pins>;
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status = "okay";
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-handle = <&phy0>;
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};
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mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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phy-mode = "gmii";
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};
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};
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};
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&i2c {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c_pins>;
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status = "okay";
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};
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&qspi {
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pinctrl-names = "default";
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pinctrl-0 = <&qspi_pins>;
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x00000 0x60000>;
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read-only;
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};
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partition@60000 {
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label = "u-boot-env";
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reg = <0x60000 0x10000>;
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read-only;
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};
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factory: partition@70000 {
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label = "factory";
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reg = <0x70000 0x40000>;
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read-only;
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};
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partition@b0000 {
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label = "kernel";
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reg = <0xb0000 0xb50000>;
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};
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};
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};
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};
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&pcie {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_pins>;
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};
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&pciephy1 {
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status = "okay";
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};
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&pio {
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eth_pins: eth-pins {
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mux {
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function = "eth";
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groups = "mdc_mdio";
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};
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};
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ephy_leds_pins: ephy-leds-pins {
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mux {
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function = "led";
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groups = "gphy_leds_0", "ephy_leds";
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};
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};
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i2c_pins: i2c-pins {
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mux {
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function = "i2c";
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groups = "i2c_0";
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};
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conf {
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pins = "I2C_SDA", "I2C_SCL";
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drive-strength = <4>;
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bias-disable;
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};
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};
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pcie_pins: pcie-pins {
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mux {
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function = "pcie";
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groups = "pcie_clkreq",
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"pcie_pereset",
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"pcie_wake";
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};
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};
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pwm_pins: pwm-pins {
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mux {
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function = "pwm";
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groups = "pwm_0";
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};
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};
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/* SPI-NOR is shared pin with serial NAND */
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qspi_pins: qspi-pins {
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mux {
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function = "flash";
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groups = "spi_nor";
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};
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};
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/* Serial NAND is shared pin with SPI-NOR */
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serial_nand_pins: serial-nand-pins {
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mux {
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function = "flash";
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groups = "snfi";
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};
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};
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spi_pins: spi-pins {
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mux {
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function = "spi";
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groups = "spi_0";
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};
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};
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uart0_pins: uart0-pins {
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mux {
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function = "uart";
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groups = "uart0_txd_rxd" ;
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};
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};
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uart1_pins: uart1-pins {
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mux {
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function = "uart";
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groups = "uart1_0_tx_rx" ;
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};
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};
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uart2_pins: uart2-pins {
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mux {
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function = "uart";
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groups = "uart2_0_txd_rxd" ;
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};
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};
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watchdog_pins: watchdog-pins {
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mux {
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function = "watchdog";
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groups = "watchdog";
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};
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};
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};
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&spi {
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pinctrl-names = "default";
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pinctrl-0 = <&spi_pins>;
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status = "okay";
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};
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&ssusb {
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vusb33-supply = <®_3p3v>;
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vbus-supply = <®_5v>;
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status = "okay";
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};
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&u3phy0 {
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status = "okay";
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&watchdog {
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pinctrl-names = "default";
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pinctrl-0 = <&watchdog_pins>;
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status = "okay";
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};
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@ -0,0 +1,481 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*
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* Author: Ryder Lee <ryder.lee@mediatek.com>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt7629-clk.h>
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#include <dt-bindings/power/mt7622-power.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/mt7629-resets.h>
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/ {
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compatible = "mediatek,mt7629";
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interrupt-parent = <&sysirq>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "mediatek,mt6589-smp";
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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clock-frequency = <1250000000>;
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cci-control-port = <&cci_control2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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clock-frequency = <1250000000>;
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cci-control-port = <&cci_control2>;
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};
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};
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pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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};
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clk20m: oscillator-0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <20000000>;
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clock-output-names = "clk20m";
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};
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clk40m: oscillator-1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <40000000>;
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clock-output-names = "clkxtal";
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <20000000>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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infracfg: syscon@10000000 {
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compatible = "mediatek,mt7629-infracfg", "syscon";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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};
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pericfg: syscon@10002000 {
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compatible = "mediatek,mt7629-pericfg", "syscon";
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reg = <0x10002000 0x1000>;
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#clock-cells = <1>;
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};
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scpsys: scpsys@10006000 {
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compatible = "mediatek,mt7629-scpsys",
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"mediatek,mt7622-scpsys";
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#power-domain-cells = <1>;
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reg = <0x10006000 0x1000>;
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clocks = <&topckgen CLK_TOP_HIF_SEL>;
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clock-names = "hif_sel";
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assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
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infracfg = <&infracfg>;
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};
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timer: timer@10009000 {
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compatible = "mediatek,mt7629-timer",
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"mediatek,mt6765-timer";
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reg = <0x10009000 0x60>;
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interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk20m>;
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clock-names = "clk20m";
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};
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sysirq: interrupt-controller@10200a80 {
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compatible = "mediatek,mt7629-sysirq",
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"mediatek,mt6577-sysirq";
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reg = <0x10200a80 0x20>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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};
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apmixedsys: syscon@10209000 {
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compatible = "mediatek,mt7629-apmixedsys", "syscon";
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reg = <0x10209000 0x1000>;
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#clock-cells = <1>;
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};
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rng: rng@1020f000 {
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compatible = "mediatek,mt7629-rng",
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"mediatek,mt7623-rng";
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reg = <0x1020f000 0x100>;
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clocks = <&infracfg CLK_INFRA_TRNG_PD>;
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clock-names = "rng";
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};
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topckgen: syscon@10210000 {
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compatible = "mediatek,mt7629-topckgen", "syscon";
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reg = <0x10210000 0x1000>;
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#clock-cells = <1>;
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};
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watchdog: watchdog@10212000 {
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compatible = "mediatek,mt7629-wdt",
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"mediatek,mt6589-wdt";
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reg = <0x10212000 0x100>;
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};
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pio: pinctrl@10217000 {
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compatible = "mediatek,mt7629-pinctrl";
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reg = <0x10217000 0x8000>,
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<0x10005000 0x1000>;
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reg-names = "base", "eint";
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gpio-controller;
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gpio-ranges = <&pio 0 0 79>;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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};
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gic: interrupt-controller@10300000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0x10310000 0x1000>,
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<0x10320000 0x1000>,
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<0x10340000 0x2000>,
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<0x10360000 0x2000>;
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};
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cci: cci@10390000 {
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compatible = "arm,cci-400";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x10390000 0x1000>;
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ranges = <0 0x10390000 0x10000>;
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cci_control0: slave-if@1000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace-lite";
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reg = <0x1000 0x1000>;
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};
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cci_control1: slave-if@4000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x4000 0x1000>;
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};
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cci_control2: slave-if@5000 {
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compatible = "arm,cci-400-ctrl-if";
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interface-type = "ace";
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reg = <0x5000 0x1000>;
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};
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pmu@9000 {
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compatible = "arm,cci-400-pmu,r1";
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reg = <0x9000 0x5000>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt7629-uart",
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"mediatek,mt6577-uart";
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reg = <0x11002000 0x400>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&pericfg CLK_PERI_UART0_PD>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt7629-uart",
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"mediatek,mt6577-uart";
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reg = <0x11003000 0x400>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&pericfg CLK_PERI_UART1_PD>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt7629-uart",
|
||||
"mediatek,mt6577-uart";
|
||||
reg = <0x11004000 0x400>;
|
||||
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_UART_SEL>,
|
||||
<&pericfg CLK_PERI_UART2_PD>;
|
||||
clock-names = "baud", "bus";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c: i2c@11007000 {
|
||||
compatible = "mediatek,mt7629-i2c",
|
||||
"mediatek,mt2712-i2c";
|
||||
reg = <0x11007000 0x90>,
|
||||
<0x11000100 0x80>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
|
||||
clock-div = <4>;
|
||||
clocks = <&pericfg CLK_PERI_I2C0_PD>,
|
||||
<&pericfg CLK_PERI_AP_DMA_PD>;
|
||||
clock-names = "main", "dma";
|
||||
assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi: spi@1100a000 {
|
||||
compatible = "mediatek,mt7629-spi",
|
||||
"mediatek,mt7622-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x1100a000 0x100>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
|
||||
<&topckgen CLK_TOP_SPI0_SEL>,
|
||||
<&pericfg CLK_PERI_SPI0_PD>;
|
||||
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qspi: spi@11014000 {
|
||||
compatible = "mediatek,mt7629-nor",
|
||||
"mediatek,mt8173-nor";
|
||||
reg = <0x11014000 0xe0>;
|
||||
clocks = <&pericfg CLK_PERI_FLASH_PD>,
|
||||
<&topckgen CLK_TOP_FLASH_SEL>;
|
||||
clock-names = "spi", "sf";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssusbsys: syscon@1a000000 {
|
||||
compatible = "mediatek,mt7629-ssusbsys", "syscon";
|
||||
reg = <0x1a000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
ssusb: usb@1a0c0000 {
|
||||
compatible = "mediatek,mt7629-xhci",
|
||||
"mediatek,mtk-xhci";
|
||||
reg = <0x1a0c0000 0x01000>,
|
||||
<0x1a0c3e00 0x0100>;
|
||||
reg-names = "mac", "ippc";
|
||||
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
|
||||
<&ssusbsys CLK_SSUSB_REF_EN>,
|
||||
<&ssusbsys CLK_SSUSB_MCU_EN>,
|
||||
<&ssusbsys CLK_SSUSB_DMA_EN>;
|
||||
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
|
||||
assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
|
||||
<&topckgen CLK_TOP_SATA_SEL>,
|
||||
<&topckgen CLK_TOP_HIF_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
|
||||
<&topckgen CLK_TOP_UNIVPLL2_D4>,
|
||||
<&topckgen CLK_TOP_UNIVPLL1_D2>;
|
||||
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
|
||||
phys = <&u2port0 PHY_TYPE_USB2>,
|
||||
<&u3port0 PHY_TYPE_USB3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
u3phy0: usb-phy@1a0c4000 {
|
||||
compatible = "mediatek,generic-tphy-v2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1a0c4000 0xe00>;
|
||||
status = "disabled";
|
||||
|
||||
u2port0: usb-phy@0 {
|
||||
reg = <0 0x700>;
|
||||
clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
|
||||
clock-names = "ref";
|
||||
#phy-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
u3port0: usb-phy@700 {
|
||||
reg = <0x700 0x700>;
|
||||
clocks = <&clk20m>;
|
||||
clock-names = "ref";
|
||||
#phy-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
pciesys: syscon@1a100800 {
|
||||
compatible = "mediatek,mt7629-pciesys", "syscon";
|
||||
reg = <0x1a100800 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
pcie: pcie@1a140000 {
|
||||
compatible = "mediatek,mt7629-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0x1a140000 0x1000>,
|
||||
<0x1a145000 0x1000>;
|
||||
reg-names = "subsys","port1";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
|
||||
<&pciesys CLK_PCIE_P0_AHB_EN>,
|
||||
<&pciesys CLK_PCIE_P1_AUX_EN>,
|
||||
<&pciesys CLK_PCIE_P1_AXI_EN>,
|
||||
<&pciesys CLK_PCIE_P1_OBFF_EN>,
|
||||
<&pciesys CLK_PCIE_P1_PIPE_EN>;
|
||||
clock-names = "sys_ck1", "ahb_ck1",
|
||||
"aux_ck1", "axi_ck1",
|
||||
"obff_ck1", "pipe_ck1";
|
||||
assigned-clocks = <&topckgen CLK_TOP_SATA_SEL>,
|
||||
<&topckgen CLK_TOP_AXI_SEL>,
|
||||
<&topckgen CLK_TOP_HIF_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>,
|
||||
<&topckgen CLK_TOP_SYSPLL1_D2>,
|
||||
<&topckgen CLK_TOP_UNIVPLL1_D2>;
|
||||
phys = <&pcieport1 PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy1";
|
||||
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
|
||||
|
||||
pcie1: pcie@1,0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
num-lanes = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
||||
<0 0 0 2 &pcie_intc1 1>,
|
||||
<0 0 0 3 &pcie_intc1 2>,
|
||||
<0 0 0 4 &pcie_intc1 3>;
|
||||
|
||||
pcie_intc1: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pciephy1: pcie-phy@1a14a000 {
|
||||
compatible = "mediatek,generic-tphy-v2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1a14a000 0x1000>;
|
||||
status = "disabled";
|
||||
|
||||
pcieport1: port1phy@0 {
|
||||
reg = <0 0x1000>;
|
||||
clocks = <&clk20m>;
|
||||
clock-names = "ref";
|
||||
#phy-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
ethsys: syscon@1b000000 {
|
||||
compatible = "mediatek,mt7629-ethsys", "syscon";
|
||||
reg = <0x1b000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
eth: ethernet@1b100000 {
|
||||
compatible = "mediatek,mt7629-eth","syscon";
|
||||
reg = <0x1b100000 0x20000>;
|
||||
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&topckgen CLK_TOP_ETH_SEL>,
|
||||
<&topckgen CLK_TOP_F10M_REF_SEL>,
|
||||
<ðsys CLK_ETH_ESW_EN>,
|
||||
<ðsys CLK_ETH_GP0_EN>,
|
||||
<ðsys CLK_ETH_GP1_EN>,
|
||||
<ðsys CLK_ETH_GP2_EN>,
|
||||
<ðsys CLK_ETH_FE_EN>,
|
||||
<&sgmiisys0 CLK_SGMII_TX_EN>,
|
||||
<&sgmiisys0 CLK_SGMII_RX_EN>,
|
||||
<&sgmiisys0 CLK_SGMII_CDR_REF>,
|
||||
<&sgmiisys0 CLK_SGMII_CDR_FB>,
|
||||
<&sgmiisys1 CLK_SGMII_TX_EN>,
|
||||
<&sgmiisys1 CLK_SGMII_RX_EN>,
|
||||
<&sgmiisys1 CLK_SGMII_CDR_REF>,
|
||||
<&sgmiisys1 CLK_SGMII_CDR_FB>,
|
||||
<&apmixedsys CLK_APMIXED_SGMIPLL>,
|
||||
<&apmixedsys CLK_APMIXED_ETH2PLL>;
|
||||
clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1",
|
||||
"gp2", "fe", "sgmii_tx250m", "sgmii_rx250m",
|
||||
"sgmii_cdr_ref", "sgmii_cdr_fb",
|
||||
"sgmii2_tx250m", "sgmii2_rx250m",
|
||||
"sgmii2_cdr_ref", "sgmii2_cdr_fb",
|
||||
"sgmii_ck", "eth2pll";
|
||||
assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
|
||||
<&topckgen CLK_TOP_F10M_REF_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
|
||||
<&topckgen CLK_TOP_SGMIIPLL_D2>;
|
||||
power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
|
||||
mediatek,ethsys = <ðsys>;
|
||||
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
|
||||
mediatek,infracfg = <&infracfg>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sgmiisys0: syscon@1b128000 {
|
||||
compatible = "mediatek,mt7629-sgmiisys", "syscon";
|
||||
reg = <0x1b128000 0x3000>;
|
||||
#clock-cells = <1>;
|
||||
mediatek,physpeed = "2500";
|
||||
};
|
||||
|
||||
sgmiisys1: syscon@1b130000 {
|
||||
compatible = "mediatek,mt7629-sgmiisys", "syscon";
|
||||
reg = <0x1b130000 0x3000>;
|
||||
#clock-cells = <1>;
|
||||
mediatek,physpeed = "2500";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2019 MediaTek Inc.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7629
|
||||
#define _DT_BINDINGS_RESET_CONTROLLER_MT7629
|
||||
|
||||
/* INFRACFG resets */
|
||||
#define MT7629_INFRA_EMI_MPU_RST 0
|
||||
#define MT7629_INFRA_UART5_RST 2
|
||||
#define MT7629_INFRA_CIRQ_EINT_RST 3
|
||||
#define MT7629_INFRA_APXGPT_RST 4
|
||||
#define MT7629_INFRA_SCPSYS_RST 5
|
||||
#define MT7629_INFRA_KP_RST 6
|
||||
#define MT7629_INFRA_SPI1_RST 7
|
||||
#define MT7629_INFRA_SPI4_RST 8
|
||||
#define MT7629_INFRA_SYSTIMER_RST 9
|
||||
#define MT7629_INFRA_IRRX_RST 10
|
||||
#define MT7629_INFRA_AO_BUS_RST 16
|
||||
#define MT7629_INFRA_EMI_RST 32
|
||||
#define MT7629_INFRA_APMIXED_RST 35
|
||||
#define MT7629_INFRA_MIPI_RST 36
|
||||
#define MT7629_INFRA_TRNG_RST 37
|
||||
#define MT7629_INFRA_SYSCIRQ_RST 38
|
||||
#define MT7629_INFRA_MIPI_CSI_RST 39
|
||||
#define MT7629_INFRA_GCE_FAXI_RST 40
|
||||
#define MT7629_INFRA_I2C_SRAM_RST 41
|
||||
#define MT7629_INFRA_IOMMU_RST 47
|
||||
|
||||
/* PERICFG resets */
|
||||
#define MT7629_PERI_UART0_SW_RST 0
|
||||
#define MT7629_PERI_UART1_SW_RST 1
|
||||
#define MT7629_PERI_UART2_SW_RST 2
|
||||
#define MT7629_PERI_BTIF_SW_RST 6
|
||||
#define MT7629_PERI_PWN_SW_RST 8
|
||||
#define MT7629_PERI_DMA_SW_RST 11
|
||||
#define MT7629_PERI_NFI_SW_RST 14
|
||||
#define MT7629_PERI_I2C0_SW_RST 22
|
||||
#define MT7629_PERI_SPI0_SW_RST 33
|
||||
#define MT7629_PERI_SPI1_SW_RST 34
|
||||
#define MT7629_PERI_FLASHIF_SW_RST 36
|
||||
|
||||
/* PCIe Subsystem resets */
|
||||
#define MT7629_PCIE1_CORE_RST 19
|
||||
#define MT7629_PCIE1_MMIO_RST 20
|
||||
#define MT7629_PCIE1_HRST 21
|
||||
#define MT7629_PCIE1_USER_RST 22
|
||||
#define MT7629_PCIE1_PIPE_RST 23
|
||||
#define MT7629_PCIE0_CORE_RST 27
|
||||
#define MT7629_PCIE0_MMIO_RST 28
|
||||
#define MT7629_PCIE0_HRST 29
|
||||
#define MT7629_PCIE0_USER_RST 30
|
||||
#define MT7629_PCIE0_PIPE_RST 31
|
||||
|
||||
/* SSUSB Subsystem resets */
|
||||
#define MT7629_SSUSB_PHY_PWR_RST 3
|
||||
#define MT7629_SSUSB_MAC_PWR_RST 4
|
||||
|
||||
/* ETH Subsystem resets */
|
||||
#define MT7629_ETHSYS_SYS_RST 0
|
||||
#define MT7629_ETHSYS_MCM_RST 2
|
||||
#define MT7629_ETHSYS_HSDMA_RST 5
|
||||
#define MT7629_ETHSYS_FE_RST 6
|
||||
#define MT7629_ETHSYS_ESW_RST 16
|
||||
#define MT7629_ETHSYS_GMAC_RST 23
|
||||
#define MT7629_ETHSYS_EPHY_RST 24
|
||||
#define MT7629_ETHSYS_CRYPTO_RST 29
|
||||
#define MT7629_ETHSYS_PPE_RST 31
|
||||
|
||||
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7629 */
|
||||
Loading…
Reference in New Issue