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clk: samsung: add needed IDs for DMC clocks in Exynos5420 

Define new IDs for clocks used by Dynamic Memory Controller in
Exynos5422 SoC.

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Lukasz Luba 2019-06-05 18:53:58 +02:00 committed by Sylwester Nawrocki
parent c304b8d2f9
commit cc9bdecf4b
1 changed files with 17 additions and 1 deletions
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18
include/dt-bindings/clock/exynos5420.h
View File

@ -60,6 +60,7 @@
#define CLK_MAU_EPLL 159
#define CLK_SCLK_HSIC_12M 160
#define CLK_SCLK_MPHY_IXTAL24 161
#define CLK_SCLK_BPLL 162
/* gate clocks */
#define CLK_UART0 257
@ -195,6 +196,16 @@
#define CLK_ACLK432_CAM 518
#define CLK_ACLK_FL1550_CAM 519
#define CLK_ACLK550_CAM 520
#define CLK_CLKM_PHY0 521
#define CLK_CLKM_PHY1 522
#define CLK_ACLK_PPMU_DREX0_0 523
#define CLK_ACLK_PPMU_DREX0_1 524
#define CLK_ACLK_PPMU_DREX1_0 525
#define CLK_ACLK_PPMU_DREX1_1 526
#define CLK_PCLK_PPMU_DREX0_0 527
#define CLK_PCLK_PPMU_DREX0_1 528
#define CLK_PCLK_PPMU_DREX1_0 529
#define CLK_PCLK_PPMU_DREX1_1 530
/* mux clocks */
#define CLK_MOUT_HDMI 640
@ -217,6 +228,8 @@
#define CLK_MOUT_EPLL 657
#define CLK_MOUT_MAU_EPLL 658
#define CLK_MOUT_USER_MAU_EPLL 659
#define CLK_MOUT_SCLK_SPLL 660
#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661
/* divider clocks */
#define CLK_DOUT_PIXEL 768
@ -248,8 +261,11 @@
#define CLK_DOUT_CCLK_DREX0 794
#define CLK_DOUT_CLK2X_PHY0 795
#define CLK_DOUT_PCLK_CORE_MEM 796
#define CLK_FF_DOUT_SPLL2 797
#define CLK_DOUT_PCLK_DREX0 798
#define CLK_DOUT_PCLK_DREX1 799
/* must be greater than maximal clock id */
#define CLK_NR_CLKS 797
#define CLK_NR_CLKS 800
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */