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Merge branches 'pci/host-designware', 'pci/host-xgene' and 'pci/host-xilinx' into next 

* pci/host-designware:
  PCI: designware: Don't complain missing *config* reg space if va_cfg0 is set

* pci/host-xgene:
  PCI: xgene: Add support for a 64-bit prefetchable memory window
  arm64: dts: Add APM X-Gene PCIe 64-bit prefetchable window
  PCI: xgene: Drop owner assignment from platform_driver

* pci/host-xilinx:
  PCI: xilinx: Check for MSI interrupt flag before handling as INTx
This commit is contained in:
Bjorn Helgaas 2015-08-04 20:52:29 -05:00
parent bc0195aad0 0f41421256 8ef54f27f6 e4a8f8ee89
commit cd66d5c3df
5 changed files with 35 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
arch/arm64/boot/dts/apm/apm-storm.dtsi
View File

@ -490,7 +490,8 @@ pcie0: pcie@1f2b0000 {
0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
reg-names = "csr", "cfg"; reg-names = "csr", "cfg";
ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */ 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */
0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map-mask = <0x0 0x0 0x0 0x7>;
@ -513,8 +514,9 @@ pcie1: pcie@1f2c0000 {
reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */
0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
reg-names = "csr", "cfg"; reg-names = "csr", "cfg";
ranges = <0x01000000 0x0 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */ ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */
0x02000000 0x0 0x80000000 0xd1 0x80000000 0x00 0x80000000>; /* mem */ 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */
0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map-mask = <0x0 0x0 0x0 0x7>;
@ -537,8 +539,9 @@ pcie2: pcie@1f2d0000 {
reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */ reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */
0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */ 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
reg-names = "csr", "cfg"; reg-names = "csr", "cfg";
ranges = <0x01000000 0x0 0x00000000 0x90 0x10000000 0x0 0x00010000 /* io */ ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */
0x02000000 0x0 0x80000000 0x91 0x80000000 0x0 0x80000000>; /* mem */ 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */
0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map-mask = <0x0 0x0 0x0 0x7>;
@ -561,8 +564,9 @@ pcie3: pcie@1f500000 {
reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */ reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */
0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
reg-names = "csr", "cfg"; reg-names = "csr", "cfg";
ranges = <0x01000000 0x0 0x00000000 0xa0 0x10000000 0x0 0x00010000 /* io */ ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */
0x02000000 0x0 0x80000000 0xa1 0x80000000 0x0 0x80000000>; /* mem */ 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */
0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map-mask = <0x0 0x0 0x0 0x7>;
@ -585,8 +589,9 @@ pcie4: pcie@1f510000 {
reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */ reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */
0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */ 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
reg-names = "csr", "cfg"; reg-names = "csr", "cfg";
ranges = <0x01000000 0x0 0x00000000 0xc0 0x10000000 0x0 0x00010000 /* io */ ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */
0x02000000 0x0 0x80000000 0xc1 0x80000000 0x0 0x80000000>; /* mem */ 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */
0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map-mask = <0x0 0x0 0x0 0x7>;

1
drivers/pci/host/pci-xgene-msi.c
View File

@ -582,7 +582,6 @@ static int xgene_msi_probe(struct platform_device *pdev)
static struct platform_driver xgene_msi_driver = { static struct platform_driver xgene_msi_driver = {
.driver = { .driver = {
.name = "xgene-msi", .name = "xgene-msi",
.owner = THIS_MODULE,
.of_match_table = xgene_msi_match_table, .of_match_table = xgene_msi_match_table,
}, },
.probe = xgene_msi_probe, .probe = xgene_msi_probe,

12
drivers/pci/host/pci-xgene.c
View File

@ -321,8 +321,16 @@ static int xgene_pcie_map_ranges(struct xgene_pcie_port *port,
return ret; return ret;
break; break;
case IORESOURCE_MEM: case IORESOURCE_MEM:
xgene_pcie_setup_ob_reg(port, res, OMR1BARL, res->start, if (res->flags & IORESOURCE_PREFETCH)
res->start - window->offset); xgene_pcie_setup_ob_reg(port, res, OMR2BARL,
res->start,
res->start -
window->offset);
else
xgene_pcie_setup_ob_reg(port, res, OMR1BARL,
res->start,
res->start -
window->offset);
break; break;
case IORESOURCE_BUS: case IORESOURCE_BUS:
break; break;

2
drivers/pci/host/pcie-designware.c
View File

@ -388,7 +388,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
addrp = of_get_address(np, index, NULL, NULL); addrp = of_get_address(np, index, NULL, NULL);
pp->cfg0_mod_base = of_read_number(addrp, ns); pp->cfg0_mod_base = of_read_number(addrp, ns);
pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size; pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size;
} else { } else if (!pp->va_cfg0_base) {
dev_err(pp->dev, "missing *config* reg space\n"); dev_err(pp->dev, "missing *config* reg space\n");
} }

5
drivers/pci/host/pcie-xilinx.c
View File

@ -449,6 +449,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
return IRQ_HANDLED; return IRQ_HANDLED;
} }
if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) {
/* Clear interrupt FIFO register 1 */ /* Clear interrupt FIFO register 1 */
pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
XILINX_PCIE_REG_RPIFR1); XILINX_PCIE_REG_RPIFR1);
@ -456,7 +457,9 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
/* Handle INTx Interrupt */ /* Handle INTx Interrupt */
val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >> val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1; XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
generic_handle_irq(irq_find_mapping(port->irq_domain, val)); generic_handle_irq(irq_find_mapping(port->irq_domain,
val));
}
} }
if (status & XILINX_PCIE_INTR_MSI) { if (status & XILINX_PCIE_INTR_MSI) {