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mtd: nand: pxa3xx: Handle ECC and DMA enable/disable properly 

When ECC is not selected, the ECC enable bit must be cleared
in the NAND control register. Same applies to DMA.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Ezequiel Garcia 2013-08-12 14:14:48 -03:00 committed by David Woodhouse
parent c0f3b8643a
commit cd9d11820f
1 changed files with 11 additions and 2 deletions
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13
drivers/mtd/nand/pxa3xx_nand.c
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@ -314,8 +314,17 @@ static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
uint32_t ndcr;
ndcr = host->reg_ndcr;
ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
if (info->use_ecc)
ndcr |= NDCR_ECC_EN;
else
ndcr &= ~NDCR_ECC_EN;
if (info->use_dma)
ndcr |= NDCR_DMA_EN;
else
ndcr &= ~NDCR_DMA_EN;
ndcr |= NDCR_ND_RUN;
/* clear status bits and run */