ARM: SAMSUNG: Remove unused register offset definition
This patch cleans up various map.h under mach-exynos, mach-s3c24xx and plat-samsung by removing unused register offset. This patch also does a minor nitpick of changing EXYNOS4 to EXYNOS from comment section of header file "mach-exynos/include/mach/map.h". Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
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@ -2,7 +2,7 @@
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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* http://www.samsung.com/
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*
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*
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* EXYNOS4 - Memory map definitions
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* EXYNOS - Memory map definitions
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* it under the terms of the GNU General Public License version 2 as
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@ -14,12 +14,6 @@
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#include <plat/map-base.h>
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#include <plat/map-base.h>
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/*
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* EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
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* So need to define it, and here is to avoid redefinition warning.
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*/
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#define S3C_UART_OFFSET (0x10000)
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#include <plat/map-s5p.h>
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#include <plat/map-s5p.h>
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#define EXYNOS_PA_CHIPID 0x10000000
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#define EXYNOS_PA_CHIPID 0x10000000
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#define EXYNOS4_PA_DMC1 0x10410000
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#define EXYNOS4_PA_DMC1 0x10410000
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#define EXYNOS4_PA_COREPERI 0x10500000
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#define EXYNOS4_PA_COREPERI 0x10500000
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#define EXYNOS4_PA_L2CC 0x10502000
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#define EXYNOS4_PA_SROMC 0x12570000
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#define EXYNOS4_PA_SROMC 0x12570000
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#define EXYNOS5_PA_SROMC 0x12250000
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#define EXYNOS5_PA_SROMC 0x12250000
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@ -14,13 +14,6 @@
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#define __ASM_ARCH_MAP_H
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#define __ASM_ARCH_MAP_H
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#include <plat/map-base.h>
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#include <plat/map-base.h>
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/*
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* S3C2410 UART offset is 0x4000 but the other SoCs are 0x400.
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* So need to define it, and here is to avoid redefinition warning.
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*/
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#define S3C_UART_OFFSET (0x4000)
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#include <plat/map-s3c.h>
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#include <plat/map-s3c.h>
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/*
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/*
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@ -34,9 +27,6 @@
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#define S3C2410_PA_MEMCTRL (0x48000000)
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#define S3C2410_PA_MEMCTRL (0x48000000)
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#define S3C24XX_SZ_MEMCTRL SZ_1M
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#define S3C24XX_SZ_MEMCTRL SZ_1M
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/* UARTs */
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#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
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/* Timers */
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/* Timers */
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#define S3C2410_PA_TIMER (0x51000000)
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#define S3C2410_PA_TIMER (0x51000000)
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#define S3C24XX_SZ_TIMER SZ_1M
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#define S3C24XX_SZ_TIMER SZ_1M
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#define S3C_PA_FB S3C2443_PA_FB
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#define S3C_PA_FB S3C2443_PA_FB
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#define S3C_PA_IIC S3C2410_PA_IIC
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#define S3C_PA_IIC S3C2410_PA_IIC
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#define S3C_PA_UART S3C24XX_PA_UART
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#define S3C_PA_USBHOST S3C2410_PA_USBHOST
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#define S3C_PA_USBHOST S3C2410_PA_USBHOST
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#define S3C_PA_HSMMC0 S3C2416_PA_HSMMC0
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#define S3C_PA_HSMMC0 S3C2416_PA_HSMMC0
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#define S3C_PA_HSMMC1 S3C2443_PA_HSMMC
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#define S3C_PA_HSMMC1 S3C2443_PA_HSMMC
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#define S3C2410_PA_UART (0x50000000)
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#define S3C2410_PA_UART (0x50000000)
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#define S3C24XX_PA_UART S3C2410_PA_UART
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#define S3C24XX_PA_UART S3C2410_PA_UART
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#ifndef S3C_UART_OFFSET
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#define S3C_UART_OFFSET (0x400)
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#endif
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/*
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/*
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* GPIO ports
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* GPIO ports
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*
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*
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#define S5P_VA_COREPERI_BASE S3C_ADDR(0x02800000)
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#define S5P_VA_COREPERI_BASE S3C_ADDR(0x02800000)
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#define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x))
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#define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x))
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#define S5P_VA_SCU S5P_VA_COREPERI(0x0)
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#define S5P_VA_SCU S5P_VA_COREPERI(0x0)
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#define S5P_VA_TWD S5P_VA_COREPERI(0x600)
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#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
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#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
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#define VA_VIC0 VA_VIC(0)
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#define VA_VIC0 VA_VIC(0)
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#define VA_VIC2 VA_VIC(2)
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#define VA_VIC2 VA_VIC(2)
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#define VA_VIC3 VA_VIC(3)
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#define VA_VIC3 VA_VIC(3)
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#ifndef S3C_UART_OFFSET
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#define S3C_UART_OFFSET (0x400)
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#endif
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#include <plat/map-s3c.h>
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#include <plat/map-s3c.h>
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#endif /* __ASM_PLAT_MAP_S5P_H */
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#endif /* __ASM_PLAT_MAP_S5P_H */
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