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Merge tag 'gvt-next-2016-11-30' of https://github.com/01org/gvt-linux into drm-intel-next-fixes 

From Zhenyu Wang <zhenyuw@linux.intel.com>

gvt-next-2016-11-30

- initialize vgpu as primary for correct cfg space setting
- fix 64 bit bar emulation
- fix un-released lock issue on dispatch workload err path

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula 2016-12-02 16:29:07 +02:00
parent e9cbc4bd01 53d6f812c0
commit cf30f5094a
3 changed files with 9 additions and 4 deletions
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2
drivers/gpu/drm/i915/gvt/gvt.h
View File

@ -361,6 +361,8 @@ static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,
* leave the bit 3 - bit 0 unchanged.
*/
*pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));
} else {
*pval = val;
}
}

10
drivers/gpu/drm/i915/gvt/scheduler.c
View File

@ -177,8 +177,8 @@ static int dispatch_workload(struct intel_vgpu_workload *workload)
rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx);
if (IS_ERR(rq)) {
gvt_err("fail to allocate gem request\n");
workload->status = PTR_ERR(rq);
return workload->status;
ret = PTR_ERR(rq);
goto out;
}
gvt_dbg_sched("ring id %d get i915 gem request %p\n", ring_id, rq);
@ -212,7 +212,8 @@ static int dispatch_workload(struct intel_vgpu_workload *workload)
if (ret)
workload->status = ret;
i915_add_request_no_flush(rq);
if (!IS_ERR_OR_NULL(rq))
i915_add_request_no_flush(rq);
mutex_unlock(&dev_priv->drm.struct_mutex);
return ret;
}
@ -460,7 +461,8 @@ static int workload_thread(void *priv)
complete_current_workload(gvt, ring_id);
i915_gem_request_put(fetch_and_zero(&workload->req));
if (workload->req)
i915_gem_request_put(fetch_and_zero(&workload->req));
if (need_force_wake)
intel_uncore_forcewake_put(gvt->dev_priv,

1
drivers/gpu/drm/i915/gvt/vgpu.c
View File

@ -378,6 +378,7 @@ struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
struct intel_vgpu *vgpu;
param.handle = 0;
param.primary = 1;
param.low_gm_sz = type->low_gm_size;
param.high_gm_sz = type->high_gm_size;
param.fence_sz = type->fence;