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dmaengine: ti-dma-crossbar: Fix event mapping for TPCC_EVT_MUX_60_63 

Register layout of a typical TPCC_EVT_MUX_M_N register is such that the
lowest numbered event is at the lowest byte address and highest numbered
event at highest byte address. But TPCC_EVT_MUX_60_63 register layout is
different,  in that the lowest numbered event is at the highest address
and highest numbered event is at the lowest address. Therefore, modify
ti_am335x_xbar_write() to handle TPCC_EVT_MUX_60_63 register
accordingly.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Vignesh R 2017-12-19 12:51:16 +02:00 committed by Vinod Koul
parent 4fbd8d194f
commit d087f15786
1 changed files with 9 additions and 1 deletions
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8
drivers/dma/ti-dma-crossbar.c
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@ -54,6 +54,14 @@ struct ti_am335x_xbar_map {
static inline void ti_am335x_xbar_write(void __iomem *iomem, int event, u8 val)
{
/*
* TPCC_EVT_MUX_60_63 register layout is different than the
* rest, in the sense, that event 63 is mapped to lowest byte
* and event 60 is mapped to highest, handle it separately.
*/
if (event >= 60 && event <= 63)
writeb_relaxed(val, iomem + (63 - event % 4));
else
writeb_relaxed(val, iomem + event);
}