drm/vc4: Set up SCALER_DISPCTRL at boot.
We want the HVS on, obviously, and we also want DSP3 (PV1's source) to be muxed from HVS channel 2 like we expect in vc4_crtc.c. The firmware wasn't setting the DSP3 mux up when both the LCD and HDMI were disabled. Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20161214194621.16499-5-eric@anholt.net
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@ -170,6 +170,7 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
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struct vc4_dev *vc4 = drm->dev_private;
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struct vc4_dev *vc4 = drm->dev_private;
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struct vc4_hvs *hvs = NULL;
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struct vc4_hvs *hvs = NULL;
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int ret;
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int ret;
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u32 dispctrl;
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hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL);
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hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL);
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if (!hvs)
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if (!hvs)
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@ -211,6 +212,19 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
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return ret;
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return ret;
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vc4->hvs = hvs;
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vc4->hvs = hvs;
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dispctrl = HVS_READ(SCALER_DISPCTRL);
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dispctrl |= SCALER_DISPCTRL_ENABLE;
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/* Set DSP3 (PV1) to use HVS channel 2, which would otherwise
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* be unused.
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*/
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dispctrl &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
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dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
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HVS_WRITE(SCALER_DISPCTRL, dispctrl);
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return 0;
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return 0;
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}
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}
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@ -244,6 +244,9 @@
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# define SCALER_DISPCTRL_ENABLE BIT(31)
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# define SCALER_DISPCTRL_ENABLE BIT(31)
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# define SCALER_DISPCTRL_DSP2EISLUR BIT(15)
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# define SCALER_DISPCTRL_DSP2EISLUR BIT(15)
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# define SCALER_DISPCTRL_DSP1EISLUR BIT(14)
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# define SCALER_DISPCTRL_DSP1EISLUR BIT(14)
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# define SCALER_DISPCTRL_DSP3_MUX_MASK VC4_MASK(19, 18)
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# define SCALER_DISPCTRL_DSP3_MUX_SHIFT 18
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/* Enables Display 0 short line and underrun contribution to
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/* Enables Display 0 short line and underrun contribution to
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* SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are
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* SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are
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* always enabled.
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* always enabled.
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