- Add bindings for mtk-scpsys for mt2701
- Add clocks for auxadc on mt8173-evb - Add nodes needed by clock controller for mt2701 - Use clocks from the clock controller for the uart of mt2701 -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABAgAGBQJYJdcrAAoJELQ5Ylss8dNDoJcP/2q1LuStbojWMWxFKexQBCIk 8VEPzY8fyEckshbmgnz36qqp2MnecTLjb1ETesFIEGZWbEBnoAJC9hyIg6fFVZQi mFZC8/0I7uvaFZHa+a3fQZb3tCmLMcWbAaGvA0p28kNRKnRhTMVHhLa7Z0WmMrG+ lQLlBBTP/xHErOakFJagkFIWYmmmMReS7x+X/tnVPienxkwODjpLYJQLL1wVmoqV lpSj/nSRRDg8CeeG8/x+Odtr77L56glDMwwieXVpBe2sd+CpRk3QSTTcuYLkUp46 JBBKrr7TLLD6KEw6FgPjvjWDR3TH7S2wkbZVJN4B+8tmdEhpQhnle2MpJ6TYLKQb ENwZ9JP70UD8o6mWb5e/g9R82WxUq1KDpdlU71OeBsnqfJRn1sge8bsO6+qs4+6Z JapDW+Zwsewp9VZS12k4VdsCsYR0MZgX6XXj/NOOseJOMUXBFAoHj7vaC5Gj0UIT VFKndrzWjIaVbaLHA/2KyVvOpJsEVTwSURyEko6XnTRLg+E85SSx+r6Bp3rlSlCV Javet8M9YTLhPa1IeFMvf/1V4C4poX5tE4tvCiSZC1Wvxto5FSEgeGarq59Pgyi3 UWnxao8FHBHi3NU8khTI+rnIYtw5WxkEpqU5UUTYMUwsQ3x83VnU0WzpCSKQSNdD Od24wmc/rrNKeU098abr =wFjD -----END PGP SIGNATURE----- Merge tag 'v4.9-next-dts' of https://github.com/mbgg/linux-mediatek into next/dt - Add bindings for mtk-scpsys for mt2701 - Add clocks for auxadc on mt8173-evb - Add nodes needed by clock controller for mt2701 - Use clocks from the clock controller for the uart of mt2701 * tag 'v4.9-next-dts' of https://github.com/mbgg/linux-mediatek: arm: dts: mt2701: Use real clock for UARTs arm: dts: mt2701: Add clock controller device nodes arm64: dts: mt8173: Fix auxadc node soc: mediatek: Add MT2701 power dt-bindings Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
d2e7d59028
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@ -9,17 +9,20 @@ domain control.
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The driver implements the Generic PM domain bindings described in
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power/power_domain.txt. It provides the power domains defined in
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include/dt-bindings/power/mt8173-power.h.
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include/dt-bindings/power/mt8173-power.h and mt2701-power.h.
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Required properties:
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- compatible: Must be "mediatek,mt8173-scpsys"
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- compatible: Should be one of:
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- "mediatek,mt2701-scpsys"
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- "mediatek,mt8173-scpsys"
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- #power-domain-cells: Must be 1
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- reg: Address range of the SCPSYS unit
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- infracfg: must contain a phandle to the infracfg controller
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- clock, clock-names: clocks according to the common clock binding.
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The clocks needed "mm", "mfg", "venc" and "venc_lt".
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These are the clocks which hardware needs to be enabled
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before enabling certain power domains.
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These are clocks which hardware needs to be
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enabled before enabling certain power domains.
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Required clocks for MT2701: "mm", "mfg", "ethif"
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Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
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Optional properties:
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- vdec-supply: Power supply for the vdec power domain
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@ -12,8 +12,10 @@
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/clock/mt2701-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/mt2701-resets.h>
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#include "skeleton64.dtsi"
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#include "mt2701-pinfunc.h"
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@ -71,10 +73,18 @@ rtc_clk: dummy32k {
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#clock-cells = <0>;
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};
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uart_clk: dummy26m {
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clk26m: oscillator@0 {
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compatible = "fixed-clock";
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clock-frequency = <26000000>;
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "clk26m";
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};
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rtc32k: oscillator@1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32000>;
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clock-output-names = "rtc32k";
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};
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timer {
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@ -104,6 +114,26 @@ syscfg_pctl_a: syscfg@10005000 {
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reg = <0 0x10005000 0 0x1000>;
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};
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topckgen: syscon@10000000 {
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compatible = "mediatek,mt2701-topckgen", "syscon";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: syscon@10001000 {
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compatible = "mediatek,mt2701-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pericfg: syscon@10003000 {
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compatible = "mediatek,mt2701-pericfg", "syscon";
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reg = <0 0x10003000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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watchdog: watchdog@10007000 {
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compatible = "mediatek,mt2701-wdt",
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"mediatek,mt6589-wdt";
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@ -128,6 +158,12 @@ sysirq: interrupt-controller@10200100 {
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reg = <0 0x10200100 0 0x1c>;
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};
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apmixedsys: syscon@10209000 {
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compatible = "mediatek,mt2701-apmixedsys", "syscon";
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reg = <0 0x10209000 0 0x1000>;
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#clock-cells = <1>;
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};
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gic: interrupt-controller@10211000 {
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compatible = "arm,cortex-a7-gic";
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interrupt-controller;
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@ -144,7 +180,8 @@ uart0: serial@11002000 {
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"mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x400>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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@ -153,7 +190,8 @@ uart1: serial@11003000 {
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"mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x400>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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@ -162,7 +200,8 @@ uart2: serial@11004000 {
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"mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x400>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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@ -171,7 +210,8 @@ uart3: serial@11005000 {
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"mediatek,mt6577-uart";
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reg = <0 0x11005000 0 0x400>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&uart_clk>;
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clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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};
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@ -450,6 +450,9 @@ gic: interrupt-controller@10220000 {
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auxadc: auxadc@11001000 {
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compatible = "mediatek,mt8173-auxadc";
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reg = <0 0x11001000 0 0x1000>;
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clocks = <&pericfg CLK_PERI_AUXADC>;
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clock-names = "main";
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#io-channel-cells = <1>;
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};
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uart0: serial@11002000 {
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@ -0,0 +1,27 @@
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/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_POWER_MT2701_POWER_H
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#define _DT_BINDINGS_POWER_MT2701_POWER_H
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#define MT2701_POWER_DOMAIN_CONN 0
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#define MT2701_POWER_DOMAIN_DISP 1
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#define MT2701_POWER_DOMAIN_MFG 2
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#define MT2701_POWER_DOMAIN_VDEC 3
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#define MT2701_POWER_DOMAIN_ISP 4
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#define MT2701_POWER_DOMAIN_BDP 5
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#define MT2701_POWER_DOMAIN_ETH 6
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#define MT2701_POWER_DOMAIN_HIF 7
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#define MT2701_POWER_DOMAIN_IFR_MSC 8
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#endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */
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