p71924506
/
linux_old1
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

drm/amd/powerplay: add SMU71 header files for iceland (v2) 

v2: cleanup headers, add copyright

Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Huang Rui 2016-06-21 10:26:26 +08:00 committed by Alex Deucher
parent 37ac235bf8
commit d31d3c28c7
2 changed files with 1141 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

510
drivers/gpu/drm/amd/powerplay/inc/smu71.h Normal file
View File

@ -0,0 +1,510 @@
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU71_H
#define SMU71_H
#if !defined(SMC_MICROCODE)
#pragma pack(push, 1)
#endif
#define SMU__NUM_PCIE_DPM_LEVELS 8
#define SMU__NUM_SCLK_DPM_STATE 8
#define SMU__NUM_MCLK_DPM_LEVELS 4
#define SMU__VARIANT__ICELAND 1
#define SMU__DGPU_ONLY 1
#define SMU__DYNAMIC_MCARB_SETTINGS 1
enum SID_OPTION {
SID_OPTION_HI,
SID_OPTION_LO,
SID_OPTION_COUNT
};
typedef struct {
uint32_t high;
uint32_t low;
} data_64_t;
typedef struct {
data_64_t high;
data_64_t low;
} data_128_t;
#define SMU7_CONTEXT_ID_SMC 1
#define SMU7_CONTEXT_ID_VBIOS 2
#define SMU71_MAX_LEVELS_VDDC 8
#define SMU71_MAX_LEVELS_VDDCI 4
#define SMU71_MAX_LEVELS_MVDD 4
#define SMU71_MAX_LEVELS_VDDNB 8
#define SMU71_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE
#define SMU71_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS
#define SMU71_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS
#define SMU71_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS
#define SMU71_MAX_ENTRIES_SMIO 32
#define DPM_NO_LIMIT 0
#define DPM_NO_UP 1
#define DPM_GO_DOWN 2
#define DPM_GO_UP 3
#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0
#define SMU7_FIRST_DPM_MEMORY_LEVEL 0
#define GPIO_CLAMP_MODE_VRHOT 1
#define GPIO_CLAMP_MODE_THERM 2
#define GPIO_CLAMP_MODE_DC 4
#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6
#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9
#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12
#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15
#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18
#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21
#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
#if defined SMU__DGPU_ONLY
#define SMU71_DTE_ITERATIONS 5
#define SMU71_DTE_SOURCES 3
#define SMU71_DTE_SINKS 1
#define SMU71_NUM_CPU_TES 0
#define SMU71_NUM_GPU_TES 1
#define SMU71_NUM_NON_TES 2
#endif
#if defined SMU__FUSION_ONLY
#define SMU7_DTE_ITERATIONS 5
#define SMU7_DTE_SOURCES 5
#define SMU7_DTE_SINKS 3
#define SMU7_NUM_CPU_TES 2
#define SMU7_NUM_GPU_TES 1
#define SMU7_NUM_NON_TES 2
#endif
struct SMU71_PIDController
{
uint32_t Ki;
int32_t LFWindupUpperLim;
int32_t LFWindupLowerLim;
uint32_t StatePrecision;
uint32_t LfPrecision;
uint32_t LfOffset;
uint32_t MaxState;
uint32_t MaxLfFraction;
uint32_t StateShift;
};
typedef struct SMU71_PIDController SMU71_PIDController;
struct SMU7_LocalDpmScoreboard
{
uint32_t PercentageBusy;
int32_t PIDError;
int32_t PIDIntegral;
int32_t PIDOutput;
uint32_t SigmaDeltaAccum;
uint32_t SigmaDeltaOutput;
uint32_t SigmaDeltaLevel;
uint32_t UtilizationSetpoint;
uint8_t TdpClampMode;
uint8_t TdcClampMode;
uint8_t ThermClampMode;
uint8_t VoltageBusy;
int8_t CurrLevel;
int8_t TargLevel;
uint8_t LevelChangeInProgress;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint32_t MinimumPerfSclk;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t GfxClkSlow;
uint8_t GpioClampMode;
uint8_t FpsFilterWeight;
uint8_t EnabledLevelsChange;
uint8_t DteClampMode;
uint8_t FpsClampMode;
uint16_t LevelResidencyCounters [SMU71_MAX_LEVELS_GRAPHICS];
uint16_t LevelSwitchCounters [SMU71_MAX_LEVELS_GRAPHICS];
void (*TargetStateCalculator)(uint8_t);
void (*SavedTargetStateCalculator)(uint8_t);
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint8_t FpsEnabled;
uint8_t MaxPerfLevel;
uint8_t AllowLowClkInterruptToHost;
uint8_t FpsRunning;
uint32_t MaxAllowedFrequency;
};
typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
#define SMU7_MAX_VOLTAGE_CLIENTS 12
struct SMU7_VoltageScoreboard
{
uint16_t CurrentVoltage;
uint16_t HighestVoltage;
uint16_t MaxVid;
uint8_t HighestVidOffset;
uint8_t CurrentVidOffset;
#if defined (SMU__DGPU_ONLY)
uint8_t CurrentPhases;
uint8_t HighestPhases;
#else
uint8_t AvsOffset;
uint8_t AvsOffsetApplied;
#endif
uint8_t ControllerBusy;
uint8_t CurrentVid;
uint16_t RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
#if defined (SMU__DGPU_ONLY)
uint8_t RequestedPhases[SMU7_MAX_VOLTAGE_CLIENTS];
#endif
uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
uint8_t TargetIndex;
uint8_t Delay;
uint8_t ControllerEnable;
uint8_t ControllerRunning;
uint16_t CurrentStdVoltageHiSidd;
uint16_t CurrentStdVoltageLoSidd;
#if defined (SMU__DGPU_ONLY)
uint16_t RequestedVddci;
uint16_t CurrentVddci;
uint16_t HighestVddci;
uint8_t CurrentVddciVid;
uint8_t TargetVddciIndex;
#endif
};
typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
// -------------------------------------------------------------------------------------------------------------------------
#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
struct SMU7_PCIeLinkSpeedScoreboard
{
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t CurrentLinkSpeed;
uint8_t EnabledLevelsChange;
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint16_t AutoDpmCount;
uint8_t DpmMode;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t CurrentLinkLevel;
};
typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
// -------------------------------------------------------- CAC table ------------------------------------------------------
#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
#define SMU7_SCALE_I 7
#define SMU7_SCALE_R 12
struct SMU7_PowerScoreboard
{
uint16_t MinVoltage;
uint16_t MaxVoltage;
uint32_t AvgGpuPower;
uint16_t VddcLeakagePower[SID_OPTION_COUNT];
uint16_t VddcSclkConstantPower[SID_OPTION_COUNT];
uint16_t VddcSclkDynamicPower[SID_OPTION_COUNT];
uint16_t VddcNonSclkDynamicPower[SID_OPTION_COUNT];
uint16_t VddcTotalPower[SID_OPTION_COUNT];
uint16_t VddcTotalCurrent[SID_OPTION_COUNT];
uint16_t VddcLoadVoltage[SID_OPTION_COUNT];
uint16_t VddcNoLoadVoltage[SID_OPTION_COUNT];
uint16_t DisplayPhyPower;
uint16_t PciePhyPower;
uint16_t VddciTotalPower;
uint16_t Vddr1TotalPower;
uint32_t RocPower;
uint32_t last_power;
uint32_t enableWinAvg;
uint32_t lkg_acc;
uint16_t VoltLkgeScaler;
uint16_t TempLkgeScaler;
uint32_t uvd_cac_dclk;
uint32_t uvd_cac_vclk;
uint32_t vce_cac_eclk;
uint32_t samu_cac_samclk;
uint32_t display_cac_dispclk;
uint32_t acp_cac_aclk;
uint32_t unb_cac;
uint32_t WinTime;
uint16_t GpuPwr_MAWt;
uint16_t FilteredVddcTotalPower;
uint8_t CalculationRepeats;
uint8_t WaterfallUp;
uint8_t WaterfallDown;
uint8_t WaterfallLimit;
};
typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
// --------------------------------------------------------------------------------------------------
struct SMU7_ThermalScoreboard
{
int16_t GpuLimit;
int16_t GpuHyst;
uint16_t CurrGnbTemp;
uint16_t FilteredGnbTemp;
uint8_t ControllerEnable;
uint8_t ControllerRunning;
uint8_t WaterfallUp;
uint8_t WaterfallDown;
uint8_t WaterfallLimit;
uint8_t padding[3];
};
typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard;
// For FeatureEnables:
#define SMU7_SCLK_DPM_CONFIG_MASK 0x01
#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02
#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04
#define SMU7_MCLK_DPM_CONFIG_MASK 0x08
#define SMU7_UVD_DPM_CONFIG_MASK 0x10
#define SMU7_VCE_DPM_CONFIG_MASK 0x20
#define SMU7_ACP_DPM_CONFIG_MASK 0x40
#define SMU7_SAMU_DPM_CONFIG_MASK 0x80
#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100
#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001
#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002
#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100
#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200
#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000
#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000
// All 'soft registers' should be uint32_t.
struct SMU71_SoftRegisters
{
uint32_t RefClockFrequency;
uint32_t PmTimerPeriod;
uint32_t FeatureEnables;
#if defined (SMU__DGPU_ONLY)
uint32_t PreVBlankGap;
uint32_t VBlankTimeout;
uint32_t TrainTimeGap;
uint32_t MvddSwitchTime;
uint32_t LongestAcpiTrainTime;
uint32_t AcpiDelay;
uint32_t G5TrainTime;
uint32_t DelayMpllPwron;
uint32_t VoltageChangeTimeout;
#endif
uint32_t HandshakeDisables;
uint8_t DisplayPhy1Config;
uint8_t DisplayPhy2Config;
uint8_t DisplayPhy3Config;
uint8_t DisplayPhy4Config;
uint8_t DisplayPhy5Config;
uint8_t DisplayPhy6Config;
uint8_t DisplayPhy7Config;
uint8_t DisplayPhy8Config;
uint32_t AverageGraphicsActivity;
uint32_t AverageMemoryActivity;
uint32_t AverageGioActivity;
uint8_t SClkDpmEnabledLevels;
uint8_t MClkDpmEnabledLevels;
uint8_t LClkDpmEnabledLevels;
uint8_t PCIeDpmEnabledLevels;
uint32_t DRAM_LOG_ADDR_H;
uint32_t DRAM_LOG_ADDR_L;
uint32_t DRAM_LOG_PHY_ADDR_H;
uint32_t DRAM_LOG_PHY_ADDR_L;
uint32_t DRAM_LOG_BUFF_SIZE;
uint32_t UlvEnterCount;
uint32_t UlvTime;
uint32_t UcodeLoadStatus;
uint8_t DPMFreezeAndForced;
uint8_t Activity_Weight;
uint8_t Reserved8[2];
uint32_t Reserved;
};
typedef struct SMU71_SoftRegisters SMU71_SoftRegisters;
struct SMU71_Firmware_Header
{
uint32_t Digest[5];
uint32_t Version;
uint32_t HeaderSize;
uint32_t Flags;
uint32_t EntryPoint;
uint32_t CodeSize;
uint32_t ImageSize;
uint32_t Rtos;
uint32_t SoftRegisters;
uint32_t DpmTable;
uint32_t FanTable;
uint32_t CacConfigTable;
uint32_t CacStatusTable;
uint32_t mcRegisterTable;
uint32_t mcArbDramTimingTable;
uint32_t PmFuseTable;
uint32_t Globals;
uint32_t UvdDpmTable;
uint32_t AcpDpmTable;
uint32_t VceDpmTable;
uint32_t SamuDpmTable;
uint32_t UlvSettings;
uint32_t Reserved[37];
uint32_t Signature;
};
typedef struct SMU71_Firmware_Header SMU71_Firmware_Header;
struct SMU7_HystController_Data
{
uint8_t waterfall_up;
uint8_t waterfall_down;
uint8_t pstate;
uint8_t clamp_mode;
};
typedef struct SMU7_HystController_Data SMU7_HystController_Data;
#define SMU71_FIRMWARE_HEADER_LOCATION 0x20000
enum DisplayConfig {
PowerDown = 1,
DP54x4,
DP54x2,
DP54x1,
DP27x4,
DP27x2,
DP27x1,
HDMI297,
HDMI162,
LVDS,
DP324x4,
DP324x2,
DP324x1
};
//#define SX_BLOCK_COUNT 8
//#define MC_BLOCK_COUNT 1
//#define CPL_BLOCK_COUNT 27
#if defined SMU__VARIANT__ICELAND
#define SX_BLOCK_COUNT 8
#define MC_BLOCK_COUNT 1
#define CPL_BLOCK_COUNT 29
#endif
struct SMU7_Local_Cac {
uint8_t BlockId;
uint8_t SignalId;
uint8_t Threshold;
uint8_t Padding;
};
typedef struct SMU7_Local_Cac SMU7_Local_Cac;
struct SMU7_Local_Cac_Table {
SMU7_Local_Cac SxLocalCac[SX_BLOCK_COUNT];
SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
};
typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
#if !defined(SMC_MICROCODE)
#pragma pack(pop)
#endif
#endif

631
drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h Normal file
View File

@ -0,0 +1,631 @@
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef SMU71_DISCRETE_H
#define SMU71_DISCRETE_H
#include "smu71.h"
#if !defined(SMC_MICROCODE)
#pragma pack(push, 1)
#endif
#define VDDC_ON_SVI2 0x1
#define VDDCI_ON_SVI2 0x2
#define MVDD_ON_SVI2 0x4
struct SMU71_Discrete_VoltageLevel
{
uint16_t Voltage;
uint16_t StdVoltageHiSidd;
uint16_t StdVoltageLoSidd;
uint8_t Smio;
uint8_t padding;
};
typedef struct SMU71_Discrete_VoltageLevel SMU71_Discrete_VoltageLevel;
struct SMU71_Discrete_GraphicsLevel
{
uint32_t MinVddc;
uint32_t MinVddcPhases;
uint32_t SclkFrequency;
uint8_t pcieDpmLevel;
uint8_t DeepSleepDivId;
uint16_t ActivityLevel;
uint32_t CgSpllFuncCntl3;
uint32_t CgSpllFuncCntl4;
uint32_t SpllSpreadSpectrum;
uint32_t SpllSpreadSpectrum2;
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
uint8_t SclkDid;
uint8_t DisplayWatermark;
uint8_t EnabledForActivity;
uint8_t EnabledForThrottle;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t PowerThrottle;
};
typedef struct SMU71_Discrete_GraphicsLevel SMU71_Discrete_GraphicsLevel;
struct SMU71_Discrete_ACPILevel
{
uint32_t Flags;
uint32_t MinVddc;
uint32_t MinVddcPhases;
uint32_t SclkFrequency;
uint8_t SclkDid;
uint8_t DisplayWatermark;
uint8_t DeepSleepDivId;
uint8_t padding;
uint32_t CgSpllFuncCntl;
uint32_t CgSpllFuncCntl2;
uint32_t CgSpllFuncCntl3;
uint32_t CgSpllFuncCntl4;
uint32_t SpllSpreadSpectrum;
uint32_t SpllSpreadSpectrum2;
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
};
typedef struct SMU71_Discrete_ACPILevel SMU71_Discrete_ACPILevel;
struct SMU71_Discrete_Ulv
{
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
uint16_t VddcOffset;
uint8_t VddcOffsetVid;
uint8_t VddcPhase;
uint32_t Reserved;
};
typedef struct SMU71_Discrete_Ulv SMU71_Discrete_Ulv;
struct SMU71_Discrete_MemoryLevel
{
uint32_t MinVddc;
uint32_t MinVddcPhases;
uint32_t MinVddci;
uint32_t MinMvdd;
uint32_t MclkFrequency;
uint8_t EdcReadEnable;
uint8_t EdcWriteEnable;
uint8_t RttEnable;
uint8_t StutterEnable;
uint8_t StrobeEnable;
uint8_t StrobeRatio;
uint8_t EnabledForThrottle;
uint8_t EnabledForActivity;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t padding;
uint16_t ActivityLevel;
uint8_t DisplayWatermark;
uint8_t padding1;
uint32_t MpllFuncCntl;
uint32_t MpllFuncCntl_1;
uint32_t MpllFuncCntl_2;
uint32_t MpllAdFuncCntl;
uint32_t MpllDqFuncCntl;
uint32_t MclkPwrmgtCntl;
uint32_t DllCntl;
uint32_t MpllSs1;
uint32_t MpllSs2;
};
typedef struct SMU71_Discrete_MemoryLevel SMU71_Discrete_MemoryLevel;
struct SMU71_Discrete_LinkLevel
{
uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3
uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
uint8_t EnabledForActivity;
uint8_t SPC;
uint32_t DownThreshold;
uint32_t UpThreshold;
uint32_t Reserved;
};
typedef struct SMU71_Discrete_LinkLevel SMU71_Discrete_LinkLevel;
#ifdef SMU__DYNAMIC_MCARB_SETTINGS
// MC ARB DRAM Timing registers.
struct SMU71_Discrete_MCArbDramTimingTableEntry
{
uint32_t McArbDramTiming;
uint32_t McArbDramTiming2;
uint8_t McArbBurstTime;
uint8_t padding[3];
};
typedef struct SMU71_Discrete_MCArbDramTimingTableEntry SMU71_Discrete_MCArbDramTimingTableEntry;
struct SMU71_Discrete_MCArbDramTimingTable
{
SMU71_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
};
typedef struct SMU71_Discrete_MCArbDramTimingTable SMU71_Discrete_MCArbDramTimingTable;
#endif
// UVD VCLK/DCLK state (level) definition.
struct SMU71_Discrete_UvdLevel
{
uint32_t VclkFrequency;
uint32_t DclkFrequency;
uint16_t MinVddc;
uint8_t MinVddcPhases;
uint8_t VclkDivider;
uint8_t DclkDivider;
uint8_t padding[3];
};
typedef struct SMU71_Discrete_UvdLevel SMU71_Discrete_UvdLevel;
// Clocks for other external blocks (VCE, ACP, SAMU).
struct SMU71_Discrete_ExtClkLevel
{
uint32_t Frequency;
uint16_t MinVoltage;
uint8_t MinPhases;
uint8_t Divider;
};
typedef struct SMU71_Discrete_ExtClkLevel SMU71_Discrete_ExtClkLevel;
// Everything that we need to keep track of about the current state.
// Use this instead of copies of the GraphicsLevel and MemoryLevel structures to keep track of state parameters
// that need to be checked later.
// We don't need to cache everything about a state, just a few parameters.
struct SMU71_Discrete_StateInfo
{
uint32_t SclkFrequency;
uint32_t MclkFrequency;
uint32_t VclkFrequency;
uint32_t DclkFrequency;
uint32_t SamclkFrequency;
uint32_t AclkFrequency;
uint32_t EclkFrequency;
uint16_t MvddVoltage;
uint16_t padding16;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint8_t McRegIndex;
uint8_t SeqIndex;
uint8_t SclkDid;
int8_t SclkIndex;
int8_t MclkIndex;
uint8_t PCIeGen;
};
typedef struct SMU71_Discrete_StateInfo SMU71_Discrete_StateInfo;
struct SMU71_Discrete_DpmTable
{
// Multi-DPM controller settings
SMU71_PIDController GraphicsPIDController;
SMU71_PIDController MemoryPIDController;
SMU71_PIDController LinkPIDController;
uint32_t SystemFlags;
// SMIO masks for voltage and phase controls
uint32_t SmioMaskVddcVid;
uint32_t SmioMaskVddcPhase;
uint32_t SmioMaskVddciVid;
uint32_t SmioMaskMvddVid;
uint32_t VddcLevelCount;
uint32_t VddciLevelCount;
uint32_t MvddLevelCount;
SMU71_Discrete_VoltageLevel VddcLevel [SMU71_MAX_LEVELS_VDDC];
SMU71_Discrete_VoltageLevel VddciLevel [SMU71_MAX_LEVELS_VDDCI];
SMU71_Discrete_VoltageLevel MvddLevel [SMU71_MAX_LEVELS_MVDD];
uint8_t GraphicsDpmLevelCount;
uint8_t MemoryDpmLevelCount;
uint8_t LinkLevelCount;
uint8_t MasterDeepSleepControl;
uint32_t Reserved[5];
// State table entries for each DPM state
SMU71_Discrete_GraphicsLevel GraphicsLevel [SMU71_MAX_LEVELS_GRAPHICS];
SMU71_Discrete_MemoryLevel MemoryACPILevel;
SMU71_Discrete_MemoryLevel MemoryLevel [SMU71_MAX_LEVELS_MEMORY];
SMU71_Discrete_LinkLevel LinkLevel [SMU71_MAX_LEVELS_LINK];
SMU71_Discrete_ACPILevel ACPILevel;
uint32_t SclkStepSize;
uint32_t Smio [SMU71_MAX_ENTRIES_SMIO];
uint8_t GraphicsBootLevel;
uint8_t GraphicsVoltageChangeEnable;
uint8_t GraphicsThermThrottleEnable;
uint8_t GraphicsInterval;
uint8_t VoltageInterval;
uint8_t ThermalInterval;
uint16_t TemperatureLimitHigh;
uint16_t TemperatureLimitLow;
uint8_t MemoryBootLevel;
uint8_t MemoryVoltageChangeEnable;
uint8_t MemoryInterval;
uint8_t MemoryThermThrottleEnable;
uint8_t MergedVddci;
uint8_t padding2;
uint16_t VoltageResponseTime;
uint16_t PhaseResponseTime;
uint8_t PCIeBootLinkLevel;
uint8_t PCIeGenInterval;
uint8_t DTEInterval;
uint8_t DTEMode;
uint8_t SVI2Enable;
uint8_t VRHotGpio;
uint8_t AcDcGpio;
uint8_t ThermGpio;
uint32_t DisplayCac;
uint16_t MaxPwr;
uint16_t NomPwr;
uint16_t FpsHighThreshold;
uint16_t FpsLowThreshold;
uint16_t BAPMTI_R [SMU71_DTE_ITERATIONS][SMU71_DTE_SOURCES][SMU71_DTE_SINKS];
uint16_t BAPMTI_RC [SMU71_DTE_ITERATIONS][SMU71_DTE_SOURCES][SMU71_DTE_SINKS];
uint8_t DTEAmbientTempBase;
uint8_t DTETjOffset;
uint8_t GpuTjMax;
uint8_t GpuTjHyst;
uint16_t BootVddc;
uint16_t BootVddci;
uint16_t BootMVdd;
uint16_t padding;
uint32_t BAPM_TEMP_GRADIENT;
uint32_t LowSclkInterruptThreshold;
uint32_t VddGfxReChkWait;
uint16_t PPM_PkgPwrLimit;
uint16_t PPM_TemperatureLimit;
uint16_t DefaultTdp;
uint16_t TargetTdp;
};
typedef struct SMU71_Discrete_DpmTable SMU71_Discrete_DpmTable;
// --------------------------------------------------- AC Timing Parameters ------------------------------------------------
#define SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
#define SMU71_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU71_MAX_LEVELS_MEMORY
struct SMU71_Discrete_MCRegisterAddress
{
uint16_t s0;
uint16_t s1;
};
typedef struct SMU71_Discrete_MCRegisterAddress SMU71_Discrete_MCRegisterAddress;
struct SMU71_Discrete_MCRegisterSet
{
uint32_t value[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
};
typedef struct SMU71_Discrete_MCRegisterSet SMU71_Discrete_MCRegisterSet;
struct SMU71_Discrete_MCRegisters
{
uint8_t last;
uint8_t reserved[3];
SMU71_Discrete_MCRegisterAddress address[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
SMU71_Discrete_MCRegisterSet data[SMU71_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
};
typedef struct SMU71_Discrete_MCRegisters SMU71_Discrete_MCRegisters;
// --------------------------------------------------- Fan Table -----------------------------------------------------------
struct SMU71_Discrete_FanTable
{
uint16_t FdoMode;
int16_t TempMin;
int16_t TempMed;
int16_t TempMax;
int16_t Slope1;
int16_t Slope2;
int16_t FdoMin;
int16_t HystUp;
int16_t HystDown;
int16_t HystSlope;
int16_t TempRespLim;
int16_t TempCurr;
int16_t SlopeCurr;
int16_t PwmCurr;
uint32_t RefreshPeriod;
int16_t FdoMax;
uint8_t TempSrc;
int8_t Padding;
};
typedef struct SMU71_Discrete_FanTable SMU71_Discrete_FanTable;
#define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
struct SMU71_MclkDpmScoreboard
{
uint32_t PercentageBusy;
int32_t PIDError;
int32_t PIDIntegral;
int32_t PIDOutput;
uint32_t SigmaDeltaAccum;
uint32_t SigmaDeltaOutput;
uint32_t SigmaDeltaLevel;
uint32_t UtilizationSetpoint;
uint8_t TdpClampMode;
uint8_t TdcClampMode;
uint8_t ThermClampMode;
uint8_t VoltageBusy;
int8_t CurrLevel;
int8_t TargLevel;
uint8_t LevelChangeInProgress;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint32_t MinimumPerfMclk;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t MclkSwitchInProgress;
uint8_t MclkSwitchCritical;
uint8_t TargetMclkIndex;
uint8_t TargetMvddIndex;
uint8_t MclkSwitchResult;
uint8_t EnabledLevelsChange;
uint16_t LevelResidencyCounters [SMU71_MAX_LEVELS_MEMORY];
uint16_t LevelSwitchCounters [SMU71_MAX_LEVELS_MEMORY];
void (*TargetStateCalculator)(uint8_t);
void (*SavedTargetStateCalculator)(uint8_t);
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint16_t MclkSwitchingTime;
uint8_t padding[2];
};
typedef struct SMU71_MclkDpmScoreboard SMU71_MclkDpmScoreboard;
struct SMU71_UlvScoreboard
{
uint8_t EnterUlv;
uint8_t ExitUlv;
uint8_t UlvActive;
uint8_t WaitingForUlv;
uint8_t UlvEnable;
uint8_t UlvRunning;
uint8_t UlvMasterEnable;
uint8_t padding;
uint32_t UlvAbortedCount;
uint32_t UlvTimeStamp;
};
typedef struct SMU71_UlvScoreboard SMU71_UlvScoreboard;
struct SMU71_VddGfxScoreboard
{
uint8_t VddGfxEnable;
uint8_t VddGfxActive;
uint8_t padding[2];
uint32_t VddGfxEnteredCount;
uint32_t VddGfxAbortedCount;
};
typedef struct SMU71_VddGfxScoreboard SMU71_VddGfxScoreboard;
struct SMU71_AcpiScoreboard {
uint32_t SavedInterruptMask[2];
uint8_t LastACPIRequest;
uint8_t CgBifResp;
uint8_t RequestType;
uint8_t Padding;
SMU71_Discrete_ACPILevel D0Level;
};
typedef struct SMU71_AcpiScoreboard SMU71_AcpiScoreboard;
struct SMU71_Discrete_PmFuses {
// dw0-dw1
uint8_t BapmVddCVidHiSidd[8];
// dw2-dw3
uint8_t BapmVddCVidLoSidd[8];
// dw4-dw5
uint8_t VddCVid[8];
// dw6
uint8_t SviLoadLineEn;
uint8_t SviLoadLineVddC;
uint8_t SviLoadLineTrimVddC;
uint8_t SviLoadLineOffsetVddC;
// dw7
uint16_t TDC_VDDC_PkgLimit;
uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
uint8_t TDC_MAWt;
// dw8
uint8_t TdcWaterfallCtl;
uint8_t LPMLTemperatureMin;
uint8_t LPMLTemperatureMax;
uint8_t Reserved;
// dw9-dw12
uint8_t LPMLTemperatureScaler[16];
// dw13-dw14
int16_t FuzzyFan_ErrorSetDelta;
int16_t FuzzyFan_ErrorRateSetDelta;
int16_t FuzzyFan_PwmSetDelta;
uint16_t Reserved6;
// dw15
uint8_t GnbLPML[16];
// dw15
uint8_t GnbLPMLMaxVid;
uint8_t GnbLPMLMinVid;
uint8_t Reserved1[2];
// dw16
uint16_t BapmVddCBaseLeakageHiSidd;
uint16_t BapmVddCBaseLeakageLoSidd;
};
typedef struct SMU71_Discrete_PmFuses SMU71_Discrete_PmFuses;
struct SMU71_Discrete_Log_Header_Table {
uint32_t version;
uint32_t asic_id;
uint16_t flags;
uint16_t entry_size;
uint32_t total_size;
uint32_t num_of_entries;
uint8_t type;
uint8_t mode;
uint8_t filler_0[2];
uint32_t filler_1[2];
};
typedef struct SMU71_Discrete_Log_Header_Table SMU71_Discrete_Log_Header_Table;
struct SMU71_Discrete_Log_Cntl {
uint8_t Enabled;
uint8_t Type;
uint8_t padding[2];
uint32_t BufferSize;
uint32_t SamplesLogged;
uint32_t SampleSize;
uint32_t AddrL;
uint32_t AddrH;
};
typedef struct SMU71_Discrete_Log_Cntl SMU71_Discrete_Log_Cntl;
#if defined SMU__DGPU_ONLY
#define CAC_ACC_NW_NUM_OF_SIGNALS 83
#endif
struct SMU71_Discrete_Cac_Collection_Table {
uint32_t temperature;
uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
uint32_t filler[4];
};
typedef struct SMU71_Discrete_Cac_Collection_Table SMU71_Discrete_Cac_Collection_Table;
struct SMU71_Discrete_Cac_Verification_Table {
uint32_t VddcTotalPower;
uint32_t VddcLeakagePower;
uint32_t VddcConstantPower;
uint32_t VddcGfxDynamicPower;
uint32_t VddcUvdDynamicPower;
uint32_t VddcVceDynamicPower;
uint32_t VddcAcpDynamicPower;
uint32_t VddcPcieDynamicPower;
uint32_t VddcDceDynamicPower;
uint32_t VddcCurrent;
uint32_t VddcVoltage;
uint32_t VddciTotalPower;
uint32_t VddciLeakagePower;
uint32_t VddciConstantPower;
uint32_t VddciDynamicPower;
uint32_t Vddr1TotalPower;
uint32_t Vddr1LeakagePower;
uint32_t Vddr1ConstantPower;
uint32_t Vddr1DynamicPower;
uint32_t spare[8];
uint32_t temperature;
};
typedef struct SMU71_Discrete_Cac_Verification_Table SMU71_Discrete_Cac_Verification_Table;
#if !defined(SMC_MICROCODE)
#pragma pack(pop)
#endif
#endif