powerpc/powernv: Move cpuidle related code from setup.c to new file
This is a cleanup patch; doesn't change any functionality. Moves all cpuidle related code from setup.c to a new file. Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com> Reviewed-by: Preeti U Murthy <preeti@linux.vnet.ibm.com> [mpe: Fix the SMP=n build by including asm/smp.h in idle.c] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Shreyas B. Prabhu
Michael Ellerman
parent
e602ffb2fa
commit
d405a98c70
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@ -1,4 +1,4 @@
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obj-y += setup.o opal-wrappers.o opal.o opal-async.o
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obj-y += setup.o opal-wrappers.o opal.o opal-async.o idle.o
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obj-y += opal-rtc.o opal-nvram.o opal-lpc.o opal-flash.o
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obj-y += rng.o opal-elog.o opal-dump.o opal-sysparam.o opal-sensor.o
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obj-y += opal-msglog.o opal-hmi.o opal-power.o
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@ -0,0 +1,192 @@
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/*
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* PowerNV cpuidle code
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*
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* Copyright 2015 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <asm/firmware.h>
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#include <asm/opal.h>
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#include <asm/cputhreads.h>
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#include <asm/cpuidle.h>
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#include <asm/code-patching.h>
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#include <asm/smp.h>
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#include "powernv.h"
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#include "subcore.h"
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static u32 supported_cpuidle_states;
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int pnv_save_sprs_for_winkle(void)
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{
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int cpu;
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int rc;
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/*
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* hid0, hid1, hid4, hid5, hmeer and lpcr values are symmetric accross
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* all cpus at boot. Get these reg values of current cpu and use the
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* same accross all cpus.
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*/
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uint64_t lpcr_val = mfspr(SPRN_LPCR) & ~(u64)LPCR_PECE1;
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uint64_t hid0_val = mfspr(SPRN_HID0);
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uint64_t hid1_val = mfspr(SPRN_HID1);
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uint64_t hid4_val = mfspr(SPRN_HID4);
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uint64_t hid5_val = mfspr(SPRN_HID5);
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uint64_t hmeer_val = mfspr(SPRN_HMEER);
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for_each_possible_cpu(cpu) {
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uint64_t pir = get_hard_smp_processor_id(cpu);
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uint64_t hsprg0_val = (uint64_t)&paca[cpu];
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/*
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* HSPRG0 is used to store the cpu's pointer to paca. Hence last
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* 3 bits are guaranteed to be 0. Program slw to restore HSPRG0
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* with 63rd bit set, so that when a thread wakes up at 0x100 we
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* can use this bit to distinguish between fastsleep and
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* deep winkle.
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*/
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hsprg0_val |= 1;
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rc = opal_slw_set_reg(pir, SPRN_HSPRG0, hsprg0_val);
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if (rc != 0)
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return rc;
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rc = opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val);
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if (rc != 0)
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return rc;
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/* HIDs are per core registers */
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if (cpu_thread_in_core(cpu) == 0) {
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rc = opal_slw_set_reg(pir, SPRN_HMEER, hmeer_val);
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if (rc != 0)
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return rc;
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rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val);
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if (rc != 0)
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return rc;
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rc = opal_slw_set_reg(pir, SPRN_HID1, hid1_val);
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if (rc != 0)
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return rc;
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rc = opal_slw_set_reg(pir, SPRN_HID4, hid4_val);
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if (rc != 0)
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return rc;
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rc = opal_slw_set_reg(pir, SPRN_HID5, hid5_val);
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if (rc != 0)
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return rc;
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}
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}
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return 0;
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}
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static void pnv_alloc_idle_core_states(void)
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{
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int i, j;
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int nr_cores = cpu_nr_cores();
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u32 *core_idle_state;
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/*
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* core_idle_state - First 8 bits track the idle state of each thread
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* of the core. The 8th bit is the lock bit. Initially all thread bits
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* are set. They are cleared when the thread enters deep idle state
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* like sleep and winkle. Initially the lock bit is cleared.
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* The lock bit has 2 purposes
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* a. While the first thread is restoring core state, it prevents
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* other threads in the core from switching to process context.
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* b. While the last thread in the core is saving the core state, it
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* prevents a different thread from waking up.
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*/
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for (i = 0; i < nr_cores; i++) {
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int first_cpu = i * threads_per_core;
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int node = cpu_to_node(first_cpu);
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core_idle_state = kmalloc_node(sizeof(u32), GFP_KERNEL, node);
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*core_idle_state = PNV_CORE_IDLE_THREAD_BITS;
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for (j = 0; j < threads_per_core; j++) {
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int cpu = first_cpu + j;
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paca[cpu].core_idle_state_ptr = core_idle_state;
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paca[cpu].thread_idle_state = PNV_THREAD_RUNNING;
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paca[cpu].thread_mask = 1 << j;
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}
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}
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update_subcore_sibling_mask();
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if (supported_cpuidle_states & OPAL_PM_WINKLE_ENABLED)
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pnv_save_sprs_for_winkle();
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}
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u32 pnv_get_supported_cpuidle_states(void)
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{
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return supported_cpuidle_states;
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}
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EXPORT_SYMBOL_GPL(pnv_get_supported_cpuidle_states);
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static int __init pnv_init_idle_states(void)
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{
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struct device_node *power_mgt;
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int dt_idle_states;
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u32 *flags;
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int i;
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supported_cpuidle_states = 0;
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if (cpuidle_disable != IDLE_NO_OVERRIDE)
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goto out;
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if (!firmware_has_feature(FW_FEATURE_OPALv3))
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goto out;
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power_mgt = of_find_node_by_path("/ibm,opal/power-mgt");
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if (!power_mgt) {
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pr_warn("opal: PowerMgmt Node not found\n");
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goto out;
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}
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dt_idle_states = of_property_count_u32_elems(power_mgt,
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"ibm,cpu-idle-state-flags");
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if (dt_idle_states < 0) {
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pr_warn("cpuidle-powernv: no idle states found in the DT\n");
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goto out;
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}
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flags = kzalloc(sizeof(*flags) * dt_idle_states, GFP_KERNEL);
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if (of_property_read_u32_array(power_mgt,
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"ibm,cpu-idle-state-flags", flags, dt_idle_states)) {
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pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-flags in DT\n");
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goto out_free;
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}
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for (i = 0; i < dt_idle_states; i++)
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supported_cpuidle_states |= flags[i];
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if (!(supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED_ER1)) {
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patch_instruction(
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(unsigned int *)pnv_fastsleep_workaround_at_entry,
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PPC_INST_NOP);
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patch_instruction(
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(unsigned int *)pnv_fastsleep_workaround_at_exit,
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PPC_INST_NOP);
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}
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pnv_alloc_idle_core_states();
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out_free:
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kfree(flags);
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out:
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return 0;
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}
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subsys_initcall(pnv_init_idle_states);
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@ -35,12 +35,8 @@
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#include <asm/opal.h>
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#include <asm/kexec.h>
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#include <asm/smp.h>
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#include <asm/cputhreads.h>
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#include <asm/cpuidle.h>
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#include <asm/code-patching.h>
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#include "powernv.h"
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#include "subcore.h"
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static void __init pnv_setup_arch(void)
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{
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@ -277,173 +273,6 @@ static void __init pnv_setup_machdep_opal(void)
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ppc_md.handle_hmi_exception = opal_handle_hmi_exception;
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}
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static u32 supported_cpuidle_states;
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int pnv_save_sprs_for_winkle(void)
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{
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int cpu;
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int rc;
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/*
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* hid0, hid1, hid4, hid5, hmeer and lpcr values are symmetric accross
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* all cpus at boot. Get these reg values of current cpu and use the
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* same accross all cpus.
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*/
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uint64_t lpcr_val = mfspr(SPRN_LPCR) & ~(u64)LPCR_PECE1;
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uint64_t hid0_val = mfspr(SPRN_HID0);
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uint64_t hid1_val = mfspr(SPRN_HID1);
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uint64_t hid4_val = mfspr(SPRN_HID4);
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uint64_t hid5_val = mfspr(SPRN_HID5);
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uint64_t hmeer_val = mfspr(SPRN_HMEER);
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for_each_possible_cpu(cpu) {
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uint64_t pir = get_hard_smp_processor_id(cpu);
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uint64_t hsprg0_val = (uint64_t)&paca[cpu];
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/*
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* HSPRG0 is used to store the cpu's pointer to paca. Hence last
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* 3 bits are guaranteed to be 0. Program slw to restore HSPRG0
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* with 63rd bit set, so that when a thread wakes up at 0x100 we
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* can use this bit to distinguish between fastsleep and
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* deep winkle.
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*/
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hsprg0_val |= 1;
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rc = opal_slw_set_reg(pir, SPRN_HSPRG0, hsprg0_val);
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if (rc != 0)
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return rc;
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rc = opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val);
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if (rc != 0)
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return rc;
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/* HIDs are per core registers */
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if (cpu_thread_in_core(cpu) == 0) {
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rc = opal_slw_set_reg(pir, SPRN_HMEER, hmeer_val);
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if (rc != 0)
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return rc;
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rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val);
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if (rc != 0)
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return rc;
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rc = opal_slw_set_reg(pir, SPRN_HID1, hid1_val);
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if (rc != 0)
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return rc;
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rc = opal_slw_set_reg(pir, SPRN_HID4, hid4_val);
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if (rc != 0)
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return rc;
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rc = opal_slw_set_reg(pir, SPRN_HID5, hid5_val);
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if (rc != 0)
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return rc;
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}
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}
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return 0;
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}
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static void pnv_alloc_idle_core_states(void)
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{
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int i, j;
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int nr_cores = cpu_nr_cores();
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u32 *core_idle_state;
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/*
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* core_idle_state - First 8 bits track the idle state of each thread
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* of the core. The 8th bit is the lock bit. Initially all thread bits
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* are set. They are cleared when the thread enters deep idle state
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* like sleep and winkle. Initially the lock bit is cleared.
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* The lock bit has 2 purposes
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* a. While the first thread is restoring core state, it prevents
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* other threads in the core from switching to process context.
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* b. While the last thread in the core is saving the core state, it
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* prevents a different thread from waking up.
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*/
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for (i = 0; i < nr_cores; i++) {
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int first_cpu = i * threads_per_core;
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int node = cpu_to_node(first_cpu);
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core_idle_state = kmalloc_node(sizeof(u32), GFP_KERNEL, node);
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*core_idle_state = PNV_CORE_IDLE_THREAD_BITS;
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for (j = 0; j < threads_per_core; j++) {
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int cpu = first_cpu + j;
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paca[cpu].core_idle_state_ptr = core_idle_state;
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paca[cpu].thread_idle_state = PNV_THREAD_RUNNING;
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paca[cpu].thread_mask = 1 << j;
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}
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}
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update_subcore_sibling_mask();
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if (supported_cpuidle_states & OPAL_PM_WINKLE_ENABLED)
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pnv_save_sprs_for_winkle();
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}
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u32 pnv_get_supported_cpuidle_states(void)
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{
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return supported_cpuidle_states;
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}
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EXPORT_SYMBOL_GPL(pnv_get_supported_cpuidle_states);
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static int __init pnv_init_idle_states(void)
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{
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struct device_node *power_mgt;
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int dt_idle_states;
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u32 *flags;
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int i;
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supported_cpuidle_states = 0;
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if (cpuidle_disable != IDLE_NO_OVERRIDE)
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goto out;
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if (!firmware_has_feature(FW_FEATURE_OPALv3))
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goto out;
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power_mgt = of_find_node_by_path("/ibm,opal/power-mgt");
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if (!power_mgt) {
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pr_warn("opal: PowerMgmt Node not found\n");
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goto out;
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}
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dt_idle_states = of_property_count_u32_elems(power_mgt,
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"ibm,cpu-idle-state-flags");
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if (dt_idle_states < 0) {
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pr_warn("cpuidle-powernv: no idle states found in the DT\n");
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goto out;
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}
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flags = kzalloc(sizeof(*flags) * dt_idle_states, GFP_KERNEL);
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if (of_property_read_u32_array(power_mgt,
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"ibm,cpu-idle-state-flags", flags, dt_idle_states)) {
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pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-flags in DT\n");
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goto out_free;
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}
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for (i = 0; i < dt_idle_states; i++)
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supported_cpuidle_states |= flags[i];
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if (!(supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED_ER1)) {
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patch_instruction(
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(unsigned int *)pnv_fastsleep_workaround_at_entry,
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PPC_INST_NOP);
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patch_instruction(
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(unsigned int *)pnv_fastsleep_workaround_at_exit,
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PPC_INST_NOP);
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}
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pnv_alloc_idle_core_states();
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out_free:
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kfree(flags);
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out:
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return 0;
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}
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subsys_initcall(pnv_init_idle_states);
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static int __init pnv_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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