Qualcomm ARM Based Driver Updates for v5.5
* Add Bjorn as QCOM co-maintainer * Add LLLC yaml bindings and SC7180 support * Fixups/Cleanup for LLLC * Add SMD-RPM MSM8976 compatible and interconnect device * Add missing RPMD SMD perf level -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJdwP5rAAoJEFKiBbHx2RXVpigQALkNC+SntAom44+EtGe8fZEm Zdd4piMEi2Yr1m07wfSDG0GvOi0W0JP1xJ84BpzNBqqe/oJpmWJlpqfMf9W3ZgM1 /e3QPa5/TvjNznwxUVTIwo4VPMy31pk9ZsRep6vXkGL1zU+vGcXs8/IzaRKHMx/A eE1I1O6dxXQFia0fwSioQpsD6MvhAp447Z2CUQu6JMrEHRIiI+AJ9LgRWynYekv2 elmYvuFKJT+6BWB52hG+ck8Q6efvyhFJTB+Af4emjNmFIRaI26ZvTEDp6XXlb+Pq 0btTKLeEPxveVK8PxPmdNhPHjXvh7582piKXz3LyelPu50LIsElRZv45ACgRgsIF iGawfjgY/eoWqT45dibg2N4Aq2q2p/4JxVZGPOs1inxPOeBfKeOEc1xieHtijMdP BJjzzqj+keDOklfSeKNbFpfIYlZn7QVYCp+3w+mwOYiCf+2qI9Vx1cNaWqL5dzAL t4X0axfjpKTkacL9HgVOibGVLpdaISEqUdtG3UoxhrVOHom01waKRlMQHoEZMICT wG3fipAu8mv/RGz645Lj49FqK4+7DNbS+M3anyfRNypThyt/CI7FnbR6GGLh7jcr jRdt2XO72xNJWV5lZu0Jll0PhstykeLoqPiEB/HlvH6Gl9HF6x5tdMt0ZKwTw2i7 20q3xSE4GCYWVUb51CTk =K+qQ -----END PGP SIGNATURE----- Merge tag 'qcom-drivers-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers Qualcomm ARM Based Driver Updates for v5.5 * Add Bjorn as QCOM co-maintainer * Add LLLC yaml bindings and SC7180 support * Fixups/Cleanup for LLLC * Add SMD-RPM MSM8976 compatible and interconnect device * Add missing RPMD SMD perf level * tag 'qcom-drivers-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: MAINTAINERS: Add myself as co-maintainer for QCOM dt-bindings: msm: Add LLCC for SC7180 dt-bindings: msm: Convert LLCC bindings to YAML soc: qcom: llcc: Add configuration data for SC7180 soc: qcom: llcc: Move regmap config to local variable soc: qcom: llcc: Name regmaps to avoid collisions soc: qcom: Fix llcc-qcom definitions to include soc: qcom: rpmpd: Add rpm power domains for msm8976 dt-bindings: power: Add missing rpmpd smd performance level soc: qcom: smd-rpm: Add MSM8976 compatible soc: qcom: socinfo: add sdm845 and sda845 soc ids soc: qcom: smd-rpm: Create RPM interconnect proxy child device soc: qcom: Make llcc-qcom a generic driver soc: qcom: Rename llcc-slice to llcc-qcom soc: qcom: llcc cleanup to get rid of sdm845 specific driver file Link: https://lore.kernel.org/r/1573068840-13098-4-git-send-email-agross@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
d4b0c97a80
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@ -1,41 +0,0 @@
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== Introduction==
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LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,
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that can be shared by multiple clients. Clients here are different cores in the
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SOC, the idea is to minimize the local caches at the clients and migrate to
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common pool of memory. Cache memory is divided into partitions called slices
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which are assigned to clients. Clients can query the slice details, activate
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and deactivate them.
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Properties:
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- compatible:
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Usage: required
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Value type: <string>
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Definition: must be "qcom,sdm845-llcc"
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- reg:
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Usage: required
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Value Type: <prop-encoded-array>
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Definition: The first element specifies the llcc base start address and
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the size of the register region. The second element specifies
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the llcc broadcast base address and size of the register region.
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- reg-names:
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Usage: required
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Value Type: <stringlist>
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Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base".
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- interrupts:
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Usage: required
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Definition: The interrupt is associated with the llcc edac device.
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It's used for llcc cache single and double bit error detection
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and reporting.
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Example:
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cache-controller@1100000 {
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compatible = "qcom,sdm845-llcc";
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reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
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reg-names = "llcc_base", "llcc_broadcast_base";
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interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
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};
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@ -0,0 +1,55 @@
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# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Last Level Cache Controller
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maintainers:
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- Rishabh Bhatnagar <rishabhb@codeaurora.org>
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- Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
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description: |
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LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
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that can be shared by multiple clients. Clients here are different cores in the
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SoC, the idea is to minimize the local caches at the clients and migrate to
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common pool of memory. Cache memory is divided into partitions called slices
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which are assigned to clients. Clients can query the slice details, activate
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and deactivate them.
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properties:
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compatible:
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enum:
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- qcom,sc7180-llcc
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- qcom,sdm845-llcc
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reg:
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items:
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- description: LLCC base register region
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- description: LLCC broadcast base register region
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reg-names:
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items:
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- const: llcc_base
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- const: llcc_broadcast_base
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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cache-controller@1100000 {
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compatible = "qcom,sdm845-llcc";
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reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
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reg-names = "llcc_base", "llcc_broadcast_base";
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interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
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};
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@ -5,6 +5,7 @@ which then translates it into a corresponding voltage on a rail
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Required Properties:
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- compatible: Should be one of the following
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* qcom,msm8976-rpmpd: RPM Power domain for the msm8976 family of SoC
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* qcom,msm8996-rpmpd: RPM Power domain for the msm8996 family of SoC
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* qcom,msm8998-rpmpd: RPM Power domain for the msm8998 family of SoC
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* qcom,qcs404-rpmpd: RPM Power domain for the qcs404 family of SoC
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|
|
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@ -22,6 +22,7 @@ resources.
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"qcom,rpm-apq8084"
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"qcom,rpm-msm8916"
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"qcom,rpm-msm8974"
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"qcom,rpm-msm8976"
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"qcom,rpm-msm8998"
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"qcom,rpm-sdm660"
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"qcom,rpm-qcs404"
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|
|
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@ -2102,6 +2102,7 @@ S: Maintained
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ARM/QUALCOMM SUPPORT
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M: Andy Gross <agross@kernel.org>
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M: Bjorn Andersson <bjorn.andersson@linaro.org>
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L: linux-arm-msm@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/soc/qcom/
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|
|
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@ -58,17 +58,9 @@ config QCOM_LLCC
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depends on ARCH_QCOM || COMPILE_TEST
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help
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Qualcomm Technologies, Inc. platform specific
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Last Level Cache Controller(LLCC) driver. This provides interfaces
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to clients that use the LLCC. Say yes here to enable LLCC slice
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driver.
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config QCOM_SDM845_LLCC
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tristate "Qualcomm Technologies, Inc. SDM845 LLCC driver"
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depends on QCOM_LLCC
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help
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Say yes here to enable the LLCC driver for SDM845. This provides
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data required to configure LLCC so that clients can start using the
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LLCC slices.
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Last Level Cache Controller(LLCC) driver for platforms such as,
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SDM845. This provides interfaces to clients that use the LLCC.
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Say yes here to enable LLCC slice driver.
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config QCOM_MDT_LOADER
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tristate
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|
|
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@ -21,7 +21,6 @@ obj-$(CONFIG_QCOM_SMSM) += smsm.o
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obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o
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obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
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obj-$(CONFIG_QCOM_APR) += apr.o
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obj-$(CONFIG_QCOM_LLCC) += llcc-slice.o
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obj-$(CONFIG_QCOM_SDM845_LLCC) += llcc-sdm845.o
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obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
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obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
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obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
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|
|
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|
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
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* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
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*
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*/
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@ -11,6 +11,7 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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#include <linux/sizes.h>
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@ -46,15 +47,90 @@
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#define BANK_OFFSET_STRIDE 0x80000
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static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
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static const struct regmap_config llcc_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.fast_io = true,
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/**
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* llcc_slice_config - Data associated with the llcc slice
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* @usecase_id: Unique id for the client's use case
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* @slice_id: llcc slice id for each client
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* @max_cap: The maximum capacity of the cache slice provided in KB
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* @priority: Priority of the client used to select victim line for replacement
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* @fixed_size: Boolean indicating if the slice has a fixed capacity
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* @bonus_ways: Bonus ways are additional ways to be used for any slice,
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* if client ends up using more than reserved cache ways. Bonus
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* ways are allocated only if they are not reserved for some
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* other client.
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* @res_ways: Reserved ways for the cache slice, the reserved ways cannot
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* be used by any other client than the one its assigned to.
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* @cache_mode: Each slice operates as a cache, this controls the mode of the
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* slice: normal or TCM(Tightly Coupled Memory)
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* @probe_target_ways: Determines what ways to probe for access hit. When
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* configured to 1 only bonus and reserved ways are probed.
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* When configured to 0 all ways in llcc are probed.
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* @dis_cap_alloc: Disable capacity based allocation for a client
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* @retain_on_pc: If this bit is set and client has maintained active vote
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* then the ways assigned to this client are not flushed on power
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* collapse.
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* @activate_on_init: Activate the slice immediately after it is programmed
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*/
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struct llcc_slice_config {
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u32 usecase_id;
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u32 slice_id;
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u32 max_cap;
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u32 priority;
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bool fixed_size;
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u32 bonus_ways;
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u32 res_ways;
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u32 cache_mode;
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u32 probe_target_ways;
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bool dis_cap_alloc;
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bool retain_on_pc;
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bool activate_on_init;
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};
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struct qcom_llcc_config {
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const struct llcc_slice_config *sct_data;
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int size;
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};
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static const struct llcc_slice_config sc7180_data[] = {
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{ LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 },
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{ LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
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{ LLCC_GPUHTW, 11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
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{ LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
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};
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static const struct llcc_slice_config sdm845_data[] = {
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{ LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 },
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{ LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
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{ LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
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{ LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0 },
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{ LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
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{ LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
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{ LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0 },
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{ LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
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{ LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
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{ LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0 },
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{ LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0 },
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{ LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1 },
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{ LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
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{ LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
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{ LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
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{ LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0 },
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{ LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0 },
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{ LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 },
|
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};
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|
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static const struct qcom_llcc_config sc7180_cfg = {
|
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.sct_data = sc7180_data,
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.size = ARRAY_SIZE(sc7180_data),
|
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};
|
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|
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static const struct qcom_llcc_config sdm845_cfg = {
|
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.sct_data = sdm845_data,
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.size = ARRAY_SIZE(sdm845_data),
|
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};
|
||||
|
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static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
|
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|
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/**
|
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* llcc_slice_getd - get llcc slice descriptor
|
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* @uid: usecase_id for the client
|
||||
|
|
@ -301,19 +377,24 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
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return ret;
|
||||
}
|
||||
|
||||
int qcom_llcc_remove(struct platform_device *pdev)
|
||||
static int qcom_llcc_remove(struct platform_device *pdev)
|
||||
{
|
||||
/* Set the global pointer to a error code to avoid referencing it */
|
||||
drv_data = ERR_PTR(-ENODEV);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_llcc_remove);
|
||||
|
||||
static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev,
|
||||
const char *name)
|
||||
{
|
||||
struct resource *res;
|
||||
void __iomem *base;
|
||||
struct regmap_config llcc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
|
||||
if (!res)
|
||||
|
|
@ -323,16 +404,19 @@ static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev,
|
|||
if (IS_ERR(base))
|
||||
return ERR_CAST(base);
|
||||
|
||||
llcc_regmap_config.name = name;
|
||||
return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config);
|
||||
}
|
||||
|
||||
int qcom_llcc_probe(struct platform_device *pdev,
|
||||
const struct llcc_slice_config *llcc_cfg, u32 sz)
|
||||
static int qcom_llcc_probe(struct platform_device *pdev)
|
||||
{
|
||||
u32 num_banks;
|
||||
struct device *dev = &pdev->dev;
|
||||
int ret, i;
|
||||
struct platform_device *llcc_edac;
|
||||
const struct qcom_llcc_config *cfg;
|
||||
const struct llcc_slice_config *llcc_cfg;
|
||||
u32 sz;
|
||||
|
||||
drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
|
||||
if (!drv_data) {
|
||||
|
|
@ -362,6 +446,10 @@ int qcom_llcc_probe(struct platform_device *pdev,
|
|||
num_banks >>= LLCC_LB_CNT_SHIFT;
|
||||
drv_data->num_banks = num_banks;
|
||||
|
||||
cfg = of_device_get_match_data(&pdev->dev);
|
||||
llcc_cfg = cfg->sct_data;
|
||||
sz = cfg->size;
|
||||
|
||||
for (i = 0; i < sz; i++)
|
||||
if (llcc_cfg[i].slice_id > drv_data->max_slices)
|
||||
drv_data->max_slices = llcc_cfg[i].slice_id;
|
||||
|
|
@ -407,6 +495,22 @@ int qcom_llcc_probe(struct platform_device *pdev,
|
|||
drv_data = ERR_PTR(-ENODEV);
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_llcc_probe);
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
||||
static const struct of_device_id qcom_llcc_of_match[] = {
|
||||
{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
|
||||
{ .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver qcom_llcc_driver = {
|
||||
.driver = {
|
||||
.name = "qcom-llcc",
|
||||
.of_match_table = qcom_llcc_of_match,
|
||||
},
|
||||
.probe = qcom_llcc_probe,
|
||||
.remove = qcom_llcc_remove,
|
||||
};
|
||||
module_platform_driver(qcom_llcc_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -1,100 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/soc/qcom/llcc-qcom.h>
|
||||
|
||||
/*
|
||||
* SCT(System Cache Table) entry contains of the following members:
|
||||
* usecase_id: Unique id for the client's use case
|
||||
* slice_id: llcc slice id for each client
|
||||
* max_cap: The maximum capacity of the cache slice provided in KB
|
||||
* priority: Priority of the client used to select victim line for replacement
|
||||
* fixed_size: Boolean indicating if the slice has a fixed capacity
|
||||
* bonus_ways: Bonus ways are additional ways to be used for any slice,
|
||||
* if client ends up using more than reserved cache ways. Bonus
|
||||
* ways are allocated only if they are not reserved for some
|
||||
* other client.
|
||||
* res_ways: Reserved ways for the cache slice, the reserved ways cannot
|
||||
* be used by any other client than the one its assigned to.
|
||||
* cache_mode: Each slice operates as a cache, this controls the mode of the
|
||||
* slice: normal or TCM(Tightly Coupled Memory)
|
||||
* probe_target_ways: Determines what ways to probe for access hit. When
|
||||
* configured to 1 only bonus and reserved ways are probed.
|
||||
* When configured to 0 all ways in llcc are probed.
|
||||
* dis_cap_alloc: Disable capacity based allocation for a client
|
||||
* retain_on_pc: If this bit is set and client has maintained active vote
|
||||
* then the ways assigned to this client are not flushed on power
|
||||
* collapse.
|
||||
* activate_on_init: Activate the slice immediately after the SCT is programmed
|
||||
*/
|
||||
#define SCT_ENTRY(uid, sid, mc, p, fs, bway, rway, cmod, ptw, dca, rp, a) \
|
||||
{ \
|
||||
.usecase_id = uid, \
|
||||
.slice_id = sid, \
|
||||
.max_cap = mc, \
|
||||
.priority = p, \
|
||||
.fixed_size = fs, \
|
||||
.bonus_ways = bway, \
|
||||
.res_ways = rway, \
|
||||
.cache_mode = cmod, \
|
||||
.probe_target_ways = ptw, \
|
||||
.dis_cap_alloc = dca, \
|
||||
.retain_on_pc = rp, \
|
||||
.activate_on_init = a, \
|
||||
}
|
||||
|
||||
static struct llcc_slice_config sdm845_data[] = {
|
||||
SCT_ENTRY(LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1),
|
||||
SCT_ENTRY(LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0),
|
||||
SCT_ENTRY(LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0),
|
||||
SCT_ENTRY(LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0),
|
||||
SCT_ENTRY(LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
|
||||
SCT_ENTRY(LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
|
||||
SCT_ENTRY(LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0),
|
||||
SCT_ENTRY(LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
|
||||
SCT_ENTRY(LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
|
||||
SCT_ENTRY(LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0),
|
||||
SCT_ENTRY(LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0),
|
||||
SCT_ENTRY(LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1),
|
||||
SCT_ENTRY(LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
|
||||
SCT_ENTRY(LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
|
||||
SCT_ENTRY(LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
|
||||
SCT_ENTRY(LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0),
|
||||
SCT_ENTRY(LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0),
|
||||
SCT_ENTRY(LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0),
|
||||
};
|
||||
|
||||
static int sdm845_qcom_llcc_remove(struct platform_device *pdev)
|
||||
{
|
||||
return qcom_llcc_remove(pdev);
|
||||
}
|
||||
|
||||
static int sdm845_qcom_llcc_probe(struct platform_device *pdev)
|
||||
{
|
||||
return qcom_llcc_probe(pdev, sdm845_data, ARRAY_SIZE(sdm845_data));
|
||||
}
|
||||
|
||||
static const struct of_device_id sdm845_qcom_llcc_of_match[] = {
|
||||
{ .compatible = "qcom,sdm845-llcc", },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver sdm845_qcom_llcc_driver = {
|
||||
.driver = {
|
||||
.name = "sdm845-llcc",
|
||||
.of_match_table = sdm845_qcom_llcc_of_match,
|
||||
},
|
||||
.probe = sdm845_qcom_llcc_probe,
|
||||
.remove = sdm845_qcom_llcc_remove,
|
||||
};
|
||||
module_platform_driver(sdm845_qcom_llcc_driver);
|
||||
|
||||
MODULE_DESCRIPTION("QCOM sdm845 LLCC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -115,6 +115,28 @@ struct rpmpd_desc {
|
|||
|
||||
static DEFINE_MUTEX(rpmpd_lock);
|
||||
|
||||
/* msm8976 RPM Power Domains */
|
||||
DEFINE_RPMPD_PAIR(msm8976, vddcx, vddcx_ao, SMPA, LEVEL, 2);
|
||||
DEFINE_RPMPD_PAIR(msm8976, vddmx, vddmx_ao, SMPA, LEVEL, 6);
|
||||
|
||||
DEFINE_RPMPD_VFL(msm8976, vddcx_vfl, RWSC, 2);
|
||||
DEFINE_RPMPD_VFL(msm8976, vddmx_vfl, RWSM, 6);
|
||||
|
||||
static struct rpmpd *msm8976_rpmpds[] = {
|
||||
[MSM8976_VDDCX] = &msm8976_vddcx,
|
||||
[MSM8976_VDDCX_AO] = &msm8976_vddcx_ao,
|
||||
[MSM8976_VDDCX_VFL] = &msm8976_vddcx_vfl,
|
||||
[MSM8976_VDDMX] = &msm8976_vddmx,
|
||||
[MSM8976_VDDMX_AO] = &msm8976_vddmx_ao,
|
||||
[MSM8976_VDDMX_VFL] = &msm8976_vddmx_vfl,
|
||||
};
|
||||
|
||||
static const struct rpmpd_desc msm8976_desc = {
|
||||
.rpmpds = msm8976_rpmpds,
|
||||
.num_pds = ARRAY_SIZE(msm8976_rpmpds),
|
||||
.max_state = RPM_SMD_LEVEL_TURBO_HIGH,
|
||||
};
|
||||
|
||||
/* msm8996 RPM Power domains */
|
||||
DEFINE_RPMPD_PAIR(msm8996, vddcx, vddcx_ao, SMPA, CORNER, 1);
|
||||
DEFINE_RPMPD_PAIR(msm8996, vddmx, vddmx_ao, SMPA, CORNER, 2);
|
||||
|
|
@ -198,6 +220,7 @@ static const struct rpmpd_desc qcs404_desc = {
|
|||
};
|
||||
|
||||
static const struct of_device_id rpmpd_match_table[] = {
|
||||
{ .compatible = "qcom,msm8976-rpmpd", .data = &msm8976_desc },
|
||||
{ .compatible = "qcom,msm8996-rpmpd", .data = &msm8996_desc },
|
||||
{ .compatible = "qcom,msm8998-rpmpd", .data = &msm8998_desc },
|
||||
{ .compatible = "qcom,qcs404-rpmpd", .data = &qcs404_desc },
|
||||
|
|
|
|||
|
|
@ -19,12 +19,14 @@
|
|||
/**
|
||||
* struct qcom_smd_rpm - state of the rpm device driver
|
||||
* @rpm_channel: reference to the smd channel
|
||||
* @icc: interconnect proxy device
|
||||
* @ack: completion for acks
|
||||
* @lock: mutual exclusion around the send/complete pair
|
||||
* @ack_status: result of the rpm request
|
||||
*/
|
||||
struct qcom_smd_rpm {
|
||||
struct rpmsg_endpoint *rpm_channel;
|
||||
struct platform_device *icc;
|
||||
struct device *dev;
|
||||
|
||||
struct completion ack;
|
||||
|
|
@ -193,6 +195,7 @@ static int qcom_smd_rpm_callback(struct rpmsg_device *rpdev,
|
|||
static int qcom_smd_rpm_probe(struct rpmsg_device *rpdev)
|
||||
{
|
||||
struct qcom_smd_rpm *rpm;
|
||||
int ret;
|
||||
|
||||
rpm = devm_kzalloc(&rpdev->dev, sizeof(*rpm), GFP_KERNEL);
|
||||
if (!rpm)
|
||||
|
|
@ -205,11 +208,23 @@ static int qcom_smd_rpm_probe(struct rpmsg_device *rpdev)
|
|||
rpm->rpm_channel = rpdev->ept;
|
||||
dev_set_drvdata(&rpdev->dev, rpm);
|
||||
|
||||
return of_platform_populate(rpdev->dev.of_node, NULL, NULL, &rpdev->dev);
|
||||
rpm->icc = platform_device_register_data(&rpdev->dev, "icc_smd_rpm", -1,
|
||||
NULL, 0);
|
||||
if (IS_ERR(rpm->icc))
|
||||
return PTR_ERR(rpm->icc);
|
||||
|
||||
ret = of_platform_populate(rpdev->dev.of_node, NULL, NULL, &rpdev->dev);
|
||||
if (ret)
|
||||
platform_device_unregister(rpm->icc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void qcom_smd_rpm_remove(struct rpmsg_device *rpdev)
|
||||
{
|
||||
struct qcom_smd_rpm *rpm = dev_get_drvdata(&rpdev->dev);
|
||||
|
||||
platform_device_unregister(rpm->icc);
|
||||
of_platform_depopulate(&rpdev->dev);
|
||||
}
|
||||
|
||||
|
|
@ -217,6 +232,7 @@ static const struct of_device_id qcom_smd_rpm_of_match[] = {
|
|||
{ .compatible = "qcom,rpm-apq8084" },
|
||||
{ .compatible = "qcom,rpm-msm8916" },
|
||||
{ .compatible = "qcom,rpm-msm8974" },
|
||||
{ .compatible = "qcom,rpm-msm8976" },
|
||||
{ .compatible = "qcom,rpm-msm8996" },
|
||||
{ .compatible = "qcom,rpm-msm8998" },
|
||||
{ .compatible = "qcom,rpm-sdm660" },
|
||||
|
|
|
|||
|
|
@ -198,6 +198,8 @@ static const struct soc_id soc_id[] = {
|
|||
{ 310, "MSM8996AU" },
|
||||
{ 311, "APQ8096AU" },
|
||||
{ 312, "APQ8096SG" },
|
||||
{ 321, "SDM845" },
|
||||
{ 341, "SDA845" },
|
||||
};
|
||||
|
||||
static const char *socinfo_machine(struct device *dev, unsigned int id)
|
||||
|
|
|
|||
|
|
@ -27,6 +27,14 @@
|
|||
#define RPMH_REGULATOR_LEVEL_TURBO 384
|
||||
#define RPMH_REGULATOR_LEVEL_TURBO_L1 416
|
||||
|
||||
/* MSM8976 Power Domain Indexes */
|
||||
#define MSM8976_VDDCX 0
|
||||
#define MSM8976_VDDCX_AO 1
|
||||
#define MSM8976_VDDCX_VFL 2
|
||||
#define MSM8976_VDDMX 3
|
||||
#define MSM8976_VDDMX_AO 4
|
||||
#define MSM8976_VDDMX_VFL 5
|
||||
|
||||
/* MSM8996 Power Domain Indexes */
|
||||
#define MSM8996_VDDCX 0
|
||||
#define MSM8996_VDDCX_AO 1
|
||||
|
|
@ -68,6 +76,7 @@
|
|||
#define RPM_SMD_LEVEL_NOM_PLUS 320
|
||||
#define RPM_SMD_LEVEL_TURBO 384
|
||||
#define RPM_SMD_LEVEL_TURBO_NO_CPR 416
|
||||
#define RPM_SMD_LEVEL_TURBO_HIGH 448
|
||||
#define RPM_SMD_LEVEL_BINNING 512
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -38,33 +38,27 @@ struct llcc_slice_desc {
|
|||
};
|
||||
|
||||
/**
|
||||
* llcc_slice_config - Data associated with the llcc slice
|
||||
* @usecase_id: usecase id for which the llcc slice is used
|
||||
* @slice_id: llcc slice id assigned to each slice
|
||||
* @max_cap: maximum capacity of the llcc slice
|
||||
* @priority: priority of the llcc slice
|
||||
* @fixed_size: whether the llcc slice can grow beyond its size
|
||||
* @bonus_ways: bonus ways associated with llcc slice
|
||||
* @res_ways: reserved ways associated with llcc slice
|
||||
* @cache_mode: mode of the llcc slice
|
||||
* @probe_target_ways: Probe only reserved and bonus ways on a cache miss
|
||||
* @dis_cap_alloc: Disable capacity based allocation
|
||||
* @retain_on_pc: Retain through power collapse
|
||||
* @activate_on_init: activate the slice on init
|
||||
* llcc_edac_reg_data - llcc edac registers data for each error type
|
||||
* @name: Name of the error
|
||||
* @synd_reg: Syndrome register address
|
||||
* @count_status_reg: Status register address to read the error count
|
||||
* @ways_status_reg: Status register address to read the error ways
|
||||
* @reg_cnt: Number of registers
|
||||
* @count_mask: Mask value to get the error count
|
||||
* @ways_mask: Mask value to get the error ways
|
||||
* @count_shift: Shift value to get the error count
|
||||
* @ways_shift: Shift value to get the error ways
|
||||
*/
|
||||
struct llcc_slice_config {
|
||||
u32 usecase_id;
|
||||
u32 slice_id;
|
||||
u32 max_cap;
|
||||
u32 priority;
|
||||
bool fixed_size;
|
||||
u32 bonus_ways;
|
||||
u32 res_ways;
|
||||
u32 cache_mode;
|
||||
u32 probe_target_ways;
|
||||
bool dis_cap_alloc;
|
||||
bool retain_on_pc;
|
||||
bool activate_on_init;
|
||||
struct llcc_edac_reg_data {
|
||||
char *name;
|
||||
u64 synd_reg;
|
||||
u64 count_status_reg;
|
||||
u64 ways_status_reg;
|
||||
u32 reg_cnt;
|
||||
u32 count_mask;
|
||||
u32 ways_mask;
|
||||
u8 count_shift;
|
||||
u8 ways_shift;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -93,30 +87,6 @@ struct llcc_drv_data {
|
|||
int ecc_irq;
|
||||
};
|
||||
|
||||
/**
|
||||
* llcc_edac_reg_data - llcc edac registers data for each error type
|
||||
* @name: Name of the error
|
||||
* @synd_reg: Syndrome register address
|
||||
* @count_status_reg: Status register address to read the error count
|
||||
* @ways_status_reg: Status register address to read the error ways
|
||||
* @reg_cnt: Number of registers
|
||||
* @count_mask: Mask value to get the error count
|
||||
* @ways_mask: Mask value to get the error ways
|
||||
* @count_shift: Shift value to get the error count
|
||||
* @ways_shift: Shift value to get the error ways
|
||||
*/
|
||||
struct llcc_edac_reg_data {
|
||||
char *name;
|
||||
u64 synd_reg;
|
||||
u64 count_status_reg;
|
||||
u64 ways_status_reg;
|
||||
u32 reg_cnt;
|
||||
u32 count_mask;
|
||||
u32 ways_mask;
|
||||
u8 count_shift;
|
||||
u8 ways_shift;
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_QCOM_LLCC)
|
||||
/**
|
||||
* llcc_slice_getd - get llcc slice descriptor
|
||||
|
|
@ -154,20 +124,6 @@ int llcc_slice_activate(struct llcc_slice_desc *desc);
|
|||
*/
|
||||
int llcc_slice_deactivate(struct llcc_slice_desc *desc);
|
||||
|
||||
/**
|
||||
* qcom_llcc_probe - program the sct table
|
||||
* @pdev: platform device pointer
|
||||
* @table: soc sct table
|
||||
* @sz: Size of the config table
|
||||
*/
|
||||
int qcom_llcc_probe(struct platform_device *pdev,
|
||||
const struct llcc_slice_config *table, u32 sz);
|
||||
|
||||
/**
|
||||
* qcom_llcc_remove - remove the sct table
|
||||
* @pdev: Platform device pointer
|
||||
*/
|
||||
int qcom_llcc_remove(struct platform_device *pdev);
|
||||
#else
|
||||
static inline struct llcc_slice_desc *llcc_slice_getd(u32 uid)
|
||||
{
|
||||
|
|
@ -197,16 +153,6 @@ static inline int llcc_slice_deactivate(struct llcc_slice_desc *desc)
|
|||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
static inline int qcom_llcc_probe(struct platform_device *pdev,
|
||||
const struct llcc_slice_config *table, u32 sz)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline int qcom_llcc_remove(struct platform_device *pdev)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue