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Qualcomm ARM64 DT updates for v5.19 

This adds MDIO bus description on the IPQ6018 platform.
 
 On MSM8916 the BAM-DMUX WWAN network device is added and the Huawei
 Ascend G7 gains sound card definition and clarified installation
 instructions.
 
 MSM8992 and MSM8994 continues to be worked on, gaining multimedia clock
 controller, on-chip memory, watchdog and various cleanup changes. The
 Xiaomi Mi 4C gains CPU regulators and fixes to the framebuffer
 definition, while Huawei Nexus 6P gains eMMC support.
 
 On MSM8996 the modem and sensor remtoeprocs are added and enabled in the
 Dragonboard 820c and the Xiaomi devices.
 
 On MSM8998 a few newly added clocks related to the sensor subsystem bus
 are marked as protected by default and the OnePlus devices gains NFC.
 
 The SC7180 platform and devices thereon are further polished and
 limozeen moves to using edp-panel for EDID-based detection, over
 statically defined panels.
 
 On SC7280 GPI DMA, WiFi remoteproc and network device, LPASS audio
 clocks, resets for SDCC controllers and a new CRD revision are added. A
 supply glitch on the PCIe power and a current leak for Bluetooth during
 suspend are corrected. The Herobrine board gains eDP support and the IDP
 gains backlight. USB is marked wakeup capable.
 
 On SDM845 the IPA, WLED based backlight and second WiFi channel are
 enabled for Xiaomi Pocophone F1, the firmware name is modified to not
 conflict with other boards.  On RB3 the CAN bus controller is added and
 the WiFi calibration variant is defined to allow adding the board's
 calibration information into linux-firmware.
 
 SM6350 gains I2C busses, UFS and WiFi support, and the numbering of
 uart9 is corrected.
 
 On SM7225 and the Fairphone 4 UFS, WiFi and haptics are enabled.
 
 On SM8150 PCIe, Ethernet and uSD card support is added, and enabled for
 the SA8155p ADP board. The PDC interrupt controller is also added and
 described as wakup interrupt parent for TLMM.
 
 Camera subsystem and control interface are defined for SM8250. On the
 Sony Xperia 1 II the audio amplifiers are enabled.
 
 On SM8350 GPI DMA engines are added and linked to the I2C and SPI
 serial engines. Surface Duo 2 gains battery charger support.
 
 On SM8450 the two PCIe controller/PHYs are enabled, GPI DMA and QUP
 serial engine instances are added. Remoteproc instances are enabled on
 SM8450 HDK.
 
 Last, but not least, a number of DeviceTree validation errors across
 various boards are corrected.
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Merge tag 'qcom-arm64-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm ARM64 DT updates for v5.19

This adds MDIO bus description on the IPQ6018 platform.

On MSM8916 the BAM-DMUX WWAN network device is added and the Huawei
Ascend G7 gains sound card definition and clarified installation
instructions.

MSM8992 and MSM8994 continues to be worked on, gaining multimedia clock
controller, on-chip memory, watchdog and various cleanup changes. The
Xiaomi Mi 4C gains CPU regulators and fixes to the framebuffer
definition, while Huawei Nexus 6P gains eMMC support.

On MSM8996 the modem and sensor remtoeprocs are added and enabled in the
Dragonboard 820c and the Xiaomi devices.

On MSM8998 a few newly added clocks related to the sensor subsystem bus
are marked as protected by default and the OnePlus devices gains NFC.

The SC7180 platform and devices thereon are further polished and
limozeen moves to using edp-panel for EDID-based detection, over
statically defined panels.

On SC7280 GPI DMA, WiFi remoteproc and network device, LPASS audio
clocks, resets for SDCC controllers and a new CRD revision are added. A
supply glitch on the PCIe power and a current leak for Bluetooth during
suspend are corrected. The Herobrine board gains eDP support and the IDP
gains backlight. USB is marked wakeup capable.

On SDM845 the IPA, WLED based backlight and second WiFi channel are
enabled for Xiaomi Pocophone F1, the firmware name is modified to not
conflict with other boards.  On RB3 the CAN bus controller is added and
the WiFi calibration variant is defined to allow adding the board's
calibration information into linux-firmware.

SM6350 gains I2C busses, UFS and WiFi support, and the numbering of
uart9 is corrected.

On SM7225 and the Fairphone 4 UFS, WiFi and haptics are enabled.

On SM8150 PCIe, Ethernet and uSD card support is added, and enabled for
the SA8155p ADP board. The PDC interrupt controller is also added and
described as wakup interrupt parent for TLMM.

Camera subsystem and control interface are defined for SM8250. On the
Sony Xperia 1 II the audio amplifiers are enabled.

On SM8350 GPI DMA engines are added and linked to the I2C and SPI
serial engines. Surface Duo 2 gains battery charger support.

On SM8450 the two PCIe controller/PHYs are enabled, GPI DMA and QUP
serial engine instances are added. Remoteproc instances are enabled on
SM8450 HDK.

Last, but not least, a number of DeviceTree validation errors across
various boards are corrected.

* tag 'qcom-arm64-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (150 commits)
  arm64: dts: qcom: Only include sc7180.dtsi in sc7180-trogdor.dtsi
  arm64: dts: qcom: sc7180-trogdor: Simplify spi0/spi6 labeling
  arm64: dts: qcom: sc7180-trogdor: Simplify trackpad enabling
  arm64: dts: qcom: sc7280: eDP for herobrine boards
  arm64: dts: qcom: sa8155p-adp: Disable multiple Tx and Rx queues for ethernet IP
  arm64: dts: qcom: sm8150: Fix iommu sid value for SDC2 controller
  arm64: dts: qcom: sm8350-duo2: enable battery charger
  arm64: dts: qcom: Enable pm8350c pwm for sc7280-idp2
  arm64: dts: qcom: pm8350c: Add pwm support
  arm64: dts: qcom: sc7280-qcard: Configure CTS pin to bias-bus-hold for bluetooth
  arm64: dts: qcom: sc7280-idp: Configure CTS pin to bias-bus-hold for bluetooth
  arm64: dts: qcom: sc7180: Remove ipa interconnect node
  arm64: dts: qcom: sc7280-idp: Enable GPI DMAs
  arm64: dts: qcom: sc7280: Add GENI I2C/SPI DMA channels
  arm64: dts: qcom: sc7280: Add GPI DMAengines
  arm64: dts: qcom: sm8450: Fix qmp phy node (use phy@ instead of lanes@)
  arm64: dts: qcom: db845c: Add support for MCP2517FD
  arm64: dts: qcom: qrb5165-rb5: Fix can-clock node name
  arm64: dts: qcom: sc7280: Add SAR sensors to herobrine crd
  arm64: dts: qcom: sm8250: camss: Add CCI definitions
  ...

Link: https://lore.kernel.org/r/20220509204451.325675-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-05-09 23:26:14 +02:00
parent 4c94666955 19794489fa
commit d4dcdc53c4
87 changed files with 6481 additions and 1863 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

172
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml Normal file
View File

@ -0,0 +1,172 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscorecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm LPASS Core & Audio Clock Controller Binding for SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm LPASS core and audio clock control module which supports the
clocks and power domains on SC7280.
See also:
- dt-bindings/clock/qcom,lpasscorecc-sc7280.h
- dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
properties:
clocks: true
clock-names: true
compatible:
enum:
- qcom,sc7280-lpassaoncc
- qcom,sc7280-lpassaudiocc
- qcom,sc7280-lpasscorecc
- qcom,sc7280-lpasshm
power-domains:
maxItems: 1
'#clock-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: qcom,sc7280-lpassaudiocc
then:
properties:
clocks:
items:
- description: Board XO source
- description: LPASS_AON_CC_MAIN_RCG_CLK_SRC
clock-names:
items:
- const: bi_tcxo
- const: lpass_aon_cc_main_rcg_clk_src
- if:
properties:
compatible:
contains:
enum:
- qcom,sc7280-lpassaoncc
then:
properties:
clocks:
items:
- description: Board XO source
- description: Board XO active only source
- description: LPASS_AON_CC_MAIN_RCG_CLK_SRC
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: iface
- if:
properties:
compatible:
contains:
enum:
- qcom,sc7280-lpasshm
- qcom,sc7280-lpasscorecc
then:
properties:
clocks:
items:
- description: Board XO source
clock-names:
items:
- const: bi_tcxo
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
lpass_audiocc: clock-controller@3300000 {
compatible = "qcom,sc7280-lpassaudiocc";
reg = <0x3300000 0x30000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
#clock-cells = <1>;
#power-domain-cells = <1>;
};
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
lpass_hm: clock-controller@3c00000 {
compatible = "qcom,sc7280-lpasshm";
reg = <0x3c00000 0x28>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "bi_tcxo";
#clock-cells = <1>;
#power-domain-cells = <1>;
};
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
lpasscore: clock-controller@3900000 {
compatible = "qcom,sc7280-lpasscorecc";
reg = <0x3900000 0x50000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "bi_tcxo";
power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
#clock-cells = <1>;
#power-domain-cells = <1>;
};
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
lpass_aon: clock-controller@3380000 {
compatible = "qcom,sc7280-lpassaoncc";
reg = <0x3380000 0x30000>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
<&lpasscore LPASS_CORE_CC_CORE_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao","iface";
#clock-cells = <1>;
#power-domain-cells = <1>;
};
...

5
arch/arm64/boot/dts/qcom/Makefile
View File

@ -83,11 +83,12 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r0.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r0.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb

6
arch/arm64/boot/dts/qcom/apq8096-db820c.dts
View File

@ -258,6 +258,12 @@ &mmcc {
vdd-gfx-supply = <&vdd_gfx>;
};
&mss_pil {
status = "okay";
pll-supply = <&vreg_l12a_1p8>;
firmware-name = "qcom/apq8096/mba.mbn", "qcom/apq8096/modem.mbn";
};
&pm8994_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;

2
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
View File

@ -39,7 +39,7 @@ &spi_0 {
cs-select = <0>;
status = "okay";
m25p80@0 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;

34
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View File

@ -318,12 +318,12 @@ i2c_0: i2c@78b6000 {
#size-cells = <0>;
reg = <0x0 0x078b6000 0x0 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp_dma 15>, <&blsp_dma 14>;
dma-names = "rx", "tx";
dmas = <&blsp_dma 14>, <&blsp_dma 15>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -333,12 +333,12 @@ i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */
#size-cells = <0>;
reg = <0x0 0x078b7000 0x0 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp_dma 17>, <&blsp_dma 16>;
dma-names = "rx", "tx";
dmas = <&blsp_dma 16>, <&blsp_dma 17>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -630,6 +630,16 @@ qrtr_requests {
};
};
mdio: mdio@90000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
reg = <0x0 0x90000 0x0 0x64>;
clocks = <&gcc GCC_MDIO_AHB_CLK>;
clock-names = "gcc_mdio_ahb_clk";
status = "disabled";
};
qusb_phy_1: qusb@59000 {
compatible = "qcom,ipq6018-qusb2-phy";
reg = <0x0 0x059000 0x0 0x180>;
@ -683,7 +693,6 @@ ssphy_0: ssphy@78000 {
reg = <0x0 0x78000 0x0 0x1C4>;
#address-cells = <2>;
#size-cells = <2>;
#clock-cells = <1>;
ranges;
clocks = <&gcc GCC_USB0_AUX_CLK>,
@ -695,12 +704,13 @@ ssphy_0: ssphy@78000 {
reset-names = "phy","common";
status = "disabled";
usb0_ssphy: lane@78200 {
usb0_ssphy: phy@78200 {
reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
<0x0 0x00078400 0x0 0x200>, /* Rx */
<0x0 0x00078800 0x0 0x1F8>, /* PCS */
<0x0 0x00078600 0x0 0x044>; /* PCS misc */
#phy-cells = <0>;
#clock-cells = <1>;
clocks = <&gcc GCC_USB0_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "gcc_usb0_pipe_clk_src";

2
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
View File

@ -35,7 +35,7 @@ &blsp1_i2c2 {
&blsp1_spi1 {
status = "okay";
m25p80@0 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";

2
arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
View File

@ -29,7 +29,7 @@ memory {
&blsp1_spi1 {
status = "ok";
m25p80@0 {
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";

42
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View File

@ -13,7 +13,7 @@ / {
clocks {
sleep_clk: sleep_clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-frequency = <32768>;
#clock-cells = <0>;
};
@ -467,12 +467,12 @@ blsp1_i2c2: i2c@78b6000 {
#size-cells = <0>;
reg = <0x078b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp_dma 15>, <&blsp_dma 14>;
dma-names = "rx", "tx";
dmas = <&blsp_dma 14>, <&blsp_dma 15>;
dma-names = "tx", "rx";
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "disabled";
@ -484,12 +484,12 @@ blsp1_i2c3: i2c@78b7000 {
#size-cells = <0>;
reg = <0x078b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <100000>;
dmas = <&blsp_dma 17>, <&blsp_dma 16>;
dma-names = "rx", "tx";
dmas = <&blsp_dma 16>, <&blsp_dma 17>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -499,12 +499,12 @@ blsp1_i2c5: i2c@78b9000 {
#size-cells = <0>;
reg = <0x78b9000 0x600>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp_dma 21>, <&blsp_dma 20>;
dma-names = "rx", "tx";
dmas = <&blsp_dma 20>, <&blsp_dma 21>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -514,12 +514,12 @@ blsp1_i2c6: i2c@78ba000 {
#size-cells = <0>;
reg = <0x078ba000 0x600>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <100000>;
dmas = <&blsp_dma 23>, <&blsp_dma 22>;
dma-names = "rx", "tx";
dmas = <&blsp_dma 22>, <&blsp_dma 23>;
dma-names = "tx", "rx";
status = "disabled";
};

59
arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts
View File

@ -8,18 +8,14 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/sound/apq8016-lpass.h>
/*
* Note: The original firmware from Huawei can only boot 32-bit kernels.
* To boot arm64 kernels it is necessary to flash 64-bit TZ/HYP firmware
* with EDL, e.g. taken from the DragonBoard 410c. This works because Huawei
* forgot to set up (firmware) secure boot for some reason.
*
* Also note that Huawei no longer provides bootloader unlock codes.
* This can be bypassed by patching the bootloader from a custom HYP firmware,
* making it think the bootloader is unlocked.
*
* See: https://wiki.postmarketos.org/wiki/Huawei_Ascend_G7_(huawei-g7)
* To boot this device tree using arm64 it is necessary to flash 64-bit TZ/HYP
* firmware (e.g. taken from the DragonBoard 410c).
* See https://wiki.postmarketos.org/wiki/Huawei_Ascend_G7_(huawei-g7)
* for suggested installation instructions.
*/
/ {
@ -216,6 +212,10 @@ &blsp1_uart2 {
status = "okay";
};
&lpass {
status = "okay";
};
&pm8916_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
@ -260,6 +260,40 @@ &sdhc_2 {
cd-gpios = <&msmgpio 56 GPIO_ACTIVE_LOW>;
};
&sound {
status = "okay";
model = "msm8916";
audio-routing =
"AMIC1", "MIC BIAS External1",
"AMIC2", "MIC BIAS External2",
"AMIC3", "MIC BIAS External1";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cdc_pdm_lines_act>;
pinctrl-1 = <&cdc_pdm_lines_sus>;
primary-dai-link {
link-name = "WCD";
cpu {
sound-dai = <&lpass MI2S_PRIMARY>;
};
codec {
sound-dai = <&lpass_codec 0>, <&wcd_codec 0>;
};
};
tertiary-dai-link {
link-name = "WCD-Capture";
cpu {
sound-dai = <&lpass MI2S_TERTIARY>;
};
codec {
sound-dai = <&lpass_codec 1>, <&wcd_codec 1>;
};
};
};
&usb {
status = "okay";
extcon = <&usb_id>, <&usb_id>;
@ -269,6 +303,13 @@ &usb_hs_phy {
extcon = <&usb_id>;
};
&wcd_codec {
qcom,micbias-lvl = <2800>;
qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
qcom,hphl-jack-type-normally-open;
};
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;

102
arch/arm64/boot/dts/qcom/msm8916.dtsi
View File

@ -299,7 +299,7 @@ rpm_requests: rpm-requests {
qcom,smd-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8916";
compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
#clock-cells = <1>;
};
@ -1314,6 +1314,20 @@ spmi_bus: spmi@200f000 {
#interrupt-cells = <4>;
};
bam_dmux_dma: dma-controller@4044000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x04044000 0x19000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
qcom,ee = <0>;
num-channels = <6>;
qcom,num-ees = <1>;
qcom,powered-remotely;
status = "disabled";
};
mpss: remoteproc@4080000 {
compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil";
reg = <0x04080000 0x100>,
@ -1357,6 +1371,22 @@ mpss {
memory-region = <&mpss_mem>;
};
bam_dmux: bam-dmux {
compatible = "qcom,bam-dmux";
interrupt-parent = <&hexagon_smsm>;
interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "pc", "pc-ack";
qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
qcom,smem-state-names = "pc", "pc-ack";
dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
dma-names = "tx", "rx";
status = "disabled";
};
smd-edge {
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
@ -1485,8 +1515,8 @@ blsp1_uart1: serial@78af000 {
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 1>, <&blsp_dma 0>;
dma-names = "rx", "tx";
dmas = <&blsp_dma 0>, <&blsp_dma 1>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart1_default>;
pinctrl-1 = <&blsp1_uart1_sleep>;
@ -1499,8 +1529,8 @@ blsp1_uart2: serial@78b0000 {
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 3>, <&blsp_dma 2>;
dma-names = "rx", "tx";
dmas = <&blsp_dma 2>, <&blsp_dma 3>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart2_default>;
pinctrl-1 = <&blsp1_uart2_sleep>;
@ -1511,9 +1541,9 @@ blsp_i2c1: i2c@78b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b5000 0x500>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_default>;
pinctrl-1 = <&i2c1_sleep>;
@ -1529,8 +1559,8 @@ blsp_spi1: spi@78b5000 {
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 5>, <&blsp_dma 4>;
dma-names = "rx", "tx";
dmas = <&blsp_dma 4>, <&blsp_dma 5>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi1_default>;
pinctrl-1 = <&spi1_sleep>;
@ -1543,9 +1573,9 @@ blsp_i2c2: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b6000 0x500>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c2_default>;
pinctrl-1 = <&i2c2_sleep>;
@ -1561,8 +1591,8 @@ blsp_spi2: spi@78b6000 {
clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 7>, <&blsp_dma 6>;
dma-names = "rx", "tx";
dmas = <&blsp_dma 6>, <&blsp_dma 7>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi2_default>;
pinctrl-1 = <&spi2_sleep>;
@ -1575,9 +1605,9 @@ blsp_i2c3: i2c@78b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b7000 0x500>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c3_default>;
pinctrl-1 = <&i2c3_sleep>;
@ -1593,8 +1623,8 @@ blsp_spi3: spi@78b7000 {
clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 9>, <&blsp_dma 8>;
dma-names = "rx", "tx";
dmas = <&blsp_dma 8>, <&blsp_dma 9>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi3_default>;
pinctrl-1 = <&spi3_sleep>;
@ -1607,9 +1637,9 @@ blsp_i2c4: i2c@78b8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b8000 0x500>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c4_default>;
pinctrl-1 = <&i2c4_sleep>;
@ -1625,8 +1655,8 @@ blsp_spi4: spi@78b8000 {
clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 11>, <&blsp_dma 10>;
dma-names = "rx", "tx";
dmas = <&blsp_dma 10>, <&blsp_dma 11>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi4_default>;
pinctrl-1 = <&spi4_sleep>;
@ -1639,9 +1669,9 @@ blsp_i2c5: i2c@78b9000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b9000 0x500>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c5_default>;
pinctrl-1 = <&i2c5_sleep>;
@ -1657,8 +1687,8 @@ blsp_spi5: spi@78b9000 {
clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 13>, <&blsp_dma 12>;
dma-names = "rx", "tx";
dmas = <&blsp_dma 12>, <&blsp_dma 13>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi5_default>;
pinctrl-1 = <&spi5_sleep>;
@ -1671,9 +1701,9 @@ blsp_i2c6: i2c@78ba000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078ba000 0x500>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c6_default>;
pinctrl-1 = <&i2c6_sleep>;
@ -1689,8 +1719,8 @@ blsp_spi6: spi@78ba000 {
clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 15>, <&blsp_dma 14>;
dma-names = "rx", "tx";
dmas = <&blsp_dma 14>, <&blsp_dma 15>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi6_default>;
pinctrl-1 = <&spi6_sleep>;
@ -1788,7 +1818,7 @@ wcnss_ctrl: wcnss {
qcom,mmio = <&pronto>;
bt {
bluetooth {
compatible = "qcom,wcnss-bt";
};

52
arch/arm64/boot/dts/qcom/msm8953.dtsi
View File

@ -321,12 +321,12 @@ rpm {
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
rpm_requests: rpm_requests {
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8953";
qcom,smd-channels = "rpm_requests";
rpmcc: rpmcc {
compatible = "qcom,rpmcc-msm8953";
compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc";
clocks = <&xo_board>;
clock-names = "xo";
#clock-cells = <1>;
@ -923,9 +923,9 @@ i2c_1: i2c@78b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_1_default>;
@ -941,9 +941,9 @@ i2c_2: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_2_default>;
@ -959,9 +959,9 @@ i2c_3: i2c@78b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_3_default>;
pinctrl-1 = <&i2c_3_sleep>;
@ -976,9 +976,9 @@ i2c_4: i2c@78b8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b8000 0x600>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_4_default>;
pinctrl-1 = <&i2c_4_sleep>;
@ -993,9 +993,9 @@ i2c_5: i2c@7af5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x7af5000 0x600>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_5_default>;
pinctrl-1 = <&i2c_5_sleep>;
@ -1010,9 +1010,9 @@ i2c_6: i2c@7af6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x7af6000 0x600>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_6_default>;
pinctrl-1 = <&i2c_6_sleep>;
@ -1027,9 +1027,9 @@ i2c_7: i2c@7af7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x7af7000 0x600>;
interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_7_default>;
pinctrl-1 = <&i2c_7_sleep>;
@ -1044,9 +1044,9 @@ i2c_8: i2c@7af8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x7af8000 0x600>;
interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_8_default>;
pinctrl-1 = <&i2c_8_sleep>;

36
arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
View File

@ -23,20 +23,31 @@ / {
/* This enables graphical output via bootloader-enabled display */
chosen {
bootargs = "earlycon=tty0 console=tty0";
bootargs = "earlycon=tty0 console=tty0 maxcpus=1";
#address-cells = <2>;
#size-cells = <2>;
ranges;
framebuffer0: framebuffer@3404000 {
status= "okay";
framebuffer0: framebuffer@3400000 {
compatible = "simple-framebuffer";
reg = <0 0x3404000 0 (1080 * 1920 * 3)>;
reg = <0 0x3400000 0 (1080 * 1920 * 3)>;
width = <1080>;
height = <1920>;
stride = <(1080 * 3)>;
format = "r8g8b8";
/*
* That's a lot of clocks, but it's necessary due
* to unused clk cleanup & no panel driver yet..
*/
clocks = <&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
<&mmcc MDSS_VSYNC_CLK>,
<&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_BYTE0_CLK>,
<&mmcc MDSS_PCLK0_CLK>,
<&mmcc MDSS_ESC0_CLK>;
power-domains = <&mmcc MDSS_GDSC>;
};
};
@ -126,6 +137,23 @@ &peripheral_region {
no-map;
};
&pm8994_spmi_regulators {
VDD_APC0: s8 {
regulator-min-microvolt = <680000>;
regulator-max-microvolt = <1180000>;
regulator-always-on;
regulator-boot-on;
};
/* APC1 is 3-phase, but quoting downstream, s11 is "the gang leader" */
VDD_APC1: s11 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1225000>;
regulator-always-on;
regulator-boot-on;
};
};
&rpm_requests {
pm8994-regulators {
compatible = "qcom,rpm-pm8994-regulators";

24
arch/arm64/boot/dts/qcom/msm8992.dtsi
View File

@ -10,8 +10,30 @@
/delete-node/ &cpu6_map;
/delete-node/ &cpu7_map;
&gcc {
compatible = "qcom,gcc-msm8992";
};
&mmcc {
compatible = "qcom,mmcc-msm8992";
assigned-clock-rates = <800000000>,
<808000000>,
<1020000000>,
<960000000>,
<800000000>;
};
&ocmem {
reg = <0xfdd00000 0x2000>, <0xfec00000 0x100000>;
gmu-sram@0 {
reg = <0x0 0x80000>;
};
};
&rpmcc {
compatible = "qcom,rpmcc-msm8992";
compatible = "qcom,rpmcc-msm8992", "qcom,rpmcc";
};
&tcsr_mutex {

21
arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2015, Huawei Inc. All rights reserved.
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Petr Vorel <petr.vorel@gmail.com>
* Copyright (c) 2021-2022, Petr Vorel <petr.vorel@gmail.com>
*/
/dts-v1/;
@ -27,17 +27,20 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
};
soc {
serial@f991e000 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart2_default>;
pinctrl-1 = <&blsp1_uart2_sleep>;
};
};
&blsp1_uart2 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart2_default>;
pinctrl-1 = <&blsp1_uart2_sleep>;
};
&tlmm {
gpio-reserved-ranges = <85 4>;
};
&sdhc1 {
status = "okay";
mmc-hs400-1_8v;
};

89
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi
View File

@ -108,13 +108,6 @@ &blsp1_i2c2 {
/* NXP PN547 NFC */
};
&blsp1_i2c4 {
status = "okay";
clock-frequency = <355000>;
/* Empty but active */
};
&blsp1_i2c6 {
status = "okay";
clock-frequency = <355000>;
@ -194,26 +187,38 @@ vdd_gfx: s2@1700 {
};
&rpm_requests {
/* PMI8994 should probe first, because pmi8994_bby supplies some of PM8994's regulators */
pmi8994_regulators: pmi8994-regulators {
compatible = "qcom,rpm-pmi8994-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_bst_byp-supply = <&vph_pwr>;
pmi8994_s1: s1 {
regulator-min-microvolt = <1025000>;
regulator-max-microvolt = <1025000>;
};
/* S2 & S3 - VDD_GFX */
pmi8994_bby: boost-bypass {
regulator-min-microvolt = <3150000>;
regulator-max-microvolt = <3600000>;
};
};
pm8994_regulators: pm8994-regulators {
compatible = "qcom,rpm-pm8994-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_s2-supply = <&vph_pwr>;
vdd_s3-supply = <&vph_pwr>;
vdd_s4-supply = <&vph_pwr>;
vdd_s5-supply = <&vph_pwr>;
vdd_s6-supply = <&vph_pwr>;
vdd_s7-supply = <&vph_pwr>;
vdd_s8-supply = <&vph_pwr>;
vdd_s9-supply = <&vph_pwr>;
vdd_s10-supply = <&vph_pwr>;
vdd_s11-supply = <&vph_pwr>;
vdd_s12-supply = <&vph_pwr>;
vdd_l1-supply = <&pmi8994_s1>;
vdd_l2_l26_l28-supply = <&pm8994_s3>;
vdd_l3_l11-supply = <&pm8994_s3>;
vdd_l4_l27_l31-supply = <&pm8994_s3>;
vdd_l5_l7-supply = <&pm8994_s5>;
vdd_l6_l12_l32-supply = <&pm8994_s5>;
vdd_l8_l16_l30-supply = <&vph_pwr>;
vdd_l9_l10_l18_l22-supply = <&pmi8994_bby>;
@ -234,9 +239,9 @@ pm8994_s3: s3 {
pm8994_s4: s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-system-load = <325000>;
regulator-allow-set-load;
regulator-always-on;
regulator-system-load = <325000>;
};
pm8994_s5: s5 {
@ -262,13 +267,14 @@ pm8994_l1: l1 {
pm8994_l2: l2 {
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
regulator-allow-set-load;
regulator-system-load = <10000>;
regulator-allow-set-load;
};
pm8994_l3: l3 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
};
pm8994_l4: l4 {
@ -308,8 +314,8 @@ pm8994_l11: l11 {
pm8994_l12: l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-allow-set-load;
regulator-system-load = <10000>;
regulator-allow-set-load;
};
pm8994_l13: l13 {
@ -320,8 +326,9 @@ pm8994_l13: l13 {
pm8994_l14: l14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-allow-set-load;
regulator-system-load = <10000>;
regulator-allow-set-load;
regulator-boot-on;
};
pm8994_l15: l15 {
@ -337,44 +344,47 @@ pm8994_l16: l16 {
pm8994_l17: l17 {
regulator-min-microvolt = <2200000>;
regulator-max-microvolt = <2200000>;
regulator-boot-on;
};
pm8994_l18: l18 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
regulator-boot-on;
};
pm8994_l19: l19 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-boot-on;
};
pm8994_l20: l20 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-always-on;
regulator-boot-on;
regulator-allow-set-load;
regulator-system-load = <570000>;
regulator-allow-set-load;
};
pm8994_l21: l21 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-always-on;
regulator-allow-set-load;
regulator-system-load = <800000>;
regulator-allow-set-load;
};
pm8994_l22: l22 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
};
pm8994_l23: l23 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-boot-on;
};
pm8994_l24: l24 {
@ -385,6 +395,7 @@ pm8994_l24: l24 {
pm8994_l25: l25 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
};
pm8994_l26: l26 {
@ -395,30 +406,33 @@ pm8994_l26: l26 {
pm8994_l27: l27 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
};
pm8994_l28: l28 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-allow-set-load;
regulator-system-load = <10000>;
regulator-allow-set-load;
};
pm8994_l29: l29 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
regulator-boot-on;
};
pm8994_l30: l30 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
pm8994_l31: l31 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-allow-set-load;
regulator-system-load = <10000>;
regulator-allow-set-load;
};
pm8994_l32: l32 {
@ -426,26 +440,11 @@ pm8994_l32: l32 {
regulator-max-microvolt = <1800000>;
};
pm8994_lvs1: lvs1 {};
pm8994_lvs2: lvs2 {};
};
pmi8994_regulators: pmi8994-regulators {
compatible = "qcom,rpm-pmi8994-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_bst_byp-supply = <&vph_pwr>;
pmi8994_s1: s1 {
regulator-min-microvolt = <1025000>;
regulator-max-microvolt = <1025000>;
pm8994_lvs1: lvs1 {
regulator-boot-on;
};
/* S2 & S3 - VDD_GFX */
pmi8994_bby: boost-bypass {
regulator-min-microvolt = <3150000>;
regulator-max-microvolt = <3600000>;
pm8994_lvs2: lvs2 {
regulator-boot-on;
};
};
};

126
arch/arm64/boot/dts/qcom/msm8994.dtsi
View File

@ -4,6 +4,8 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8994.h>
#include <dt-bindings/clock/qcom,mmcc-msm8994.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
/ {
@ -12,6 +14,11 @@ / {
#address-cells = <2>;
#size-cells = <2>;
aliases {
mmc1 = &sdhc1;
mmc2 = &sdhc2;
};
chosen { };
clocks {
@ -183,8 +190,8 @@ dfps_data_mem: dfps_data_mem@3400000 {
no-map;
};
cont_splash_mem: memory@3800000 {
reg = <0 0x03800000 0 0x2400000>;
cont_splash_mem: memory@3401000 {
reg = <0 0x03401000 0 0x2200000>;
no-map;
};
@ -233,7 +240,6 @@ rpm {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
qcom,local-pid = <0>;
qcom,remote-pid = <6>;
rpm_requests: rpm-requests {
@ -241,7 +247,7 @@ rpm_requests: rpm-requests {
qcom,smd-channels = "rpm_requests";
rpmcc: rpmcc {
compatible = "qcom,rpmcc-msm8994";
compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
#clock-cells = <1>;
};
@ -354,6 +360,15 @@ apcs: mailbox@f900d000 {
#mbox-cells = <1>;
};
watchdog@f9017000 {
compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt";
reg = <0xf9017000 0x1000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
clocks = <&sleep_clk>;
timeout-sec = <10>;
};
timer@f9020000 {
#address-cells = <1>;
#size-cells = <1>;
@ -498,7 +513,7 @@ blsp1_dma: dma-controller@f9904000 {
#dma-cells = <1>;
qcom,ee = <0>;
qcom,controlled-remotely;
num-channels = <18>;
num-channels = <24>;
qcom,num-ees = <4>;
};
@ -519,9 +534,9 @@ blsp1_i2c1: i2c@f9923000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9923000 0x500>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
dma-names = "tx", "rx";
@ -555,9 +570,9 @@ blsp1_i2c2: i2c@f9924000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9924000 0x500>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
dma-names = "tx", "rx";
@ -575,9 +590,9 @@ blsp1_i2c4: i2c@f9926000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9926000 0x500>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
dma-names = "tx", "rx";
@ -593,9 +608,9 @@ blsp1_i2c5: i2c@f9927000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9927000 0x500>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
dma-names = "tx", "rx";
@ -611,9 +626,9 @@ blsp1_i2c6: i2c@f9928000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9928000 0x500>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
dma-names = "tx", "rx";
@ -634,7 +649,7 @@ blsp2_dma: dma-controller@f9944000 {
#dma-cells = <1>;
qcom,ee = <0>;
qcom,controlled-remotely;
num-channels = <18>;
num-channels = <24>;
qcom,num-ees = <4>;
};
@ -657,9 +672,9 @@ blsp2_i2c1: i2c@f9963000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9963000 0x500>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
dma-names = "tx", "rx";
@ -693,9 +708,9 @@ blsp2_i2c5: i2c@f9967000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9967000 0x500>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <355000>;
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
dma-names = "tx", "rx";
@ -714,7 +729,7 @@ gcc: clock-controller@fc400000 {
#power-domain-cells = <1>;
reg = <0xfc400000 0x2000>;
clock-names = "xo", "sleep_clk";
clock-names = "xo", "sleep";
clocks = <&xo_board>, <&sleep_clk>;
};
@ -1012,6 +1027,61 @@ sdc2_data_off: sdc2-data-off {
drive-strength = <2>;
};
};
mmcc: clock-controller@fd8c0000 {
compatible = "qcom,mmcc-msm8994";
reg = <0xfd8c0000 0x5200>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clock-names = "xo",
"gpll0",
"mmssnoc_ahb",
"oxili_gfx3d_clk_src",
"dsi0pll",
"dsi0pllbyte",
"dsi1pll",
"dsi1pllbyte",
"hdmipll";
clocks = <&xo_board>,
<&gcc GPLL0_OUT_MMSSCC>,
<&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>,
<&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
<0>,
<0>,
<0>,
<0>,
<0>;
assigned-clocks = <&mmcc MMPLL0_PLL>,
<&mmcc MMPLL1_PLL>,
<&mmcc MMPLL3_PLL>,
<&mmcc MMPLL4_PLL>,
<&mmcc MMPLL5_PLL>;
assigned-clock-rates = <800000000>,
<1167000000>,
<1020000000>,
<960000000>,
<600000000>;
};
ocmem: ocmem@fdd00000 {
compatible = "qcom,msm8974-ocmem";
reg = <0xfdd00000 0x2000>,
<0xfec00000 0x200000>;
reg-names = "ctrl", "mem";
clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
<&mmcc OCMEMCX_OCMEMNOC_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <1>;
gmu_sram: gmu-sram@0 {
reg = <0x0 0x180000>;
};
};
};
timer: timer {

8
arch/arm64/boot/dts/qcom/msm8996-mtp.dts
View File

@ -18,12 +18,10 @@ aliases {
chosen {
stdout-path = "serial0";
};
};
soc {
serial@75b0000 {
status = "okay";
};
};
&blsp2_uart2 {
status = "okay";
};
&hdmi {

18
arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
View File

@ -13,9 +13,10 @@
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
/delete-node/ &slpi_region;
/delete-node/ &venus_region;
/delete-node/ &zap_shader_region;
/delete-node/ &adsp_mem;
/delete-node/ &slpi_mem;
/delete-node/ &venus_mem;
/delete-node/ &gpu_mem;
/ {
qcom,msm-id = <246 0x30001>; /* MSM8996 V3.1 (Final) */
@ -46,18 +47,23 @@ cont_splash_mem: memory@83401000 {
no-map;
};
zap_shader_region: gpu@90400000 {
adsp_mem: adsp@8ea00000 {
reg = <0x0 0x8ea00000 0x0 0x1a00000>;
no-map;
};
gpu_mem: gpu@90400000 {
compatible = "shared-dma-pool";
reg = <0x0 0x90400000 0x0 0x2000>;
no-map;
};
slpi_region: memory@90500000 {
slpi_mem: memory@90500000 {
reg = <0 0x90500000 0 0xa00000>;
no-map;
};
venus_region: memory@90f00000 {
venus_mem: memory@90f00000 {
reg = <0 0x90f00000 0 0x500000>;
no-map;
};

36
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
View File

@ -66,32 +66,32 @@ memory@88800000 {
/* This platform has all PIL regions offset by 0x1400000 */
/delete-node/ mpss@88800000;
mpss_region: mpss@89c00000 {
mpss_mem: mpss@89c00000 {
reg = <0x0 0x89c00000 0x0 0x6200000>;
no-map;
};
/delete-node/ adsp@8ea00000;
adsp_region: adsp@8ea00000 {
adsp_mem: adsp@8fe00000 {
reg = <0x0 0x8fe00000 0x0 0x1b00000>;
no-map;
};
/delete-node/ slpi@90b00000;
slpi_region: slpi@91900000 {
/delete-node/ slpi@90500000;
slpi_mem: slpi@91900000 {
reg = <0x0 0x91900000 0x0 0xa00000>;
no-map;
};
/delete-node/ gpu@8f200000;
zap_shader_region: gpu@92300000 {
/delete-node/ gpu@90f00000;
gpu_mem: gpu@92300000 {
compatible = "shared-dma-pool";
reg = <0x0 0x92300000 0x0 0x2000>;
no-map;
};
/delete-node/ venus@91000000;
venus_region: venus@90400000 {
venus_mem: venus@92400000 {
reg = <0x0 0x92400000 0x0 0x500000>;
no-map;
};
@ -107,7 +107,7 @@ ramoops@92900000 {
pmsg-size = <0x40000>;
};
/delete-node/ rmtfs@86700000;
/delete-node/ rmtfs;
rmtfs@f6c00000 {
compatible = "qcom,rmtfs-mem";
reg = <0 0xf6c00000 0 0x200000>;
@ -118,7 +118,7 @@ rmtfs@f6c00000 {
};
/delete-node/ mba@91500000;
mba_region: mba@f6f00000 {
mba_mem: mba@f6f00000 {
reg = <0x0 0xf6f00000 0x0 0x100000>;
no-map;
};
@ -267,6 +267,12 @@ &mmcc {
vdd-gfx-supply = <&vdd_gfx>;
};
&mss_pil {
status = "okay";
pll-supply = <&vreg_l12a_1p8>;
};
&pcie0 {
status = "okay";
@ -291,6 +297,12 @@ &pm8994_resin {
linux,code = <KEY_VOLUMEDOWN>;
};
&slpi_pil {
status = "okay";
px-supply = <&vreg_lvs2a_1p8>;
};
&usb3 {
status = "okay";
extcon = <&typec>;
@ -336,13 +348,7 @@ &ufsphy {
vdda-phy-supply = <&vreg_l28a_0p925>;
vdda-pll-supply = <&vreg_l12a_1p8>;
vdda-phy-max-microamp = <18380>;
vdda-pll-max-microamp = <9440>;
vddp-ref-clk-supply = <&vreg_l25a_1p2>;
vddp-ref-clk-max-microamp = <100>;
vddp-ref-clk-always-on;
};
&venus {

9
arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts
View File

@ -130,6 +130,11 @@ &pmi8994_wled {
status = "okay";
};
&mss_pil {
firmware-name = "qcom/msm8996/gemini/mba.mbn",
"qcom/msm8996/gemini/modem.mbn";
};
&q6asmdai {
dai@0 {
reg = <0>;
@ -144,6 +149,10 @@ dai@2 {
};
};
&slpi_pil {
firmware-name = "qcom/msm8996/gemini/slpi.mbn";
};
&sound {
compatible = "qcom,apq8096-sndcard";
model = "gemini";

9
arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts
View File

@ -111,6 +111,11 @@ &mdss {
status = "disabled";
};
&mss_pil {
firmware-name = "qcom/msm8996/scorpio/mba.mbn",
"qcom/msm8996/scorpio/modem.mbn";
};
&q6asmdai {
dai@0 {
reg = <0>;
@ -125,6 +130,10 @@ dai@2 {
};
};
&slpi_pil {
firmware-name = "qcom/msm8996/scorpio/slpi.mbn";
};
&sound {
compatible = "qcom,apq8096-sndcard";
model = "scorpio";

256
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@ -384,28 +384,13 @@ reserved-memory {
#size-cells = <2>;
ranges;
mba_region: mba@91500000 {
reg = <0x0 0x91500000 0x0 0x200000>;
hyp_mem: memory@85800000 {
reg = <0x0 0x85800000 0x0 0x600000>;
no-map;
};
slpi_region: slpi@90b00000 {
reg = <0x0 0x90b00000 0x0 0xa00000>;
no-map;
};
venus_region: venus@90400000 {
reg = <0x0 0x90400000 0x0 0x700000>;
no-map;
};
adsp_region: adsp@8ea00000 {
reg = <0x0 0x8ea00000 0x0 0x1a00000>;
no-map;
};
mpss_region: mpss@88800000 {
reg = <0x0 0x88800000 0x0 0x6200000>;
xbl_mem: memory@85e00000 {
reg = <0x0 0x85e00000 0x0 0x200000>;
no-map;
};
@ -414,17 +399,12 @@ smem_mem: smem-mem@86000000 {
no-map;
};
memory@85800000 {
reg = <0x0 0x85800000 0x0 0x800000>;
no-map;
};
memory@86200000 {
tz_mem: memory@86200000 {
reg = <0x0 0x86200000 0x0 0x2600000>;
no-map;
};
rmtfs@86700000 {
rmtfs_mem: rmtfs {
compatible = "qcom,rmtfs-mem";
size = <0x0 0x200000>;
@ -435,9 +415,34 @@ rmtfs@86700000 {
qcom,vmid = <15>;
};
zap_shader_region: gpu@8f200000 {
mpss_mem: mpss@88800000 {
reg = <0x0 0x88800000 0x0 0x6200000>;
no-map;
};
adsp_mem: adsp@8ea00000 {
reg = <0x0 0x8ea00000 0x0 0x1b00000>;
no-map;
};
slpi_mem: slpi@90500000 {
reg = <0x0 0x90500000 0x0 0xa00000>;
no-map;
};
gpu_mem: gpu@90f00000 {
compatible = "shared-dma-pool";
reg = <0x0 0x90b00000 0x0 0xa00000>;
reg = <0x0 0x90f00000 0x0 0x100000>;
no-map;
};
venus_mem: venus@91000000 {
reg = <0x0 0x91000000 0x0 0x500000>;
no-map;
};
mba_mem: mba@91500000 {
reg = <0x0 0x91500000 0x0 0x200000>;
no-map;
};
};
@ -456,7 +461,7 @@ rpm_requests: rpm-requests {
qcom,glink-channels = "rpm_requests";
rpmcc: qcom,rpmcc {
compatible = "qcom,rpmcc-msm8996";
compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
#clock-cells = <1>;
};
@ -513,12 +518,12 @@ smp2p-adsp {
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
smp2p_adsp_out: master-kernel {
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_adsp_in: slave-kernel {
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
@ -526,7 +531,7 @@ smp2p_adsp_in: slave-kernel {
};
};
smp2p-modem {
smp2p-mpss {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
@ -537,12 +542,12 @@ smp2p-modem {
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
modem_smp2p_out: master-kernel {
mpss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
modem_smp2p_in: slave-kernel {
mpss_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
@ -561,16 +566,17 @@ smp2p-slpi {
qcom,local-pid = <0>;
qcom,remote-pid = <3>;
smp2p_slpi_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_slpi_out: master-kernel {
slpi_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
slpi_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
soc: soc {
@ -707,7 +713,7 @@ tsens1: thermal-sensor@4ad000 {
#thermal-sensor-cells = <1>;
};
cryptobam: dma@644000 {
cryptobam: dma-controller@644000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x00644000 0x24000>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
@ -788,7 +794,7 @@ mdp: mdp@901000 {
reg-names = "mdp_phys";
interrupt-parent = <&mdss>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <0>;
clocks = <&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
@ -834,7 +840,7 @@ dsi0: dsi@994000 {
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <4>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_BYTE0_CLK>,
@ -904,7 +910,7 @@ hdmi: hdmi-tx@9a0000 {
"hdcp_physical";
interrupt-parent = <&mdss>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <8>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_AHB_CLK>,
@ -1033,7 +1039,7 @@ opp-133000000 {
};
zap-shader {
memory-region = <&zap_shader_region>;
memory-region = <&gpu_mem>;
};
};
@ -1574,7 +1580,7 @@ agnoc@0 {
ranges;
pcie0: pcie@600000 {
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
compatible = "qcom,pcie-msm8996";
status = "disabled";
power-domains = <&gcc PCIE0_GDSC>;
bus-range = <0x00 0xff>;
@ -1626,7 +1632,7 @@ pcie0: pcie@600000 {
};
pcie1: pcie@608000 {
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
compatible = "qcom,pcie-msm8996";
power-domains = <&gcc PCIE1_GDSC>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
@ -1679,7 +1685,7 @@ pcie1: pcie@608000 {
};
pcie2: pcie@610000 {
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
compatible = "qcom,pcie-msm8996";
power-domains = <&gcc PCIE2_GDSC>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
@ -1730,7 +1736,8 @@ pcie2: pcie@610000 {
};
ufshc: ufshc@624000 {
compatible = "qcom,ufshc";
compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0x00624000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
@ -2026,7 +2033,7 @@ venus: video-codec@c00000 {
<&venus_smmu 0x2c>,
<&venus_smmu 0x2d>,
<&venus_smmu 0x31>;
memory-region = <&venus_region>;
memory-region = <&venus_mem>;
status = "disabled";
video-decoder {
@ -2122,6 +2129,105 @@ lpass_q6_smmu: iommu@1600000 {
clock-names = "iface", "bus";
};
slpi_pil: remoteproc@1c00000 {
compatible = "qcom,msm8996-slpi-pil";
reg = <0x01c00000 0x4000>;
interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog",
"fatal",
"ready",
"handover",
"stop-ack";
clocks = <&xo_board>,
<&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
clock-names = "xo", "aggre2";
memory-region = <&slpi_mem>;
qcom,smem-states = <&slpi_smp2p_out 0>;
qcom,smem-state-names = "stop";
power-domains = <&rpmpd MSM8996_VDDSSCX>;
power-domain-names = "ssc_cx";
status = "disabled";
smd-edge {
interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
label = "dsps";
mboxes = <&apcs_glb 25>;
qcom,smd-edge = <3>;
qcom,remote-pid = <3>;
};
};
mss_pil: remoteproc@2080000 {
compatible = "qcom,msm8996-mss-pil";
reg = <0x2080000 0x100>,
<0x2180000 0x020>;
reg-names = "qdsp6", "rmb";
interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
<&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
<&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack",
"shutdown-ack";
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
<&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
<&gcc GCC_BOOT_ROM_AHB_CLK>,
<&xo_board>,
<&gcc GCC_MSS_GPLL0_DIV_CLK>,
<&gcc GCC_MSS_SNOC_AXI_CLK>,
<&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
<&rpmcc RPM_SMD_PCNOC_CLK>,
<&rpmcc RPM_SMD_QDSS_CLK>;
clock-names = "iface", "bus", "mem", "xo", "gpll0_mss",
"snoc_axi", "mnoc_axi", "pnoc", "qdss";
resets = <&gcc GCC_MSS_RESTART>;
reset-names = "mss_restart";
power-domains = <&rpmpd MSM8996_VDDCX>,
<&rpmpd MSM8996_VDDMX>;
power-domain-names = "cx", "mx";
qcom,smem-states = <&mpss_smp2p_out 0>;
qcom,smem-state-names = "stop";
qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
status = "disabled";
mba {
memory-region = <&mba_mem>;
};
mpss {
memory-region = <&mpss_mem>;
};
smd-edge {
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
label = "mpss";
mboxes = <&apcs_glb 12>;
qcom,smd-edge = <0>;
qcom,remote-pid = <1>;
};
};
stm@3002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x3002000 0x1000>,
@ -2786,9 +2892,9 @@ blsp1_i2c3: i2c@7577000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07577000 0x1000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c3_default>;
pinctrl-1 = <&blsp1_i2c3_sleep>;
@ -2834,9 +2940,9 @@ blsp2_i2c1: i2c@75b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b5000 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c1_default>;
pinctrl-1 = <&blsp2_i2c1_sleep>;
@ -2851,9 +2957,9 @@ blsp2_i2c2: i2c@75b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b6000 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c2_default>;
pinctrl-1 = <&blsp2_i2c2_sleep>;
@ -2868,9 +2974,9 @@ blsp2_i2c3: i2c@75b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b7000 0x1000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c3_default>;
@ -2886,9 +2992,9 @@ blsp2_i2c5: i2c@75b9000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x75b9000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp2_i2c5_default>;
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
@ -2902,9 +3008,9 @@ blsp2_i2c6: i2c@75ba000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x75ba000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c6_default>;
pinctrl-1 = <&blsp2_i2c6_sleep>;
@ -3023,19 +3129,19 @@ adsp_pil: remoteproc@9300000 {
reg = <0x09300000 0x80000>;
interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmcc RPM_SMD_BB_CLK1>;
clock-names = "xo";
memory-region = <&adsp_region>;
memory-region = <&adsp_mem>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
power-domains = <&rpmpd MSM8996_VDDCX>;

31
arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi
View File

@ -188,6 +188,23 @@ rmi4_f12: rmi4-f12@12 {
};
};
&blsp1_i2c6 {
status = "okay";
nfc@28 {
compatible = "nxp,nxp-nci-i2c";
reg = <0x28>;
interrupt-parent = <&tlmm>;
interrupts = <92 IRQ_TYPE_LEVEL_HIGH>;
enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
};
};
&blsp1_uart3 {
status = "okay";
@ -462,6 +479,20 @@ ts_reset_active: ts-reset-active {
drive-strength = <8>;
bias-pull-up;
};
nfc_int_active: nfc-int-active {
pins = "gpio92";
function = "gpio";
drive-strength = <6>;
bias-pull-up;
};
nfc_enable_active: nfc-enable-active {
pins = "gpio12", "gpio116";
function = "gpio";
drive-strength = <6>;
bias-pull-up;
};
};
&ufshc {

15
arch/arm64/boot/dts/qcom/msm8998.dtsi
View File

@ -815,6 +815,21 @@ gcc: clock-controller@100000 {
clock-names = "xo", "sleep_clk";
clocks = <&xo>, <&sleep_clk>;
/*
* The hypervisor typically configures the memory region where these clocks
* reside as read-only for the HLOS. If the HLOS tried to enable or disable
* these clocks on a device with such configuration (e.g. because they are
* enabled but unused during boot-up), the device will most likely decide
* to reboot.
* In light of that, we are conservative here and we list all such clocks
* as protected. The board dts (or a user-supplied dts) can override the
* list of protected clocks if it differs from the norm, and it is in fact
* desired for the HLOS to manage these clocks
*/
protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
<SSC_XO>,
<SSC_CNOC_AHBS_CLK>;
};
rpm_msg_ram: sram@778000 {

31
arch/arm64/boot/dts/qcom/pm8350.dtsi
View File

@ -6,6 +6,30 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pm8350_thermal: pm8350c-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm8350_temp_alarm>;
trips {
pm8350_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pm8350_crit: pm8350c-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pm8350: pmic@1 {
compatible = "qcom,pm8350", "qcom,spmi-pmic";
@ -13,6 +37,13 @@ pm8350: pmic@1 {
#address-cells = <1>;
#size-cells = <0>;
pm8350_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8350_gpios: gpio@8800 {
compatible = "qcom,pm8350-gpio";
reg = <0x8800>;

31
arch/arm64/boot/dts/qcom/pm8350b.dtsi
View File

@ -6,6 +6,30 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pm8350b_thermal: pm8350c-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm8350b_temp_alarm>;
trips {
pm8350b_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pm8350b_crit: pm8350c-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pm8350b: pmic@3 {
compatible = "qcom,pm8350b", "qcom,spmi-pmic";
@ -13,6 +37,13 @@ pm8350b: pmic@3 {
#address-cells = <1>;
#size-cells = <0>;
pm8350b_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8350b_gpios: gpio@8800 {
compatible = "qcom,pm8350b-gpio";
reg = <0x8800>;

39
arch/arm64/boot/dts/qcom/pm8350c.dtsi
View File

@ -29,26 +29,35 @@ pm8350c_gpios: gpio@8800 {
interrupt-controller;
#interrupt-cells = <2>;
};
pm8350c_pwm: pwm@e800 {
compatible = "qcom,pm8350c-pwm";
reg = <0xe800>;
#pwm-cells = <2>;
status = "disabled";
};
};
};
&thermal_zones {
pm8350c_thermal: pm8350c-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm8350c_temp_alarm>;
/ {
thermal-zones {
pm8350c_thermal: pm8350c-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm8350c_temp_alarm>;
trips {
pm8350c_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trips {
pm8350c_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pm8350c_crit: pm8350c-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
pm8350c_crit: pm8350c-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
};

59
arch/arm64/boot/dts/qcom/pm8450.dtsi Normal file
View File

@ -0,0 +1,59 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022, Linaro Limited
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pm8450-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm8450_temp_alarm>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "hot";
};
};
};
};
};
&spmi_bus {
pm8450: pmic@7 {
compatible = "qcom,pm8450", "qcom,spmi-pmic";
reg = <0x7 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8450_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8450_gpios: gpio@8800 {
compatible = "qcom,pm8450-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pm8450_gpios 0 0 4>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

32
arch/arm64/boot/dts/qcom/pmr735a.dtsi
View File

@ -32,23 +32,25 @@ pmr735a_gpios: gpio@8800 {
};
};
&thermal_zones {
pmr735a_thermal: pmr735a-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmr735a_temp_alarm>;
/ {
thermal-zones {
pmr735a_thermal: pmr735a-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmr735a_temp_alarm>;
trips {
pmr735a_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trips {
pmr735a_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pmr735a_crit: pmr735a-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
pmr735a_crit: pmr735a-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
};

31
arch/arm64/boot/dts/qcom/pmr735b.dtsi
View File

@ -6,6 +6,30 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pmr735a_thermal: pmr735a-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmr735b_temp_alarm>;
trips {
pmr735b_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pmr735b_crit: pmr735a-crit {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pmr735b: pmic@5 {
compatible = "qcom,pmr735b", "qcom,spmi-pmic";
@ -13,6 +37,13 @@ pmr735b: pmic@5 {
#address-cells = <1>;
#size-cells = <0>;
pmr735b_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmr735b_gpios: gpio@8800 {
compatible = "qcom,pmr735b-gpio";
reg = <0x8800>;

94
arch/arm64/boot/dts/qcom/qcs404.dtsi
View File

@ -226,7 +226,7 @@ rpm_requests: glink-channel {
qcom,glink-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-qcs404";
compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc";
#clock-cells = <1>;
};
@ -823,8 +823,8 @@ blsp1_uart0: serial@78af000 {
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 1>, <&blsp1_dma 0>;
dma-names = "rx", "tx";
dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_uart0_default>;
status = "disabled";
@ -836,8 +836,8 @@ blsp1_uart1: serial@78b0000 {
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 3>, <&blsp1_dma 2>;
dma-names = "rx", "tx";
dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_uart1_default>;
status = "disabled";
@ -849,8 +849,8 @@ blsp1_uart2: serial@78b1000 {
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 5>, <&blsp1_dma 4>;
dma-names = "rx", "tx";
dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_uart2_default>;
status = "okay";
@ -903,8 +903,8 @@ blsp1_uart3: serial@78b2000 {
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 7>, <&blsp1_dma 6>;
dma-names = "rx", "tx";
dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_uart3_default>;
status = "disabled";
@ -914,9 +914,9 @@ blsp1_i2c0: i2c@78b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c0_default>;
#address-cells = <1>;
@ -928,9 +928,9 @@ blsp1_spi0: spi@78b5000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_spi0_default>;
#address-cells = <1>;
@ -942,9 +942,9 @@ blsp1_i2c1: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c1_default>;
#address-cells = <1>;
@ -956,9 +956,9 @@ blsp1_spi1: spi@78b6000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_spi1_default>;
#address-cells = <1>;
@ -970,9 +970,9 @@ blsp1_i2c2: i2c@78b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c2_default>;
#address-cells = <1>;
@ -984,9 +984,9 @@ blsp1_spi2: spi@78b7000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_spi2_default>;
#address-cells = <1>;
@ -998,9 +998,9 @@ blsp1_i2c3: i2c@78b8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b8000 0x600>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c3_default>;
#address-cells = <1>;
@ -1012,9 +1012,9 @@ blsp1_spi3: spi@78b8000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b8000 0x600>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_spi3_default>;
#address-cells = <1>;
@ -1026,9 +1026,9 @@ blsp1_i2c4: i2c@78b9000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b9000 0x600>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c4_default>;
#address-cells = <1>;
@ -1040,9 +1040,9 @@ blsp1_spi4: spi@78b9000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b9000 0x600>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_spi4_default>;
#address-cells = <1>;
@ -1067,8 +1067,8 @@ blsp2_uart0: serial@7aef000 {
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp2_dma 1>, <&blsp2_dma 0>;
dma-names = "rx", "tx";
dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&blsp2_uart0_default>;
status = "disabled";
@ -1078,9 +1078,9 @@ blsp2_i2c0: i2c@7af5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07af5000 0x600>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp2_i2c0_default>;
#address-cells = <1>;
@ -1092,9 +1092,9 @@ blsp2_spi0: spi@7af5000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07af5000 0x600>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>;
clock-names = "iface", "core";
clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp2_spi0_default>;
#address-cells = <1>;

2
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
View File

@ -29,7 +29,7 @@ chosen {
};
/* Fixed crystal oscillator dedicated to MCP2518FD */
clk40M: can_clock {
clk40M: can-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;

193
arch/arm64/boot/dts/qcom/sa8155p-adp.dts
View File

@ -47,6 +47,29 @@ vreg_s4a_1p8: smps4 {
vin-supply = <&vreg_3p3>;
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <1>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
snps,route-up;
snps,priority = <0x1>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
snps,tx-sched-wrr;
queue0 {
snps,weight = <0x10>;
snps,dcb-algorithm;
snps,priority = <0x0>;
};
};
};
&apps_rsc {
@ -303,6 +326,44 @@ vreg_l18c_0p88: ldo18 {
};
};
&ethernet {
status = "okay";
snps,reset-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 11000 70000>;
snps,ptp-ref-clk-rate = <250000000>;
snps,ptp-req-clk-rate = <96000000>;
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
pinctrl-names = "default";
pinctrl-0 = <&ethernet_defaults>;
phy-handle = <&rgmii_phy>;
phy-mode = "rgmii";
max-speed = <1000>;
mdio {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,dwmac-mdio";
/* Micrel KSZ9031RNZ PHY */
rgmii_phy: phy@7 {
reg = <0x7>;
interrupt-parent = <&tlmm>;
interrupts-extended = <&tlmm 124 IRQ_TYPE_EDGE_FALLING>; /* phy intr */
device_type = "ethernet-phy";
compatible = "ethernet-phy-ieee802.3-c22";
};
};
};
&qupv3_id_1 {
status = "okay";
};
@ -317,6 +378,20 @@ &remoteproc_cdsp {
firmware-name = "qcom/sa8155p/cdsp.mdt";
};
&sdhc_2 {
status = "okay";
cd-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
vqmmc-supply = <&vreg_l13c_2p96>; /* IO line power */
vmmc-supply = <&vreg_l17a_2p96>; /* Card power line */
bus-width = <4>;
no-sdio;
no-emmc;
};
&uart2 {
status = "okay";
};
@ -387,9 +462,78 @@ &usb_2_qmpphy {
vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
};
&pcie0 {
status = "okay";
};
&pcie0_phy {
status = "okay";
vdda-phy-supply = <&vreg_l18c_0p88>;
vdda-pll-supply = <&vreg_l8c_1p2>;
};
&pcie1_phy {
vdda-phy-supply = <&vreg_l18c_0p88>;
vdda-pll-supply = <&vreg_l8c_1p2>;
};
&tlmm {
gpio-reserved-ranges = <0 4>;
sdc2_on: sdc2_on {
clk {
pins = "sdc2_clk";
bias-disable; /* No pull */
drive-strength = <16>; /* 16 MA */
};
cmd {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
data {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
sd-cd {
pins = "gpio96";
function = "gpio";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
};
sdc2_off: sdc2_off {
clk {
pins = "sdc2_clk";
bias-disable; /* No pull */
drive-strength = <2>; /* 2 MA */
};
cmd {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
data {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
sd-cd {
pins = "gpio96";
function = "gpio";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
};
usb2phy_ac_en1_default: usb2phy_ac_en1_default {
mux {
pins = "gpio113";
@ -407,4 +551,53 @@ mux {
drive-strength = <2>;
};
};
ethernet_defaults: ethernet-defaults {
mdc {
pins = "gpio7";
function = "rgmii";
bias-pull-up;
};
mdio {
pins = "gpio59";
function = "rgmii";
bias-pull-up;
};
rgmii-rx {
pins = "gpio117", "gpio118", "gpio119", "gpio120", "gpio115", "gpio116";
function = "rgmii";
bias-disable;
drive-strength = <2>;
};
rgmii-tx {
pins = "gpio122", "gpio4", "gpio5", "gpio6", "gpio114", "gpio121";
function = "rgmii";
bias-pull-up;
drive-strength = <16>;
};
phy-intr {
pins = "gpio124";
function = "emac_phy";
bias-disable;
drive-strength = <8>;
};
pps {
pins = "gpio81";
function = "emac_pps";
bias-disable;
drive-strength = <8>;
};
phy-reset {
pins = "gpio79";
function = "gpio";
bias-pull-up;
drive-strength = <16>;
};
};
};

11
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
View File

@ -5,15 +5,10 @@
* Copyright 2020 Google LLC.
*/
#include "sc7180.dtsi"
ap_ec_spi: &spi6 {};
ap_h1_spi: &spi0 {};
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
/* Deleted nodes from trogdor.dtsi */
/* Deleted nodes from sc7180-trogdor.dtsi */
/delete-node/ &alc5682;
/delete-node/ &pp3300_codec;
@ -111,10 +106,6 @@ ap_ts: touchscreen@5d {
};
};
&i2c7 {
status = "disabled";
};
&i2c9 {
status = "disabled";
};

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts
View File

@ -7,7 +7,7 @@
/dts-v1/;
#include "sc7180.dtsi"
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
#include "sc7180-trogdor-homestar.dtsi"

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts
View File

@ -7,7 +7,7 @@
/dts-v1/;
#include "sc7180.dtsi"
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
#include "sc7180-trogdor-homestar.dtsi"

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts
View File

@ -7,7 +7,7 @@
/dts-v1/;
#include "sc7180.dtsi"
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-parade-ps8640.dtsi"
#include "sc7180-trogdor-homestar.dtsi"

7
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
View File

@ -5,9 +5,6 @@
* Copyright 2021 Google LLC.
*/
ap_ec_spi: &spi6 {};
ap_h1_spi: &spi0 {};
#include "sc7180-trogdor.dtsi"
/ {
@ -88,10 +85,6 @@ map1 {
};
};
&ap_tp_i2c {
status = "disabled";
};
ap_ts_pen_1v8: &i2c4 {
status = "okay";
clock-frequency = <400000>;

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts
View File

@ -7,7 +7,7 @@
/dts-v1/;
#include "sc7180.dtsi"
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
#include "sc7180-trogdor-lazor.dtsi"
#include "sc7180-trogdor-lte-sku.dtsi"

4
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts
View File

@ -7,7 +7,7 @@
/dts-v1/;
#include "sc7180.dtsi"
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-parade-ps8640.dtsi"
#include "sc7180-trogdor-lazor.dtsi"
#include "sc7180-trogdor-lte-sku.dtsi"
@ -20,7 +20,7 @@ / {
/delete-node/&ap_ts;
&panel {
compatible = "innolux,n116bca-ea1", "innolux,n116bge";
compatible = "edp-panel";
};
&sdhc_2 {

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts
View File

@ -7,7 +7,7 @@
/dts-v1/;
#include "sc7180.dtsi"
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
#include "sc7180-trogdor-lazor.dtsi"
#include "sc7180-trogdor-lte-sku.dtsi"

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r9.dts
View File

@ -7,7 +7,7 @@
/dts-v1/;
#include "sc7180.dtsi"
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-parade-ps8640.dtsi"
#include "sc7180-trogdor-lazor.dtsi"
#include "sc7180-trogdor-lte-sku.dtsi"

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts
View File

@ -7,7 +7,7 @@
/dts-v1/;
#include "sc7180.dtsi"
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
#include "sc7180-trogdor-lazor.dtsi"

4
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts
View File

@ -13,10 +13,6 @@ / {
compatible = "google,lazor-rev1-sku0", "google,lazor-rev2-sku0", "qcom,sc7180";
};
&ap_sar_sensor {
status = "okay";
};
&ap_sar_sensor_i2c {
status = "okay";
};

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts
View File

@ -7,7 +7,7 @@
/dts-v1/;
#include "sc7180.dtsi"
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
#include "sc7180-trogdor-lazor.dtsi"

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts
View File

@ -7,7 +7,7 @@
/dts-v1/;
#include "sc7180.dtsi"
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
#include "sc7180-trogdor-lazor.dtsi"
#include "sc7180-lite.dtsi"

6
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts
View File

@ -7,7 +7,7 @@
/dts-v1/;
#include "sc7180.dtsi"
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
#include "sc7180-trogdor-lazor.dtsi"
#include "sc7180-trogdor-lte-sku.dtsi"
@ -20,10 +20,6 @@ / {
"qcom,sc7180";
};
&ap_sar_sensor {
status = "okay";
};
&ap_sar_sensor_i2c {
status = "okay";
};

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts
View File

@ -7,7 +7,7 @@
/dts-v1/;
#include "sc7180.dtsi"
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
#include "sc7180-trogdor-lazor.dtsi"
#include "sc7180-lite.dtsi"

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts
View File

@ -7,7 +7,7 @@
/dts-v1/;
#include "sc7180.dtsi"
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-parade-ps8640.dtsi"
#include "sc7180-trogdor-lazor.dtsi"
#include "sc7180-lite.dtsi"

6
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts
View File

@ -7,7 +7,7 @@
/dts-v1/;
#include "sc7180.dtsi"
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-parade-ps8640.dtsi"
#include "sc7180-trogdor-lazor.dtsi"
#include "sc7180-trogdor-lte-sku.dtsi"
@ -17,10 +17,6 @@ / {
compatible = "google,lazor-sku0", "qcom,sc7180";
};
&ap_sar_sensor {
status = "okay";
};
&ap_sar_sensor_i2c {
status = "okay";
};

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts
View File

@ -7,7 +7,7 @@
/dts-v1/;
#include "sc7180.dtsi"
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-parade-ps8640.dtsi"
#include "sc7180-trogdor-lazor.dtsi"
#include "sc7180-lite.dtsi"

7
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
View File

@ -5,9 +5,6 @@
* Copyright 2020 Google LLC.
*/
ap_ec_spi: &spi6 {};
ap_h1_spi: &spi0 {};
#include "sc7180-trogdor.dtsi"
&ap_sar_sensor {
@ -19,6 +16,10 @@ &ap_sar_sensor {
semtech,avg-pos-strength = <64>;
};
&ap_tp_i2c {
status = "okay";
};
/*
* Lazor is stuffed with a 47k NTC as charger thermistor which currently is
* not supported by the PM6150 ADC driver. Disable the charger thermal zone

9
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi
View File

@ -5,11 +5,6 @@
* Copyright 2020 Google LLC.
*/
#include "sc7180.dtsi"
ap_ec_spi: &spi6 {};
ap_h1_spi: &spi0 {};
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
@ -36,6 +31,10 @@ &alc5682 {
realtek,dmic-clk-driving-high = "true";
};
&ap_tp_i2c {
status = "okay";
};
&cpu6_alert0 {
temperature = <60000>;
};

9
arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts
View File

@ -7,11 +7,6 @@
/dts-v1/;
#include "sc7180.dtsi"
ap_ec_spi: &spi6 {};
ap_h1_spi: &spi0 {};
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
@ -20,6 +15,10 @@ / {
compatible = "google,trogdor", "qcom,sc7180";
};
&ap_tp_i2c {
status = "okay";
};
ap_ts_pen_1v8: &i2c4 {
status = "okay";
clock-frequency = <400000>;

9
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
View File

@ -11,7 +11,8 @@
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/sound/sc7180-lpass.h>
/* PMICs depend on spmi_bus label and so must come after SoC */
#include "sc7180.dtsi"
/* PMICs depend on spmi_bus label and so must come after sc7180.dtsi */
#include "pm6150.dtsi"
#include "pm6150l.dtsi"
@ -626,7 +627,7 @@ src_vreg_bob: bob {
};
};
&ap_ec_spi {
ap_ec_spi: &spi6 {
status = "okay";
cros_ec: ec@0 {
compatible = "google,cros-ec-spi";
@ -675,7 +676,7 @@ usb_c1: connector@1 {
};
};
&ap_h1_spi {
ap_h1_spi: &spi0 {
status = "okay";
cr50: tpm@0 {
compatible = "google,cr50";
@ -722,13 +723,11 @@ ap_sar_sensor: proximity@28 {
vdd-supply = <&pp3300_a>;
svdd-supply = <&pp1800_prox>;
status = "disabled";
label = "proximity-wifi";
};
};
ap_tp_i2c: &i2c7 {
status = "okay";
clock-frequency = <400000>;
trackpad: trackpad@15 {

9
arch/arm64/boot/dts/qcom/sc7180.dtsi
View File

@ -1421,13 +1421,6 @@ mmss_noc: interconnect@1740000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
ipa_virt: interconnect@1e00000 {
compatible = "qcom,sc7180-ipa-virt";
reg = <0 0x01e00000 0 0x1000>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
ipa: ipa@1e40000 {
compatible = "qcom,sc7180-ipa";
@ -3522,7 +3515,7 @@ rpmhpd_opp_turbo_l1: opp11 {
};
};
apps_bcm_voter: bcm_voter {
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
};
};

7
arch/arm64/boot/dts/qcom/sc7280-crd.dts → arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
View File

@ -11,8 +11,11 @@
#include "sc7280-idp-ec-h1.dtsi"
/ {
model = "Qualcomm Technologies, Inc. sc7280 CRD platform";
compatible = "qcom,sc7280-crd", "google,hoglin", "qcom,sc7280";
model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4)";
compatible = "qcom,sc7280-crd",
"google,hoglin-rev3", "google,hoglin-rev4",
"google,piglin-rev3", "google,piglin-rev4",
"qcom,sc7280";
aliases {
serial0 = &uart5;

365
arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts Normal file
View File

@ -0,0 +1,365 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* sc7280 CRD 3+ board device tree source
*
* Copyright 2022 Google LLC.
*/
/dts-v1/;
#include "sc7280-herobrine.dtsi"
/ {
model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)";
compatible = "google,hoglin", "qcom,sc7280";
/* FIXED REGULATORS */
/*
* On most herobrine boards PPVAR_SYS directly provides VREG_EDP_BL.
* However, on CRD there's an extra regulator in the way. Since this
* is expected to be uncommon, we'll leave the "vreg_edp_bl" label
* in the baseboard herobrine.dtsi point at "ppvar_sys" and then
* make a "_crd" specific version here.
*/
vreg_edp_bl_crd: vreg-edp-bl-crd-regulator {
compatible = "regulator-fixed";
regulator-name = "vreg_edp_bl_crd";
gpio = <&pm8350c_gpios 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&edp_bl_reg_en>;
vin-supply = <&ppvar_sys>;
};
};
/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
&apps_rsc {
pmg1110-regulators {
compatible = "qcom,pmg1110-rpmh-regulators";
qcom,pmic-id = "k";
vreg_s1k_1p0: smps1 {
regulator-min-microvolt = <1010000>;
regulator-max-microvolt = <1170000>;
};
};
};
ap_tp_i2c: &i2c0 {
status = "okay";
clock-frequency = <400000>;
trackpad: trackpad@15 {
compatible = "hid-over-i2c";
reg = <0x15>;
pinctrl-names = "default";
pinctrl-0 = <&tp_int_odl>;
interrupt-parent = <&tlmm>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
post-power-on-delay-ms = <20>;
hid-descr-addr = <0x0001>;
vdd-supply = <&pp3300_z1>;
wakeup-source;
};
};
&ap_sar_sensor_i2c {
status = "okay";
};
&ap_sar_sensor0 {
status = "okay";
};
&ap_sar_sensor1 {
status = "okay";
};
ap_ts_pen_1v8: &i2c13 {
status = "okay";
clock-frequency = <400000>;
ap_ts: touchscreen@5c {
compatible = "hid-over-i2c";
reg = <0x5c>;
pinctrl-names = "default";
pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>;
interrupt-parent = <&tlmm>;
interrupts = <55 IRQ_TYPE_LEVEL_LOW>;
post-power-on-delay-ms = <500>;
hid-descr-addr = <0x0000>;
vdd-supply = <&pp3300_left_in_mlb>;
};
};
&mdss_edp {
status = "okay";
};
&mdss_edp_phy {
status = "okay";
};
/* For nvme */
&pcie1 {
status = "okay";
};
/* For nvme */
&pcie1_phy {
status = "okay";
};
&pm8350c_pwm_backlight {
power-supply = <&vreg_edp_bl_crd>;
};
/* For eMMC */
&sdhc_1 {
status = "okay";
};
/* For SD Card */
&sdhc_2 {
status = "okay";
};
/* PINCTRL - BOARD-SPECIFIC */
/*
* Methodology for gpio-line-names:
* - If a pin goes to CRD board and is named it gets that name.
* - If a pin goes to CRD board and is not named, it gets no name.
* - If a pin is totally internal to Qcard then it gets Qcard name.
* - If a pin is not hooked up on Qcard, it gets no name.
*/
&pm8350c_gpios {
gpio-line-names = "FLASH_STROBE_1", /* 1 */
"AP_SUSPEND",
"PM8008_1_RST_N",
"",
"",
"EDP_BL_REG_EN",
"PMIC_EDP_BL_EN",
"PMIC_EDP_BL_PWM",
"";
edp_bl_reg_en: edp-bl-reg-en {
pins = "gpio6";
function = "normal";
bias-disable;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
};
};
&tlmm {
gpio-line-names = "AP_TP_I2C_SDA", /* 0 */
"AP_TP_I2C_SCL",
"PCIE1_RESET_N",
"PCIE1_WAKE_N",
"APPS_I2C_SDA",
"APPS_I2C_SCL",
"",
"TPAD_INT_N",
"",
"",
"GNSS_L1_EN", /* 10 */
"GNSS_L5_EN",
"QSPI_DATA_0",
"QSPI_DATA_1",
"QSPI_CLK",
"QSPI_CS_N_1",
/*
* AP_FLASH_WP is crossystem ABI. Schematics call it
* BIOS_FLASH_WP_L (the '_L' suffix is misleading, the
* signal is active high).
*/
"AP_FLASH_WP",
"",
"AP_EC_INT_N",
"",
"CAM0_RST_N", /* 20 */
"CAM1_RST_N",
"SM_DBG_UART_TX",
"SM_DBG_UART_RX",
"",
"PM8008_IRQ_1",
"HOST2WLAN_SOL",
"WLAN2HOST_SOL",
"MOS_BT_UART_CTS",
"MOS_BT_UART_RFR",
"MOS_BT_UART_TX", /* 30 */
"MOS_BT_UART_RX",
"",
"HUB_RST",
"",
"",
"",
"",
"",
"",
"EC_SPI_MISO_GPIO40", /* 40 */
"EC_SPI_MOSI_GPIO41",
"EC_SPI_CLK_GPIO42",
"EC_SPI_CS_GPIO43",
"",
"EARLY_EUD_EN",
"",
"DP_HOT_PLUG_DETECT",
"AP_BRD_ID_0",
"AP_BRD_ID_1",
"AP_BRD_ID_2", /* 50 */
"NVME_PWR_REG_EN",
"TS_I2C_SDA_CONN",
"TS_I2C_CLK_CONN",
"TS_RST_CONN",
"TS_INT_CONN",
"AP_I2C_TPM_SDA",
"AP_I2C_TPM_SCL",
"",
"",
"EDP_HOT_PLUG_DET_N", /* 60 */
"",
"",
"AMP_EN",
"CAM0_MCLK_GPIO_64",
"CAM1_MCLK_GPIO_65",
"",
"",
"",
"CCI_I2C_SDA0",
"CCI_I2C_SCL0", /* 70 */
"",
"",
"",
"",
"",
"",
"",
"",
"PCIE1_CLK_REQ_N",
"EN_PP3300_DX_EDP", /* 80 */
"US_EURO_HS_SEL",
"FORCED_USB_BOOT",
"WCD_RESET_N",
"MOS_WLAN_EN",
"MOS_BT_EN",
"MOS_SW_CTRL",
"MOS_PCIE0_RST",
"MOS_PCIE0_CLKREQ_N",
"MOS_PCIE0_WAKE_N",
"MOS_LAA_AS_EN", /* 90 */
"SD_CARD_DET_CONN",
"",
"",
"MOS_BT_WLAN_SLIMBUS_CLK",
"MOS_BT_WLAN_SLIMBUS_DAT0",
"",
"",
"",
"",
"", /* 100 */
"",
"",
"",
"H1_AP_INT_N",
"",
"AMP_BCLK",
"AMP_DIN",
"AMP_LRCLK",
"UIM1_DATA_GPIO_109",
"UIM1_CLK_GPIO_110", /* 110 */
"UIM1_RESET_GPIO_111",
"",
"UIM1_DATA",
"UIM1_CLK",
"UIM1_RESET",
"UIM1_PRESENT",
"SDM_RFFE0_CLK",
"SDM_RFFE0_DATA",
"",
"SDM_RFFE1_DATA", /* 120 */
"SC_GPIO_121",
"FASTBOOT_SEL_1",
"SC_GPIO_123",
"FASTBOOT_SEL_2",
"SM_RFFE4_CLK_GRFC_8",
"SM_RFFE4_DATA_GRFC_9",
"WLAN_COEX_UART1_RX",
"WLAN_COEX_UART1_TX",
"",
"", /* 130 */
"",
"",
"SDR_QLINK_REQ",
"SDR_QLINK_EN",
"QLINK0_WMSS_RESET_N",
"SMR526_QLINK1_REQ",
"SMR526_QLINK1_EN",
"SMR526_QLINK1_WMSS_RESET_N",
"",
"SAR1_INT_N", /* 140 */
"SAR0_INT_N",
"",
"",
"WCD_SWR_TX_CLK",
"WCD_SWR_TX_DATA0",
"WCD_SWR_TX_DATA1",
"WCD_SWR_RX_CLK",
"WCD_SWR_RX_DATA0",
"WCD_SWR_RX_DATA1",
"DMIC01_CLK", /* 150 */
"DMIC01_DATA",
"DMIC23_CLK",
"DMIC23_DATA",
"",
"",
"EC_IN_RW_N",
"EN_PP3300_HUB",
"WCD_SWR_TX_DATA2",
"",
"", /* 160 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 170 */
"MOS_BLE_UART_TX",
"MOS_BLE_UART_RX",
"",
"",
"";
};

1352
arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts
View File

File diff suppressed because it is too large Load Diff

38
arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts
View File

@ -14,6 +14,36 @@ / {
compatible = "google,herobrine", "qcom,sc7280";
};
/*
* ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES
*
* Sort order matches the order in the parent files (parents before children).
*/
&pp3300_codec {
status = "okay";
};
&pp3300_fp_mcu {
status = "okay";
};
&pp2850_vcm_wf_cam {
status = "okay";
};
&pp2850_wf_cam {
status = "okay";
};
&pp1800_wf_cam {
status = "okay";
};
&pp1200_wf_cam {
status = "okay";
};
/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
&ap_spi_fp {
@ -70,6 +100,14 @@ ap_ts: touchscreen@5c {
};
};
&mdss_edp {
status = "okay";
};
&mdss_edp_phy {
status = "okay";
};
/* For nvme */
&pcie1 {
status = "okay";

304
arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts Normal file
View File

@ -0,0 +1,304 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Villager board device tree source
*
* Copyright 2022 Google LLC.
*/
/dts-v1/;
#include "sc7280-herobrine.dtsi"
/ {
model = "Google Villager (rev0+)";
compatible = "google,villager", "qcom,sc7280";
};
/*
* ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES
*
* Sort order matches the order in the parent files (parents before children).
*/
&pp3300_codec {
status = "okay";
};
/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
ap_tp_i2c: &i2c0 {
status = "okay";
clock-frequency = <400000>;
trackpad: trackpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
pinctrl-names = "default";
pinctrl-0 = <&tp_int_odl>;
interrupt-parent = <&tlmm>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
hid-descr-addr = <0x20>;
vcc-supply = <&pp3300_z1>;
wakeup-source;
};
};
&ap_sar_sensor_i2c {
status = "okay";
};
&ap_sar_sensor0 {
status = "okay";
};
&ap_sar_sensor1 {
status = "okay";
};
&mdss_edp {
status = "okay";
};
&mdss_edp_phy {
status = "okay";
};
/* For nvme */
&pcie1 {
status = "okay";
};
/* For nvme */
&pcie1_phy {
status = "okay";
};
/* For eMMC */
&sdhc_1 {
status = "okay";
};
/* PINCTRL - BOARD-SPECIFIC */
/*
* Methodology for gpio-line-names:
* - If a pin goes to herobrine board and is named it gets that name.
* - If a pin goes to herobrine board and is not named, it gets no name.
* - If a pin is totally internal to Qcard then it gets Qcard name.
* - If a pin is not hooked up on Qcard, it gets no name.
*/
&pm8350c_gpios {
gpio-line-names = "FLASH_STROBE_1", /* 1 */
"AP_SUSPEND",
"PM8008_1_RST_N",
"",
"",
"",
"PMIC_EDP_BL_EN",
"PMIC_EDP_BL_PWM",
"";
};
&tlmm {
gpio-line-names = "AP_TP_I2C_SDA", /* 0 */
"AP_TP_I2C_SCL",
"SSD_RST_L",
"PE_WAKE_ODL",
"AP_SAR_SDA",
"AP_SAR_SCL",
"PRB_SC_GPIO_6",
"TP_INT_ODL",
"HP_I2C_SDA",
"HP_I2C_SCL",
"GNSS_L1_EN", /* 10 */
"GNSS_L5_EN",
"SPI_AP_MOSI",
"SPI_AP_MISO",
"SPI_AP_CLK",
"SPI_AP_CS0_L",
/*
* AP_FLASH_WP is crossystem ABI. Schematics
* call it BIOS_FLASH_WP_OD.
*/
"AP_FLASH_WP",
"",
"AP_EC_INT_L",
"",
"UF_CAM_RST_L", /* 20 */
"WF_CAM_RST_L",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"",
"PM8008_IRQ_1",
"HOST2WLAN_SOL",
"WLAN2HOST_SOL",
"MOS_BT_UART_CTS",
"MOS_BT_UART_RFR",
"MOS_BT_UART_TX", /* 30 */
"MOS_BT_UART_RX",
"PRB_SC_GPIO_32",
"HUB_RST_L",
"",
"",
"AP_SPI_FP_MISO",
"AP_SPI_FP_MOSI",
"AP_SPI_FP_CLK",
"AP_SPI_FP_CS_L",
"AP_EC_SPI_MISO", /* 40 */
"AP_EC_SPI_MOSI",
"AP_EC_SPI_CLK",
"AP_EC_SPI_CS_L",
"LCM_RST_L",
"EARLY_EUD_N",
"",
"DP_HOT_PLUG_DET",
"IO_BRD_MLB_ID0",
"IO_BRD_MLB_ID1",
"IO_BRD_MLB_ID2", /* 50 */
"SSD_EN",
"TS_I2C_SDA_CONN",
"TS_I2C_CLK_CONN",
"TS_RST_CONN",
"TS_INT_CONN",
"AP_I2C_TPM_SDA",
"AP_I2C_TPM_SCL",
"PRB_SC_GPIO_58",
"PRB_SC_GPIO_59",
"EDP_HOT_PLUG_DET_N", /* 60 */
"FP_TO_AP_IRQ_L",
"",
"AMP_EN",
"CAM0_MCLK_GPIO_64",
"CAM1_MCLK_GPIO_65",
"WF_CAM_MCLK",
"PRB_SC_GPIO_67",
"FPMCU_BOOT0",
"UF_CAM_SDA",
"UF_CAM_SCL", /* 70 */
"",
"",
"WF_CAM_SDA",
"WF_CAM_SCL",
"",
"",
"EN_FP_RAILS",
"FP_RST_L",
"PCIE1_CLKREQ_ODL",
"EN_PP3300_DX_EDP", /* 80 */
"SC_GPIO_81",
"FORCED_USB_BOOT",
"WCD_RESET_N",
"MOS_WLAN_EN",
"MOS_BT_EN",
"MOS_SW_CTRL",
"MOS_PCIE0_RST",
"MOS_PCIE0_CLKREQ_N",
"MOS_PCIE0_WAKE_N",
"MOS_LAA_AS_EN", /* 90 */
"SD_CD_ODL",
"",
"",
"MOS_BT_WLAN_SLIMBUS_CLK",
"MOS_BT_WLAN_SLIMBUS_DAT0",
"HP_MCLK",
"HP_BCLK",
"HP_DOUT",
"HP_DIN",
"HP_LRCLK", /* 100 */
"HP_IRQ",
"",
"",
"GSC_AP_INT_ODL",
"EN_PP3300_CODEC",
"AMP_BCLK",
"AMP_DIN",
"AMP_LRCLK",
"UIM1_DATA_GPIO_109",
"UIM1_CLK_GPIO_110", /* 110 */
"UIM1_RESET_GPIO_111",
"PRB_SC_GPIO_112",
"UIM0_DATA",
"UIM0_CLK",
"UIM0_RST",
"UIM0_PRESENT_ODL",
"SDM_RFFE0_CLK",
"SDM_RFFE0_DATA",
"WF_CAM_EN",
"FASTBOOT_SEL_0", /* 120 */
"SC_GPIO_121",
"FASTBOOT_SEL_1",
"SC_GPIO_123",
"FASTBOOT_SEL_2",
"SM_RFFE4_CLK_GRFC_8",
"SM_RFFE4_DATA_GRFC_9",
"WLAN_COEX_UART1_RX",
"WLAN_COEX_UART1_TX",
"PRB_SC_GPIO_129",
"LCM_ID0", /* 130 */
"LCM_ID1",
"",
"SDR_QLINK_REQ",
"SDR_QLINK_EN",
"QLINK0_WMSS_RESET_N",
"SMR526_QLINK1_REQ",
"SMR526_QLINK1_EN",
"SMR526_QLINK1_WMSS_RESET_N",
"PRB_SC_GPIO_139",
"SAR1_IRQ_ODL", /* 140 */
"SAR0_IRQ_ODL",
"PRB_SC_GPIO_142",
"",
"WCD_SWR_TX_CLK",
"WCD_SWR_TX_DATA0",
"WCD_SWR_TX_DATA1",
"WCD_SWR_RX_CLK",
"WCD_SWR_RX_DATA0",
"WCD_SWR_RX_DATA1",
"DMIC01_CLK", /* 150 */
"DMIC01_DATA",
"DMIC23_CLK",
"DMIC23_DATA",
"",
"",
"EC_IN_RW_ODL",
"HUB_EN",
"WCD_SWR_TX_DATA2",
"",
"", /* 160 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 170 */
"MOS_BLE_UART_TX",
"MOS_BLE_UART_RX",
"",
"",
"";
};

93
arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
View File

@ -92,6 +92,7 @@ pp3300_codec: pp3300-codec-regulator {
pinctrl-0 = <&en_pp3300_codec>;
vin-supply = <&pp3300_z1>;
status = "disabled";
};
pp3300_left_in_mlb: pp3300-left-in-mlb-regulator {
@ -132,6 +133,7 @@ pp3300_fp_mcu: pp3300-fp-regulator {
pinctrl-0 = <&en_fp_rails>;
vin-supply = <&pp3300_z1>;
status = "disabled";
};
pp3300_hub: pp3300-hub-regulator {
@ -178,6 +180,13 @@ pp3300_ssd: pp3300-ssd-regulator {
pinctrl-names = "default";
pinctrl-0 = <&ssd_en>;
/*
* The bootloaer may have left PCIe configured. Powering this
* off while the PCIe clocks are still running isn't great,
* so it's better to default to this regulator being on.
*/
regulator-boot-on;
vin-supply = <&pp3300_z1>;
};
@ -194,6 +203,7 @@ pp2850_vcm_wf_cam: pp2850-vcm-wf-cam-regulator {
pinctrl-0 = <&wf_cam_en>;
vin-supply = <&pp3300_z1>;
status = "disabled";
};
pp2850_wf_cam: pp2850-wf-cam-regulator {
@ -214,6 +224,7 @@ pp2850_wf_cam: pp2850-wf-cam-regulator {
*/
vin-supply = <&pp3300_z1>;
status = "disabled";
};
pp1800_fp: pp1800-fp-regulator {
@ -258,6 +269,7 @@ pp1800_wf_cam: pp1800-wf-cam-regulator {
*/
vin-supply = <&vreg_l19b_s0>;
status = "disabled";
};
pp1200_wf_cam: pp1200-wf-cam-regulator {
@ -278,6 +290,7 @@ pp1200_wf_cam: pp1200-wf-cam-regulator {
*/
vin-supply = <&pp3300_z1>;
status = "disabled";
};
/* BOARD-SPECIFIC TOP LEVEL NODES */
@ -295,7 +308,10 @@ keyboard_backlight: keyboard-backlight {
};
/*
* BOARD-LOCAL NAMES FOR REGULATORS THAT CONNECT TO QCARD
* ADJUSTMENTS TO QCARD REGULATORS
*
* Mostly this is just board-local names for regulators that come from
* Qcard, but this also has some minor regulator overrides.
*
* Names are only listed here if regulators go somewhere other than a
* testpoint.
@ -339,8 +355,60 @@ keyboard_backlight: keyboard-backlight {
ts_avdd: &pp3300_left_in_mlb {};
vreg_edp_3p3: &pp3300_left_in_mlb {};
/* Regulator overrides from Qcard */
/*
* Herobrine boards only use l2c to power an external audio codec (like
* alc5682) and we want that to be at 1.8V, not at some slightly lower voltage.
*/
&vreg_l2c_1p8 {
regulator-min-microvolt = <1800000>;
};
/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
&edp_panel {
/* Our board provides power to the qcard for the eDP panel. */
power-supply = <&vreg_edp_3p3>;
};
ap_sar_sensor_i2c: &i2c1 {
clock-frequency = <400000>;
status = "disabled";
ap_sar_sensor0: proximity@28 {
compatible = "semtech,sx9324";
reg = <0x28>;
#io-channel-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sar0_irq_odl>;
interrupt-parent = <&tlmm>;
interrupts = <141 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&pp1800_prox>;
label = "proximity-wifi-lte0";
status = "disabled";
};
ap_sar_sensor1: proximity@2c {
compatible = "semtech,sx9324";
reg = <0x2c>;
#io-channel-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sar1_irq_odl>;
interrupt-parent = <&tlmm>;
interrupts = <140 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&pp1800_prox>;
label = "proximity-wifi-lte1";
status = "disabled";
};
};
ap_i2c_tpm: &i2c14 {
status = "okay";
clock-frequency = <400000>;
@ -357,6 +425,14 @@ tpm@50 {
};
};
&mdss {
status = "okay";
};
&mdss_mdp {
status = "okay";
};
/* NVMe drive, enabled on a per-board basis */
&pcie1 {
pinctrl-names = "default";
@ -366,6 +442,17 @@ &pcie1 {
vddpe-3v3-supply = <&pp3300_ssd>;
};
&pm8350c_pwm {
status = "okay";
};
&pm8350c_pwm_backlight {
status = "okay";
/* Our board provides power to the qcard for the backlight */
power-supply = <&vreg_edp_bl>;
};
&pmk8350_rtc {
status = "disabled";
};
@ -677,7 +764,6 @@ fp_rst_l: fp-rst-l {
function = "gpio";
bias-disable;
drive-strength = <2>;
output-high;
};
fp_to_ap_irq_l: fp-to-ap-irq-l {
@ -691,7 +777,6 @@ fpmcu_boot0: fpmcu-boot0 {
pins = "gpio68";
function = "gpio";
bias-disable;
output-low;
};
gsc_ap_int_odl: gsc-ap-int-odl {
@ -741,7 +826,7 @@ sar0_irq_odl: sar0-irq-odl {
bias-pull-up;
};
sar1_irq_odl: sar0-irq-odl {
sar1_irq_odl: sar1-irq-odl {
pins = "gpio140";
function = "gpio";
bias-pull-up;

2
arch/arm64/boot/dts/qcom/sc7280-idp.dts
View File

@ -90,7 +90,7 @@ &usb_2 {
};
&usb_2_dwc3 {
dr_mode = "host";
dr_mode = "otg";
};
&usb_2_hsphy {

36
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
View File

@ -233,6 +233,14 @@ vreg_bob: bob {
};
};
&gpi_dma0 {
status = "okay";
};
&gpi_dma1 {
status = "okay";
};
&ipa {
status = "okay";
modem-init;
@ -400,10 +408,13 @@ &qup_uart5_rx {
&qup_uart7_cts {
/*
* Configure a pull-down on CTS to match the pull of
* the Bluetooth module.
* Configure a bias-bus-hold on CTS to lower power
* usage when Bluetooth is turned off. Bus hold will
* maintain a low power state regardless of whether
* the Bluetooth module drives the pin in either
* direction or leaves the pin fully unpowered.
*/
bias-pull-down;
bias-bus-hold;
};
&qup_uart7_rts {
@ -495,10 +506,13 @@ qup_uart7_sleep_cts: qup-uart7-sleep-cts {
pins = "gpio28";
function = "gpio";
/*
* Configure a pull-down on CTS to match the pull of
* the Bluetooth module.
* Configure a bias-bus-hold on CTS to lower power
* usage when Bluetooth is turned off. Bus hold will
* maintain a low power state regardless of whether
* the Bluetooth module drives the pin in either
* direction or leaves the pin fully unpowered.
*/
bias-pull-down;
bias-bus-hold;
};
qup_uart7_sleep_rts: qup-uart7-sleep-rts {
@ -547,3 +561,13 @@ sw_ctrl: sw-ctrl {
};
};
&remoteproc_wpss {
status = "okay";
};
&wifi {
status = "okay";
wifi-firmware {
iommus = <&apps_smmu 0x1c02 0x1>;
};
};

4
arch/arm64/boot/dts/qcom/sc7280-idp2.dts
View File

@ -34,3 +34,7 @@ &nvme_pwren {
&nvme_3v3_regulator {
gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>;
};
&pm8350c_pwm {
status = "okay";
};

73
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
View File

@ -29,6 +29,16 @@ aliases {
serial0 = &uart5;
serial1 = &uart7;
};
pm8350c_pwm_backlight: backlight {
compatible = "pwm-backlight";
status = "disabled";
enable-gpios = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_edp_bl_en>;
pwms = <&pm8350c_pwm 3 65535>;
};
};
&apps_rsc {
@ -293,11 +303,50 @@ &ipa {
modem-init;
};
/* NOTE: Not all Qcards have eDP connector stuffed */
&mdss_edp {
vdda-0p9-supply = <&vdd_a_edp_0_0p9>;
vdda-1p2-supply = <&vdd_a_edp_0_1p2>;
aux-bus {
edp_panel: panel {
compatible = "edp-panel";
backlight = <&pm8350c_pwm_backlight>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
edp_panel_in: endpoint {
remote-endpoint = <&mdss_edp_out>;
};
};
};
};
};
};
&mdss_edp_out {
remote-endpoint = <&edp_panel_in>;
};
&mdss_edp_phy {
vdda-pll-supply = <&vdd_a_edp_0_0p9>;
vdda-phy-supply = <&vdd_a_edp_0_1p2>;
};
&pcie1_phy {
vdda-phy-supply = <&vreg_l10c_0p88>;
vdda-pll-supply = <&vreg_l6b_1p2>;
};
&pm8350c_pwm {
pinctrl-names = "default";
pinctrl-0 = <&pmic_edp_bl_pwm>;
};
&pmk8350_vadc {
pmk8350-die-temp@3 {
reg = <PMK8350_ADC7_DIE_TEMP>;
@ -383,6 +432,11 @@ &usb_2_hsphy {
* baseboard or board device tree, not here.
*/
/* No external pull for eDP HPD, so set the internal one. */
&edp_hot_plug_det {
bias-pull-down;
};
/*
* For ts_i2c
*
@ -398,8 +452,14 @@ &qup_i2c13_data_clk {
/* For mos_bt_uart */
&qup_uart7_cts {
/* Configure a pull-down on CTS to match the pull of the Bluetooth module. */
bias-pull-down;
/*
* Configure a bias-bus-hold on CTS to lower power
* usage when Bluetooth is turned off. Bus hold will
* maintain a low power state regardless of whether
* the Bluetooth module drives the pin in either
* direction or leaves the pin fully unpowered.
*/
bias-bus-hold;
};
/* For mos_bt_uart */
@ -490,10 +550,13 @@ qup_uart7_sleep_cts: qup-uart7-sleep-cts {
pins = "gpio28";
function = "gpio";
/*
* Configure a pull-down on CTS to match the pull of
* the Bluetooth module.
* Configure a bias-bus-hold on CTS to lower power
* usage when Bluetooth is turned off. Bus hold will
* maintain a low power state regardless of whether
* the Bluetooth module drives the pin in either
* direction or leaves the pin fully unpowered.
*/
bias-pull-down;
bias-bus-hold;
};
/* For mos_bt_uart */

336
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@ -8,8 +8,11 @@
#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,gpucc-sc7280.h>
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sc7280.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
@ -85,6 +88,11 @@ reserved-memory {
#size-cells = <2>;
ranges;
wlan_ce_mem: memory@4cd000 {
no-map;
reg = <0x0 0x004cd000 0x0 0x1000>;
};
hyp_mem: memory@80000000 {
reg = <0x0 0x80000000 0x0 0x600000>;
no-map;
@ -842,6 +850,11 @@ qfprom: efuse@784000 {
power-domains = <&rpmhpd SC7280_MX>;
#address-cells = <1>;
#size-cells = <1>;
gpu_speed_bin: gpu_speed_bin@1e9 {
reg = <0x1e9 0x2>;
bits = <5 8>;
};
};
sdhc_1: sdhci@7c4000 {
@ -881,6 +894,8 @@ sdhc_1: sdhci@7c4000 {
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
resets = <&gcc GCC_SDCC1_BCR>;
sdhc1_opp_table: opp-table {
compatible = "operating-points-v2";
@ -901,6 +916,28 @@ opp-384000000 {
};
gpi_dma0: dma-controller@900000 {
#dma-cells = <3>;
compatible = "qcom,sc7280-gpi-dma";
reg = <0 0x00900000 0 0x60000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <12>;
dma-channel-mask = <0x7f>;
iommus = <&apps_smmu 0x0136 0x0>;
status = "disabled";
};
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x009c0000 0 0x2000>;
@ -928,6 +965,9 @@ i2c0: i2c@980000 {
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -946,6 +986,9 @@ spi0: spi@980000 {
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -980,6 +1023,9 @@ i2c1: i2c@984000 {
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -998,6 +1044,9 @@ spi1: spi@984000 {
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1032,6 +1081,9 @@ i2c2: i2c@988000 {
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1050,6 +1102,9 @@ spi2: spi@988000 {
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1084,6 +1139,9 @@ i2c3: i2c@98c000 {
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1102,6 +1160,9 @@ spi3: spi@98c000 {
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
<&gpi_dma0 1 3 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1136,6 +1197,9 @@ i2c4: i2c@990000 {
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1154,6 +1218,9 @@ spi4: spi@990000 {
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
<&gpi_dma0 1 4 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1188,6 +1255,9 @@ i2c5: i2c@994000 {
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1206,6 +1276,9 @@ spi5: spi@994000 {
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
<&gpi_dma0 1 5 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1240,6 +1313,9 @@ i2c6: i2c@998000 {
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
<&gpi_dma0 1 6 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1258,6 +1334,9 @@ spi6: spi@998000 {
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
<&gpi_dma0 1 6 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1292,6 +1371,9 @@ i2c7: i2c@99c000 {
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
<&gpi_dma0 1 7 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1310,6 +1392,9 @@ spi7: spi@99c000 {
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
<&gpi_dma0 1 7 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1330,6 +1415,28 @@ uart7: serial@99c000 {
};
};
gpi_dma1: dma-controller@a00000 {
#dma-cells = <3>;
compatible = "qcom,sc7280-gpi-dma";
reg = <0 0x00a00000 0 0x60000>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <12>;
dma-channel-mask = <0x1e>;
iommus = <&apps_smmu 0x56 0x0>;
status = "disabled";
};
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x00ac0000 0 0x2000>;
@ -1357,6 +1464,9 @@ i2c8: i2c@a80000 {
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1375,6 +1485,9 @@ spi8: spi@a80000 {
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1409,6 +1522,9 @@ i2c9: i2c@a84000 {
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1427,6 +1543,9 @@ spi9: spi@a84000 {
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
<&gpi_dma1 1 1 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1461,6 +1580,9 @@ i2c10: i2c@a88000 {
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1479,6 +1601,9 @@ spi10: spi@a88000 {
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1513,6 +1638,9 @@ i2c11: i2c@a8c000 {
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1531,6 +1659,9 @@ spi11: spi@a8c000 {
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1565,6 +1696,9 @@ i2c12: i2c@a90000 {
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1583,6 +1717,9 @@ spi12: spi@a90000 {
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
<&gpi_dma1 1 4 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1617,6 +1754,9 @@ i2c13: i2c@a94000 {
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
<&gpi_dma1 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1635,6 +1775,9 @@ spi13: spi@a94000 {
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
<&gpi_dma1 1 5 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1669,6 +1812,9 @@ i2c14: i2c@a98000 {
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
<&gpi_dma1 1 6 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1687,6 +1833,9 @@ spi14: spi@a98000 {
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
<&gpi_dma1 1 6 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1721,6 +1870,9 @@ i2c15: i2c@a9c000 {
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
<&gpi_dma1 1 7 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1739,6 +1891,9 @@ spi15: spi@a9c000 {
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
<&gpi_dma1 1 7 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -1808,6 +1963,47 @@ mmss_noc: interconnect@1740000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
wifi: wifi@17a10040 {
compatible = "qcom,wcn6750-wifi";
reg = <0 0x17a10040 0 0x0>;
iommus = <&apps_smmu 0x1c00 0x1>;
interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
qcom,rproc = <&remoteproc_wpss>;
memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
status = "disabled";
};
pcie1: pci@1c08000 {
compatible = "qcom,pcie-sc7280";
reg = <0 0x01c08000 0 0x3000>,
@ -1903,7 +2099,7 @@ pcie1_phy: phy@1c0e000 {
status = "disabled";
pcie1_lane: lanes@1c0e200 {
pcie1_lane: phy@1c0e200 {
reg = <0 0x01c0e200 0 0x170>,
<0 0x01c0e400 0 0x200>,
<0 0x01c0ea00 0 0x1f0>,
@ -1980,6 +2176,47 @@ lpasscc: lpasscc@3000000 {
#clock-cells = <1>;
};
lpass_audiocc: clock-controller@3300000 {
compatible = "qcom,sc7280-lpassaudiocc";
reg = <0 0x03300000 0 0x30000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
#clock-cells = <1>;
#power-domain-cells = <1>;
};
lpass_aon: clock-controller@3380000 {
compatible = "qcom,sc7280-lpassaoncc";
reg = <0 0x03380000 0 0x30000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&lpasscore LPASS_CORE_CC_CORE_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
#clock-cells = <1>;
#power-domain-cells = <1>;
};
lpasscore: clock-controller@3900000 {
compatible = "qcom,sc7280-lpasscorecc";
reg = <0 0x03900000 0 0x50000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "bi_tcxo";
power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
#clock-cells = <1>;
#power-domain-cells = <1>;
};
lpass_hm: clock-controller@3c00000 {
compatible = "qcom,sc7280-lpasshm";
reg = <0 0x3c00000 0 0x28>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "bi_tcxo";
#clock-cells = <1>;
#power-domain-cells = <1>;
};
lpass_ag_noc: interconnect@3c40000 {
reg = <0 0x03c40000 0 0xf080>;
compatible = "qcom,sc7280-lpass-ag-noc";
@ -2003,6 +2240,9 @@ gpu: gpu@3d00000 {
interconnect-names = "gfx-mem";
#cooling-cells = <2>;
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
@ -2010,18 +2250,56 @@ opp-315000000 {
opp-hz = /bits/ 64 <315000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-peak-kBps = <1804000>;
opp-supported-hw = <0x03>;
};
opp-450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <4068000>;
opp-supported-hw = <0x03>;
};
opp-550000000 {
opp-hz = /bits/ 64 <550000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <6832000>;
opp-supported-hw = <0x03>;
};
opp-608000000 {
opp-hz = /bits/ 64 <608000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
opp-peak-kBps = <8368000>;
opp-supported-hw = <0x02>;
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
opp-peak-kBps = <8532000>;
opp-supported-hw = <0x02>;
};
opp-812000000 {
opp-hz = /bits/ 64 <812000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
opp-peak-kBps = <8532000>;
opp-supported-hw = <0x02>;
};
opp-840000000 {
opp-hz = /bits/ 64 <840000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
opp-peak-kBps = <8532000>;
opp-supported-hw = <0x02>;
};
opp-900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
opp-peak-kBps = <8532000>;
opp-supported-hw = <0x02>;
};
};
};
@ -2686,6 +2964,8 @@ sdhc_2: sdhci@8804000 {
qcom,dll-config = <0x0007642c>;
resets = <&gcc GCC_SDCC2_BCR>;
sdhc2_opp_table: opp-table {
compatible = "operating-points-v2";
@ -2842,6 +3122,57 @@ qspi: spi@88dc000 {
status = "disabled";
};
remoteproc_wpss: remoteproc@8a00000 {
compatible = "qcom,sc7280-wpss-pil";
reg = <0 0x08a00000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
<&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
<&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";
clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
<&gcc GCC_WPSS_AHB_CLK>,
<&gcc GCC_WPSS_RSCP_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "ahb_bdg", "ahb",
"rscp", "xo";
power-domains = <&rpmhpd SC7280_CX>,
<&rpmhpd SC7280_MX>;
power-domain-names = "cx", "mx";
memory-region = <&wpss_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&wpss_smp2p_out 0>;
qcom,smem-state-names = "stop";
resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
<&pdc_reset PDC_WPSS_SYNC_RESET>;
reset-names = "restart", "pdc_sync";
qcom,halt-regs = <&tcsr_mutex 0x37000>;
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_WPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "wpss";
qcom,remote-pid = <13>;
};
};
dc_noc: interconnect@90e0000 {
reg = <0 0x090e0000 0 0x5080>;
compatible = "qcom,sc7280-dc-noc";
@ -2916,6 +3247,7 @@ usb_1_dwc3: usb@a600000 {
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
maximum-speed = "super-speed";
wakeup-source;
};
};
@ -3296,7 +3628,7 @@ edp_in: endpoint {
port@1 {
reg = <1>;
edp_out: endpoint { };
mdss_edp_out: endpoint { };
};
};

4
arch/arm64/boot/dts/qcom/sdm630.dtsi
View File

@ -1453,7 +1453,7 @@ mdp: mdp@c901000 {
reg-names = "mdp_phys";
interrupt-parent = <&mdss>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <0>;
assigned-clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_VSYNC_CLK>;
@ -1530,7 +1530,7 @@ dsi0: dsi@c994000 {
power-domains = <&rpmpd SDM660_VDDCX>;
interrupt-parent = <&mdss>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <4>;
assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
<&mmcc PCLK0_CLK_SRC>;

2
arch/arm64/boot/dts/qcom/sdm660.dtsi
View File

@ -163,7 +163,7 @@ dsi1: dsi@c996000 {
power-domains = <&rpmpd SDM660_VDDCX>;
interrupt-parent = <&mdss>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <5>;
assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
<&mmcc PCLK1_CLK_SRC>;

33
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
View File

@ -28,6 +28,13 @@ chosen {
stdout-path = "serial0:115200n8";
};
/* Fixed crystal oscillator dedicated to MCP2517FD */
clk40M: can-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
};
dc12v: dc12v-regulator {
compatible = "regulator-fixed";
regulator-name = "DC12V";
@ -746,6 +753,23 @@ codec {
};
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi0_default>;
cs-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
can@0 {
compatible = "microchip,mcp2517fd";
reg = <0>;
clocks = <&clk40M>;
interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
spi-max-frequency = <10000000>;
vdd-supply = <&vdc_5v>;
xceiver-supply = <&vdc_5v>;
};
};
&spi2 {
/* On Low speed expansion */
label = "LS-SPI0";
@ -1051,6 +1075,7 @@ &wifi {
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
qcom,snoc-host-cap-8bit-quirk;
qcom,ath10k-calibration-variant = "Thundercomm_DB845C";
};
/* PINCTRL - additions to nodes defined in sdm845.dtsi */
@ -1219,3 +1244,11 @@ ov7251_ep: endpoint {
};
};
};
/* PINCTRL - additions to nodes defined in sdm845.dtsi */
&qup_spi0_default {
config {
drive-strength = <6>;
bias-disable;
};
};

2
arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts
View File

@ -563,7 +563,7 @@ mux {
config {
pins = "gpio6", "gpio11";
drive-strength = <8>;
bias-disable = <0>;
bias-disable;
};
};

35
arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts
View File

@ -121,7 +121,7 @@ vreg_s4a_1p8: vreg-s4a-1p8 {
&adsp_pas {
status = "okay";
firmware-name = "qcom/sdm845/adsp.mdt";
firmware-name = "qcom/sdm845/beryllium/adsp.mbn";
};
&apps_rsc {
@ -185,6 +185,12 @@ vreg_l21a_2p95: ldo21 {
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l23a_3p3: ldo23 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l24a_3p075: ldo24 {
regulator-min-microvolt = <3088000>;
regulator-max-microvolt = <3088000>;
@ -208,7 +214,7 @@ vreg_l26a_1p2: ldo26 {
&cdsp_pas {
status = "okay";
firmware-name = "qcom/sdm845/cdsp.mdt";
firmware-name = "qcom/sdm845/beryllium/cdsp.mbn";
};
&dsi0 {
@ -218,13 +224,14 @@ &dsi0 {
panel@0 {
compatible = "tianma,fhd-video";
reg = <0>;
vddi0-supply = <&vreg_l14a_1p8>;
vddio-supply = <&vreg_l14a_1p8>;
vddpos-supply = <&lab>;
vddneg-supply = <&ibb>;
#address-cells = <1>;
#size-cells = <0>;
backlight = <&pmi8998_wled>;
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
port {
@ -262,7 +269,7 @@ &gpu {
zap-shader {
memory-region = <&gpu_mem>;
firmware-name = "qcom/sdm845/a630_zap.mbn";
firmware-name = "qcom/sdm845/beryllium/a630_zap.mbn";
};
};
@ -289,7 +296,13 @@ &mdss {
&mss_pil {
status = "okay";
firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mdt";
firmware-name = "qcom/sdm845/beryllium/mba.mbn", "qcom/sdm845/beryllium/modem.mbn";
};
&ipa {
status = "okay";
memory-region = <&ipa_fw_mem>;
firmware-name = "qcom/sdm845/beryllium/ipa_fws.mbn";
};
&pm8998_gpio {
@ -302,6 +315,17 @@ vol_up_pin_a: vol-up-active {
};
};
&pmi8998_wled {
status = "okay";
qcom,current-boost-limit = <970>;
qcom,ovp-millivolt = <29600>;
qcom,current-limit-microamp = <20000>;
qcom,num-strings = <2>;
qcom,switching-freq = <600>;
qcom,external-pfet;
qcom,cabc;
};
&pm8998_pon {
resin {
compatible = "qcom,pm8941-resin";
@ -541,6 +565,7 @@ &wifi {
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
vdd-3.3-ch1-supply = <&vreg_l23a_3p3>;
};
/* PINCTRL - additions to nodes defined in sdm845.dtsi */

34
arch/arm64/boot/dts/qcom/sdm845.dtsi
View File

@ -200,8 +200,8 @@ CPU0: cpu@0 {
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
capacity-dmips-mhz = <611>;
dynamic-power-coefficient = <290>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
@ -225,8 +225,8 @@ CPU1: cpu@100 {
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
capacity-dmips-mhz = <611>;
dynamic-power-coefficient = <290>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
@ -247,8 +247,8 @@ CPU2: cpu@200 {
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
capacity-dmips-mhz = <611>;
dynamic-power-coefficient = <290>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
@ -269,8 +269,8 @@ CPU3: cpu@300 {
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <607>;
dynamic-power-coefficient = <100>;
capacity-dmips-mhz = <611>;
dynamic-power-coefficient = <290>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
@ -292,7 +292,7 @@ CPU4: cpu@400 {
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
dynamic-power-coefficient = <442>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
@ -314,7 +314,7 @@ CPU5: cpu@500 {
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
dynamic-power-coefficient = <442>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
@ -336,7 +336,7 @@ CPU6: cpu@600 {
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
dynamic-power-coefficient = <442>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
@ -358,7 +358,7 @@ CPU7: cpu@700 {
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
dynamic-power-coefficient = <396>;
dynamic-power-coefficient = <442>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
@ -2027,7 +2027,7 @@ llcc: system-cache-controller@1100000 {
};
pcie0: pci@1c00000 {
compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
compatible = "qcom,pcie-sdm845";
reg = <0 0x01c00000 0 0x2000>,
<0 0x60000000 0 0xf1d>,
<0 0x60000f20 0 0xa8>,
@ -2132,7 +2132,7 @@ pcie0_lane: phy@1c06200 {
};
pcie1: pci@1c08000 {
compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
compatible = "qcom,pcie-sdm845";
reg = <0 0x01c08000 0 0x2000>,
<0 0x40000000 0 0xf1d>,
<0 0x40000f20 0 0xa8>,
@ -4283,7 +4283,7 @@ mdss_mdp: mdp@ae01000 {
power-domains = <&rpmhpd SDM845_CX>;
interrupt-parent = <&mdss>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <0>;
ports {
#address-cells = <1>;
@ -4335,7 +4335,7 @@ dsi0: dsi@ae94000 {
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <4>;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
@ -4407,7 +4407,7 @@ dsi1: dsi@ae96000 {
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <5>;
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,

241
arch/arm64/boot/dts/qcom/sm6350.dtsi
View File

@ -517,6 +517,45 @@ opp-384000000 {
};
};
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x8c0000 0x0 0x2000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
#address-cells = <2>;
#size-cells = <2>;
iommus = <&apps_smmu 0x43 0x0>;
ranges;
status = "disabled";
i2c0: i2c@880000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00880000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@888000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00888000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
qupv3_id_1: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x9c0000 0x0 0x2000>;
@ -529,16 +568,146 @@ qupv3_id_1: geniqup@9c0000 {
ranges;
status = "disabled";
uart2: serial@98c000 {
i2c6: i2c@980000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00980000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c6_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c7: i2c@984000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00984000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c7_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c8: i2c@988000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00988000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c8_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart9: serial@98c000 {
compatible = "qcom,geni-debug-uart";
reg = <0 0x98c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart2_default>;
pinctrl-0 = <&qup_uart9_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c10: i2c@990000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00990000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c10_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
ufs_mem_hc: ufs@1d84000 {
compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>,
<0 0x01d90000 0 0x8000>;
reg-names = "std", "ice";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
power-domains = <&gcc UFS_PHY_GDSC>;
iommus = <&apps_smmu 0x80 0x0>;
clock-names = "core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk",
"ice_core_clk";
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&rpmhcc RPMH_QLINK_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
freq-table-hz =
<50000000 200000000>,
<0 0>,
<0 0>,
<37500000 150000000>,
<75000000 300000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
status = "disabled";
};
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sm6350-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x18c>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clock-names = "ref",
"ref_aux";
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
status = "disabled";
ufs_mem_phy_lanes: phy@1d87400 {
reg = <0 0x01d87400 0 0x128>,
<0 0x01d87600 0 0x1fc>,
<0 0x01d87c00 0 0x1dc>,
<0 0x01d87800 0 0x128>,
<0 0x01d87a00 0 0x1fc>;
#phy-cells = <0>;
};
};
tcsr_mutex: hwlock@1f40000 {
@ -974,12 +1143,54 @@ tlmm: pinctrl@f100000 {
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 157>;
qup_uart2_default: qup-uart2-default {
qup_uart9_default: qup-uart9-default {
pins = "gpio25", "gpio26";
function = "qup13_f2";
drive-strength = <2>;
bias-disable;
};
qup_i2c0_default: qup-i2c0-default {
pins = "gpio0", "gpio1";
function = "qup00";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c2_default: qup-i2c2-default {
pins = "gpio45", "gpio46";
function = "qup02";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c6_default: qup-i2c6-default {
pins = "gpio13", "gpio14";
function = "qup10";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c7_default: qup-i2c7-default {
pins = "gpio27", "gpio28";
function = "qup11";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c8_default: qup-i2c8-default {
pins = "gpio19", "gpio20";
function = "qup12";
drive-strength = <2>;
bias-pull-up;
};
qup_i2c10_default: qup-i2c10-default {
pins = "gpio4", "gpio5";
function = "qup14";
drive-strength = <2>;
bias-pull-up;
};
};
apps_smmu: iommu@15000000 {
@ -1145,6 +1356,28 @@ frame@17c2d000 {
};
};
wifi: wifi@18800000 {
compatible = "qcom,wcn3990-wifi";
reg = <0 0x18800000 0 0x800000>;
reg-names = "membase";
memory-region = <&wlan_fw_mem>;
interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0x20 0x1>;
qcom,msa-fixed-perm;
status = "disabled";
};
apps_rsc: rsc@18200000 {
compatible = "qcom,rpmh-rsc";
label = "apps_rsc";
@ -1217,7 +1450,7 @@ rpmhpd_opp_turbo_l1: opp10 {
};
};
apps_bcm_voter: bcm_voter {
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
};
};

61
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
View File

@ -23,7 +23,7 @@ / {
qcom,board-id = <8 32>;
aliases {
serial0 = &uart2;
serial0 = &uart9;
};
chosen {
@ -296,6 +296,35 @@ &cdsp {
firmware-name = "qcom/sm7225/fairphone4/cdsp.mdt";
};
&i2c10 {
status = "okay";
clock-frequency = <400000>;
haptics@5a {
compatible = "awinic,aw8695";
reg = <0x5a>;
interrupts-extended = <&tlmm 85 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&tlmm 90 GPIO_ACTIVE_HIGH>;
awinic,f0-preset = <2350>;
awinic,f0-coefficient = <260>;
awinic,f0-calibration-percent = <7>;
awinic,drive-level = <125>;
awinic,f0-detection-play-time = <5>;
awinic,f0-detection-wait-time = <3>;
awinic,f0-detection-repeat = <2>;
awinic,f0-detection-trace = <15>;
awinic,boost-debug = /bits/ 8 <0x30 0xeb 0xd4>;
awinic,tset = /bits/ 8 <0x12>;
awinic,r-spare = /bits/ 8 <0x68>;
awinic,bemf-upper-threshold = <4104>;
awinic,bemf-lower-threshold = <1016>;
};
};
&mpss {
status = "okay";
firmware-name = "qcom/sm7225/fairphone4/modem.mdt";
@ -332,10 +361,28 @@ &tlmm {
gpio-reserved-ranges = <13 4>, <56 2>;
};
&uart2 {
&uart9 {
status = "okay";
};
&ufs_mem_hc {
status = "okay";
reset-gpios = <&tlmm 156 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l7e>;
vcc-max-microamp = <800000>;
vccq2-supply = <&vreg_l12a>;
vccq2-max-microamp = <800000>;
};
&ufs_mem_phy {
status = "okay";
vdda-phy-supply = <&vreg_l18a>;
vdda-pll-supply = <&vreg_l22a>;
};
&usb_1 {
status = "okay";
};
@ -359,3 +406,13 @@ &usb_1_qmpphy {
vdda-phy-supply = <&vreg_l22a>;
vdda-pll-supply = <&vreg_l16a>;
};
&wifi {
status = "okay";
vdd-0.8-cx-mx-supply = <&vreg_l4a>;
vdd-1.8-xo-supply = <&vreg_l7a>;
vdd-1.3-rfa-supply = <&vreg_l2e>;
vdd-3.3-ch0-supply = <&vreg_l10e>;
vdd-3.3-ch1-supply = <&vreg_l11e>;
};

330
arch/arm64/boot/dts/qcom/sm8150.dtsi
View File

@ -915,6 +915,33 @@ gpi_dma0: dma-controller@800000 {
status = "disabled";
};
ethernet: ethernet@20000 {
compatible = "qcom,sm8150-ethqos";
reg = <0x0 0x00020000 0x0 0x10000>,
<0x0 0x00036000 0x0 0x100>;
reg-names = "stmmaceth", "rgmii";
clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
clocks = <&gcc GCC_EMAC_AXI_CLK>,
<&gcc GCC_EMAC_SLV_AHB_CLK>,
<&gcc GCC_EMAC_PTP_CLK>,
<&gcc GCC_EMAC_RGMII_CLK>;
interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_lpi";
power-domains = <&gcc EMAC_GDSC>;
resets = <&gcc GCC_EMAC_BCR>;
iommus = <&apps_smmu 0x3C0 0x0>;
snps,tso;
rx-fifo-depth = <4096>;
tx-fifo-depth = <4096>;
status = "disabled";
};
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
@ -1746,6 +1773,203 @@ system-cache-controller@9200000 {
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
pcie0: pci@1c00000 {
compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
reg = <0 0x01c00000 0 0x3000>,
<0 0x60000000 0 0xf1d>,
<0 0x60000f20 0 0xa8>,
<0 0x60001000 0 0x1000>,
<0 0x60100000 0 0x100000>;
reg-names = "parf", "dbi", "elbi", "atu", "config";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"tbu";
iommus = <&apps_smmu 0x1d80 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
<0x100 &apps_smmu 0x1d81 0x1>;
resets = <&gcc GCC_PCIE_0_BCR>;
reset-names = "pci";
power-domains = <&gcc PCIE_0_GDSC>;
phys = <&pcie0_lane>;
phy-names = "pciephy";
perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
status = "disabled";
};
pcie0_phy: phy@1c06000 {
compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
reg = <0 0x01c06000 0 0x1c0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
clock-names = "aux", "cfg_ahb", "refgen";
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "phy";
assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
assigned-clock-rates = <100000000>;
status = "disabled";
pcie0_lane: phy@1c06200 {
reg = <0 0x1c06200 0 0x170>, /* tx */
<0 0x1c06400 0 0x200>, /* rx */
<0 0x1c06800 0 0x1f0>, /* pcs */
<0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
#phy-cells = <0>;
clock-output-names = "pcie_0_pipe_clk";
};
};
pcie1: pci@1c08000 {
compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
reg = <0 0x01c08000 0 0x3000>,
<0 0x40000000 0 0xf1d>,
<0 0x40000f20 0 0xa8>,
<0 0x40001000 0 0x1000>,
<0 0x40100000 0 0x100000>;
reg-names = "parf", "dbi", "elbi", "atu", "config";
device_type = "pci";
linux,pci-domain = <1>;
bus-range = <0x00 0xff>;
num-lanes = <2>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
<&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"tbu";
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommus = <&apps_smmu 0x1e00 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
<0x100 &apps_smmu 0x1e01 0x1>;
resets = <&gcc GCC_PCIE_1_BCR>;
reset-names = "pci";
power-domains = <&gcc PCIE_1_GDSC>;
phys = <&pcie1_lane>;
phy-names = "pciephy";
perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
status = "disabled";
};
pcie1_phy: phy@1c0e000 {
compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
reg = <0 0x01c0e000 0 0x1c0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
clock-names = "aux", "cfg_ahb", "refgen";
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "phy";
assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
assigned-clock-rates = <100000000>;
status = "disabled";
pcie1_lane: phy@1c0e200 {
reg = <0 0x1c0e200 0 0x170>, /* tx0 */
<0 0x1c0e400 0 0x200>, /* rx0 */
<0 0x1c0ea00 0 0x1f0>, /* pcs */
<0 0x1c0e600 0 0x170>, /* tx1 */
<0 0x1c0e800 0 0x200>, /* rx1 */
<0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "pipe0";
#phy-cells = <0>;
clock-output-names = "pcie_1_pipe_clk";
};
};
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
@ -1807,6 +2031,8 @@ ufs_mem_phy: phy@1d87000 {
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
power-domains = <&gcc UFS_PHY_GDSC>;
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
status = "disabled";
@ -2048,6 +2274,7 @@ tlmm: pinctrl@3100000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
qup_i2c0_default: qup-i2c0-default {
mux {
@ -2448,6 +2675,52 @@ qup_spi19_default: qup-spi19-default {
drive-strength = <6>;
bias-disable;
};
pcie0_default_state: pcie0-default {
perst {
pins = "gpio35";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq {
pins = "gpio36";
function = "pci_e0";
drive-strength = <2>;
bias-pull-up;
};
wake {
pins = "gpio37";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie1_default_state: pcie1-default {
perst {
pins = "gpio102";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq {
pins = "gpio103";
function = "pci_e1";
drive-strength = <2>;
bias-pull-up;
};
wake {
pins = "gpio104";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};
remoteproc_mpss: remoteproc@4080000 {
@ -3270,6 +3543,51 @@ usb_2_ssphy: phy@88eb200 {
};
};
sdhc_2: sdhci@8804000 {
compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "core", "xo";
iommus = <&apps_smmu 0x6a0 0x0>;
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
power-domains = <&rpmhpd 0>;
operating-points-v2 = <&sdhc2_opp_table>;
status = "disabled";
sdhc2_opp_table: sdhc2-opp-table {
compatible = "operating-points-v2";
opp-19200000 {
opp-hz = /bits/ 64 <19200000>;
required-opps = <&rpmhpd_opp_min_svs>;
};
opp-50000000 {
opp-hz = /bits/ 64 <50000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
};
dc_noc: interconnect@9160000 {
compatible = "qcom,sm8150-dc-noc";
reg = <0 0x09160000 0 0x3200>;
@ -3381,6 +3699,16 @@ camnoc_virt: interconnect@ac00000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8150-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x400>;
qcom,pdc-ranges = <0 480 94>, <94 609 31>,
<125 63 1>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sm8150-aoss-qmp";
reg = <0x0 0x0c300000 0x0 0x400>;
@ -3744,7 +4072,7 @@ rpmhpd_opp_turbo_l1: opp11 {
};
};
apps_bcm_voter: bcm_voter {
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
};
};

30
arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi
View File

@ -441,7 +441,35 @@ &i2c2 {
status = "okay";
clock-frequency = <1000000>;
/* Dual Cirrus Logic CS35L41 amps @ 40, 41 */
cs35l41_l: cs35l41@40 {
compatible = "cirrus,cs35l41";
reg = <0x40>;
interrupt-parent = <&tlmm>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
cirrus,boost-peak-milliamp = <4000>;
cirrus,boost-ind-nanohenry = <1000>;
cirrus,boost-cap-microfarad = <15>;
cirrus,asp-sdout-hiz = <3>;
cirrus,gpio2-src-select = <2>;
cirrus,gpio2-output-enable;
#sound-dai-cells = <1>;
};
cs35l41_r: cs35l41@41 {
compatible = "cirrus,cs35l41";
reg = <0x41>;
interrupt-parent = <&tlmm>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
cirrus,boost-peak-milliamp = <4000>;
cirrus,boost-ind-nanohenry = <1000>;
cirrus,boost-cap-microfarad = <15>;
cirrus,asp-sdout-hiz = <3>;
cirrus,gpio2-src-select = <2>;
cirrus,gpio2-output-enable;
#sound-dai-cells = <1>;
};
};
&i2c5 {

339
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@ -18,6 +18,7 @@
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/clock/qcom,camcc-sm8250.h>
#include <dt-bindings/clock/qcom,videocc-sm8250.h>
/ {
@ -3149,6 +3150,256 @@ videocc: clock-controller@abf0000 {
#power-domain-cells = <1>;
};
cci0: cci@ac4f000 {
compatible = "qcom,sm8250-cci";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x0ac4f000 0 0x1000>;
interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
power-domains = <&camcc TITAN_TOP_GDSC>;
clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
<&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&camcc CAM_CC_CPAS_AHB_CLK>,
<&camcc CAM_CC_CCI_0_CLK>,
<&camcc CAM_CC_CCI_0_CLK_SRC>;
clock-names = "camnoc_axi",
"slow_ahb_src",
"cpas_ahb",
"cci",
"cci_src";
pinctrl-0 = <&cci0_default>;
pinctrl-1 = <&cci0_sleep>;
pinctrl-names = "default", "sleep";
status = "disabled";
cci0_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci0_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
cci1: cci@ac50000 {
compatible = "qcom,sm8250-cci";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x0ac50000 0 0x1000>;
interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
power-domains = <&camcc TITAN_TOP_GDSC>;
clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
<&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&camcc CAM_CC_CPAS_AHB_CLK>,
<&camcc CAM_CC_CCI_1_CLK>,
<&camcc CAM_CC_CCI_1_CLK_SRC>;
clock-names = "camnoc_axi",
"slow_ahb_src",
"cpas_ahb",
"cci",
"cci_src";
pinctrl-0 = <&cci1_default>;
pinctrl-1 = <&cci1_sleep>;
pinctrl-names = "default", "sleep";
status = "disabled";
cci1_i2c0: i2c-bus@0 {
reg = <0>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
cci1_i2c1: i2c-bus@1 {
reg = <1>;
clock-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
camss: camss@ac6a000 {
compatible = "qcom,sm8250-camss";
status = "disabled";
reg = <0 0xac6a000 0 0x2000>,
<0 0xac6c000 0 0x2000>,
<0 0xac6e000 0 0x1000>,
<0 0xac70000 0 0x1000>,
<0 0xac72000 0 0x1000>,
<0 0xac74000 0 0x1000>,
<0 0xacb4000 0 0xd000>,
<0 0xacc3000 0 0xd000>,
<0 0xacd9000 0 0x2200>,
<0 0xacdb200 0 0x2200>;
reg-names = "csiphy0",
"csiphy1",
"csiphy2",
"csiphy3",
"csiphy4",
"csiphy5",
"vfe0",
"vfe1",
"vfe_lite0",
"vfe_lite1";
interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "csiphy0",
"csiphy1",
"csiphy2",
"csiphy3",
"csiphy4",
"csiphy5",
"csid0",
"csid1",
"csid2",
"csid3",
"vfe0",
"vfe1",
"vfe_lite0",
"vfe_lite1";
power-domains = <&camcc IFE_0_GDSC>,
<&camcc IFE_1_GDSC>,
<&camcc TITAN_TOP_GDSC>;
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
<&gcc GCC_CAMERA_HF_AXI_CLK>,
<&gcc GCC_CAMERA_SF_AXI_CLK>,
<&camcc CAM_CC_CAMNOC_AXI_CLK>,
<&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
<&camcc CAM_CC_CORE_AHB_CLK>,
<&camcc CAM_CC_CPAS_AHB_CLK>,
<&camcc CAM_CC_CSIPHY0_CLK>,
<&camcc CAM_CC_CSI0PHYTIMER_CLK>,
<&camcc CAM_CC_CSIPHY1_CLK>,
<&camcc CAM_CC_CSI1PHYTIMER_CLK>,
<&camcc CAM_CC_CSIPHY2_CLK>,
<&camcc CAM_CC_CSI2PHYTIMER_CLK>,
<&camcc CAM_CC_CSIPHY3_CLK>,
<&camcc CAM_CC_CSI3PHYTIMER_CLK>,
<&camcc CAM_CC_CSIPHY4_CLK>,
<&camcc CAM_CC_CSI4PHYTIMER_CLK>,
<&camcc CAM_CC_CSIPHY5_CLK>,
<&camcc CAM_CC_CSI5PHYTIMER_CLK>,
<&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&camcc CAM_CC_IFE_0_AHB_CLK>,
<&camcc CAM_CC_IFE_0_AXI_CLK>,
<&camcc CAM_CC_IFE_0_CLK>,
<&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_0_CSID_CLK>,
<&camcc CAM_CC_IFE_0_AREG_CLK>,
<&camcc CAM_CC_IFE_1_AHB_CLK>,
<&camcc CAM_CC_IFE_1_AXI_CLK>,
<&camcc CAM_CC_IFE_1_CLK>,
<&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_1_CSID_CLK>,
<&camcc CAM_CC_IFE_1_AREG_CLK>,
<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
<&camcc CAM_CC_IFE_LITE_AXI_CLK>,
<&camcc CAM_CC_IFE_LITE_CLK>,
<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_LITE_CSID_CLK>;
clock-names = "cam_ahb_clk",
"cam_hf_axi",
"cam_sf_axi",
"camnoc_axi",
"camnoc_axi_src",
"core_ahb",
"cpas_ahb",
"csiphy0",
"csiphy0_timer",
"csiphy1",
"csiphy1_timer",
"csiphy2",
"csiphy2_timer",
"csiphy3",
"csiphy3_timer",
"csiphy4",
"csiphy4_timer",
"csiphy5",
"csiphy5_timer",
"slow_ahb_src",
"vfe0_ahb",
"vfe0_axi",
"vfe0",
"vfe0_cphy_rx",
"vfe0_csid",
"vfe0_areg",
"vfe1_ahb",
"vfe1_axi",
"vfe1",
"vfe1_cphy_rx",
"vfe1_csid",
"vfe1_areg",
"vfe_lite_ahb",
"vfe_lite_axi",
"vfe_lite",
"vfe_lite_cphy_rx",
"vfe_lite_csid";
iommus = <&apps_smmu 0x800 0x400>,
<&apps_smmu 0x801 0x400>,
<&apps_smmu 0x840 0x400>,
<&apps_smmu 0x841 0x400>,
<&apps_smmu 0xc00 0x400>,
<&apps_smmu 0xc01 0x400>,
<&apps_smmu 0xc40 0x400>,
<&apps_smmu 0xc41 0x400>;
interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>,
<&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,
<&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,
<&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>;
interconnect-names = "cam_ahb",
"cam_hf_0_mnoc",
"cam_sf_0_mnoc",
"cam_sf_icp_mnoc";
};
camcc: clock-controller@ad00000 {
compatible = "qcom,sm8250-camcc";
reg = <0 0x0ad00000 0 0x10000>;
clocks = <&gcc GCC_CAMERA_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
power-domains = <&rpmhpd SM8250_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
mdss: mdss@ae00000 {
compatible = "qcom,sm8250-mdss";
reg = <0 0x0ae00000 0 0x1000>;
@ -3202,7 +3453,7 @@ mdss_mdp: mdp@ae01000 {
power-domains = <&rpmhpd SM8250_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <0>;
ports {
#address-cells = <1>;
@ -3254,7 +3505,7 @@ dsi0: dsi@ae94000 {
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <4>;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
@ -3327,7 +3578,7 @@ dsi1: dsi@ae96000 {
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <5>;
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
@ -3519,6 +3770,86 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 181>;
wakeup-parent = <&pdc>;
cci0_default: cci0-default {
cci0_i2c0_default: cci0-i2c0-default {
/* SDA, SCL */
pins = "gpio101", "gpio102";
function = "cci_i2c";
bias-pull-up;
drive-strength = <2>; /* 2 mA */
};
cci0_i2c1_default: cci0-i2c1-default {
/* SDA, SCL */
pins = "gpio103", "gpio104";
function = "cci_i2c";
bias-pull-up;
drive-strength = <2>; /* 2 mA */
};
};
cci0_sleep: cci0-sleep {
cci0_i2c0_sleep: cci0-i2c0-sleep {
/* SDA, SCL */
pins = "gpio101", "gpio102";
function = "cci_i2c";
drive-strength = <2>; /* 2 mA */
bias-pull-down;
};
cci0_i2c1_sleep: cci0-i2c1-sleep {
/* SDA, SCL */
pins = "gpio103", "gpio104";
function = "cci_i2c";
drive-strength = <2>; /* 2 mA */
bias-pull-down;
};
};
cci1_default: cci1-default {
cci1_i2c0_default: cci1-i2c0-default {
/* SDA, SCL */
pins = "gpio105","gpio106";
function = "cci_i2c";
bias-pull-up;
drive-strength = <2>; /* 2 mA */
};
cci1_i2c1_default: cci1-i2c1-default {
/* SDA, SCL */
pins = "gpio107","gpio108";
function = "cci_i2c";
bias-pull-up;
drive-strength = <2>; /* 2 mA */
};
};
cci1_sleep: cci1-sleep {
cci1_i2c0_sleep: cci1-i2c0-sleep {
/* SDA, SCL */
pins = "gpio105","gpio106";
function = "cci_i2c";
bias-pull-down;
drive-strength = <2>; /* 2 mA */
};
cci1_i2c1_sleep: cci1-i2c1-sleep {
/* SDA, SCL */
pins = "gpio107","gpio108";
function = "cci_i2c";
bias-pull-down;
drive-strength = <2>; /* 2 mA */
};
};
pri_mi2s_active: pri-mi2s-active {
sclk {
pins = "gpio138";
@ -4654,7 +4985,7 @@ rpmhpd_opp_turbo_l1: opp10 {
};
};
apps_bcm_voter: bcm_voter {
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
};
};

4
arch/arm64/boot/dts/qcom/sm8350-hdk.dts
View File

@ -213,6 +213,10 @@ &cdsp {
firmware-name = "qcom/sm8350/cdsp.mbn";
};
&gpi_dma1 {
status = "okay";
};
&mpss {
status = "okay";
firmware-name = "qcom/sm8350/modem.mbn";

12
arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts
View File

@ -281,6 +281,14 @@ &cdsp {
firmware-name = "qcom/sm8350/microsoft/cdsp.mbn";
};
&i2c10 {
status = "okay";
};
&i2c11 {
status = "okay";
};
&ipa {
status = "okay";
@ -296,6 +304,10 @@ &qupv3_id_0 {
status = "okay";
};
&qupv3_id_1 {
status = "okay";
};
&slpi {
status = "okay";
firmware-name = "qcom/sm8350/microsoft/slpi.mbn";

186
arch/arm64/boot/dts/qcom/sm8350.dtsi
View File

@ -6,6 +6,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,sm8350.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
@ -675,6 +676,28 @@ opp-120000000 {
};
};
gpi_dma2: dma-controller@800000 {
compatible = "qcom,sm8350-gpi-dma";
reg = <0 0x00800000 0 0x60000>;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <12>;
dma-channel-mask = <0xff>;
iommus = <&apps_smmu 0x5f6 0x0>;
#dma-cells = <3>;
status = "disabled";
};
qupv3_id_2: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
@ -695,6 +718,9 @@ i2c14: i2c@880000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c14_default>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
<&gpi_dma2 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -708,6 +734,9 @@ spi14: spi@880000 {
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_120mhz>;
dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
<&gpi_dma2 1 0 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -721,6 +750,9 @@ i2c15: i2c@884000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c15_default>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
<&gpi_dma2 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -734,6 +766,9 @@ spi15: spi@884000 {
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_120mhz>;
dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
<&gpi_dma2 1 1 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -747,6 +782,9 @@ i2c16: i2c@888000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c16_default>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
<&gpi_dma2 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -760,6 +798,9 @@ spi16: spi@888000 {
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
<&gpi_dma2 1 2 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -773,6 +814,9 @@ i2c17: i2c@88c000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c17_default>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
<&gpi_dma2 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -786,6 +830,9 @@ spi17: spi@88c000 {
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
<&gpi_dma2 1 3 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -801,6 +848,9 @@ spi18: spi@890000 {
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
<&gpi_dma2 1 4 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -827,6 +877,9 @@ i2c19: i2c@894000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c19_default>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
<&gpi_dma2 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -840,12 +893,37 @@ spi19: spi@894000 {
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
<&gpi_dma2 1 5 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
gpi_dma0: dma-controller@900000 {
compatible = "qcom,sm8350-gpi-dma";
reg = <0 0x09800000 0 0x60000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <12>;
dma-channel-mask = <0x7e>;
iommus = <&apps_smmu 0x5b6 0x0>;
#dma-cells = <3>;
status = "disabled";
};
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x009c0000 0x0 0x6000>;
@ -866,6 +944,9 @@ i2c0: i2c@980000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -879,6 +960,9 @@ spi0: spi@980000 {
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -892,6 +976,9 @@ i2c1: i2c@984000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -905,6 +992,9 @@ spi1: spi@984000 {
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -918,6 +1008,9 @@ i2c2: i2c@988000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -931,6 +1024,9 @@ spi2: spi@988000 {
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -961,6 +1057,9 @@ spi3: spi@98c000 {
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
<&gpi_dma0 1 3 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -974,6 +1073,9 @@ i2c4: i2c@990000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c4_default>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -987,6 +1089,9 @@ spi4: spi@990000 {
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
<&gpi_dma0 1 4 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1000,6 +1105,9 @@ i2c5: i2c@994000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1013,6 +1121,9 @@ spi5: spi@994000 {
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
<&gpi_dma0 1 5 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1026,6 +1137,9 @@ i2c6: i2c@998000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c6_default>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
<&gpi_dma0 1 6 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1039,6 +1153,9 @@ spi6: spi@998000 {
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
<&gpi_dma0 1 6 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1065,6 +1182,9 @@ i2c7: i2c@99c000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c7_default>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
<&gpi_dma0 1 7 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1078,12 +1198,37 @@ spi7: spi@99c000 {
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
<&gpi_dma0 1 7 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
gpi_dma1: dma-controller@a00000 {
compatible = "qcom,sm8350-gpi-dma";
reg = <0 0x00a00000 0 0x60000>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <12>;
dma-channel-mask = <0xff>;
iommus = <&apps_smmu 0x56 0x0>;
#dma-cells = <3>;
status = "disabled";
};
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x6000>;
@ -1104,6 +1249,9 @@ i2c8: i2c@a80000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c8_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1117,6 +1265,9 @@ spi8: spi@a80000 {
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_120mhz>;
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1130,6 +1281,9 @@ i2c9: i2c@a84000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c9_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1143,6 +1297,9 @@ spi9: spi@a84000 {
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
<&gpi_dma1 1 1 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1156,6 +1313,9 @@ i2c10: i2c@a88000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c10_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1169,6 +1329,9 @@ spi10: spi@a88000 {
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1182,6 +1345,9 @@ i2c11: i2c@a8c000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c11_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1195,6 +1361,9 @@ spi11: spi@a8c000 {
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1208,6 +1377,9 @@ i2c12: i2c@a90000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c12_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1221,6 +1393,9 @@ spi12: spi@a90000 {
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
<&gpi_dma1 1 4 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1234,6 +1409,9 @@ i2c13: i2c@a94000 {
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c13_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
<&gpi_dma1 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1247,6 +1425,9 @@ spi13: spi@a94000 {
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
<&gpi_dma1 1 5 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -1881,7 +2062,7 @@ rpmhpd_opp_turbo_l1: opp10 {
};
};
apps_bcm_voter: bcm_voter {
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
};
};
@ -1916,7 +2097,6 @@ ufs_mem_hc: ufshc@1d84000 {
iommus = <&apps_smmu 0xe0 0x0>;
clock-names =
"ref_clk",
"core_clk",
"bus_aggr_clk",
"iface_clk",
@ -1926,7 +2106,6 @@ ufs_mem_hc: ufshc@1d84000 {
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
@ -1936,7 +2115,6 @@ ufs_mem_hc: ufshc@1d84000 {
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<75000000 300000000>,
<75000000 300000000>,
<0 0>,
<0 0>,

41
arch/arm64/boot/dts/qcom/sm8450-hdk.dts
View File

@ -349,6 +349,47 @@ vreg_l7e_2p8: ldo7 {
};
};
&pcie0 {
status = "okay";
max-link-speed = <2>;
};
&pcie0_phy {
status = "okay";
vdda-phy-supply = <&vreg_l5b_0p88>;
vdda-pll-supply = <&vreg_l6b_1p2>;
};
&pcie1 {
status = "okay";
};
&pcie1_phy {
status = "okay";
vdda-phy-supply = <&vreg_l2h_0p91>;
vdda-pll-supply = <&vreg_l6b_1p2>;
};
&remoteproc_adsp {
status = "okay";
firmware-name = "qcom/sm8450/adsp.mbn";
};
&remoteproc_cdsp {
status = "okay";
firmware-name = "qcom/sm8450/cdsp.mbn";
};
&remoteproc_mpss {
status = "okay";
firmware-name = "qcom/sm8450/modem.mbn";
};
&remoteproc_slpi {
status = "okay";
firmware-name = "qcom/sm8450/slpi.mbn";
};
&qupv3_id_0 {
status = "okay";
};

34
arch/arm64/boot/dts/qcom/sm8450-qrd.dts
View File

@ -342,10 +342,32 @@ vreg_l6e_1p2: ldo6 {
};
};
&pcie0 {
status = "okay";
};
&pcie0_phy {
status = "okay";
vdda-phy-supply = <&vreg_l5b_0p88>;
vdda-pll-supply = <&vreg_l6b_1p2>;
};
&gpi_dma0 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&qupv3_id_0 {
status = "okay";
};
&qupv3_id_2 {
status = "okay";
};
&remoteproc_adsp {
status = "okay";
firmware-name = "qcom/sm8450/adsp.mbn";
@ -366,6 +388,18 @@ &remoteproc_slpi {
firmware-name = "qcom/sm8450/slpi.mbn";
};
&spi4 {
status = "okay";
};
&spi18 {
status = "okay";
};
&spi19 {
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <28 4>, <36 4>;
};

2500
arch/arm64/boot/dts/qcom/sm8450.dtsi
View File

File diff suppressed because it is too large Load Diff

4
include/dt-bindings/clock/qcom,gcc-msm8998.h
View File

@ -186,6 +186,10 @@
#define UFS_UNIPRO_CORE_CLK_SRC 177
#define GCC_MMSS_GPLL0_CLK 178
#define HMSS_GPLL0_CLK_SRC 179
#define GCC_IM_SLEEP 180
#define AGGRE2_SNOC_NORTH_AXI 181
#define SSC_XO 182
#define SSC_CNOC_AHBS_CLK 183
#define PCIE_0_GDSC 0
#define UFS_GDSC 1

43
include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h Normal file
View File

@ -0,0 +1,43 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SC7280_H
#define _DT_BINDINGS_CLK_QCOM_LPASS_AUDIO_CC_SC7280_H
/* LPASS_AUDIO_CC clocks */
#define LPASS_AUDIO_CC_PLL 0
#define LPASS_AUDIO_CC_PLL_OUT_AUX2 1
#define LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC 2
#define LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC 3
#define LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC 4
#define LPASS_AUDIO_CC_CODEC_MEM0_CLK 5
#define LPASS_AUDIO_CC_CODEC_MEM1_CLK 6
#define LPASS_AUDIO_CC_CODEC_MEM2_CLK 7
#define LPASS_AUDIO_CC_CODEC_MEM_CLK 8
#define LPASS_AUDIO_CC_EXT_MCLK0_CLK 9
#define LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC 10
#define LPASS_AUDIO_CC_EXT_MCLK1_CLK 11
#define LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC 12
#define LPASS_AUDIO_CC_RX_MCLK_2X_CLK 13
#define LPASS_AUDIO_CC_RX_MCLK_CLK 14
#define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 15
/* LPASS_AON_CC clocks */
#define LPASS_AON_CC_PLL 0
#define LPASS_AON_CC_PLL_OUT_EVEN 1
#define LPASS_AON_CC_PLL_OUT_MAIN_CDIV_DIV_CLK_SRC 2
#define LPASS_AON_CC_PLL_OUT_ODD 3
#define LPASS_AON_CC_AUDIO_HM_H_CLK 4
#define LPASS_AON_CC_CDIV_TX_MCLK_DIV_CLK_SRC 5
#define LPASS_AON_CC_MAIN_RCG_CLK_SRC 6
#define LPASS_AON_CC_TX_MCLK_2X_CLK 7
#define LPASS_AON_CC_TX_MCLK_CLK 8
#define LPASS_AON_CC_TX_MCLK_RCG_CLK_SRC 9
#define LPASS_AON_CC_VA_MEM0_CLK 10
/* LPASS_AON_CC power domains */
#define LPASS_AON_CC_LPASS_AUDIO_HM_GDSC 0
#endif

26
include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h Normal file
View File

@ -0,0 +1,26 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7280_H
#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7280_H
/* LPASS_CORE_CC clocks */
#define LPASS_CORE_CC_DIG_PLL 0
#define LPASS_CORE_CC_DIG_PLL_OUT_MAIN_DIV_CLK_SRC 1
#define LPASS_CORE_CC_DIG_PLL_OUT_ODD 2
#define LPASS_CORE_CC_CORE_CLK 3
#define LPASS_CORE_CC_CORE_CLK_SRC 4
#define LPASS_CORE_CC_EXT_IF0_CLK_SRC 5
#define LPASS_CORE_CC_EXT_IF0_IBIT_CLK 6
#define LPASS_CORE_CC_EXT_IF1_CLK_SRC 7
#define LPASS_CORE_CC_EXT_IF1_IBIT_CLK 8
#define LPASS_CORE_CC_LPM_CORE_CLK 9
#define LPASS_CORE_CC_LPM_MEM0_CORE_CLK 10
#define LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK 11
/* LPASS_CORE_CC power domains */
#define LPASS_CORE_CC_LPASS_CORE_HM_GDSC 0
#endif