crypto: atmel-aes - add support to the XTS mode
This patch adds the xts(aes) algorithm, which is supported from hardware version 0x500 and above (sama5d2x). Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Cyrille Pitchen
Herbert Xu
parent
f709dc86bc
commit
d52db5188a
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@ -28,6 +28,7 @@
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#define AES_MR_OPMOD_CFB (0x3 << 12)
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#define AES_MR_OPMOD_CTR (0x4 << 12)
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#define AES_MR_OPMOD_GCM (0x5 << 12)
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#define AES_MR_OPMOD_XTS (0x6 << 12)
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#define AES_MR_LOD (0x1 << 15)
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#define AES_MR_CFBS_MASK (0x7 << 16)
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#define AES_MR_CFBS_128b (0x0 << 16)
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@ -67,6 +68,9 @@
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#define AES_CTRR 0x98
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#define AES_GCMHR(x) (0x9c + ((x) * 0x04))
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#define AES_TWR(x) (0xc0 + ((x) * 0x04))
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#define AES_ALPHAR(x) (0xd0 + ((x) * 0x04))
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#define AES_HW_VERSION 0xFC
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#endif /* __ATMEL_AES_REGS_H__ */
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@ -36,6 +36,7 @@
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#include <crypto/scatterwalk.h>
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#include <crypto/algapi.h>
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#include <crypto/aes.h>
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#include <crypto/xts.h>
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#include <crypto/internal/aead.h>
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#include <linux/platform_data/crypto-atmel.h>
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#include <dt-bindings/dma/at91.h>
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@ -68,6 +69,7 @@
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#define AES_FLAGS_CFB8 (AES_MR_OPMOD_CFB | AES_MR_CFBS_8b)
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#define AES_FLAGS_CTR AES_MR_OPMOD_CTR
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#define AES_FLAGS_GCM AES_MR_OPMOD_GCM
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#define AES_FLAGS_XTS AES_MR_OPMOD_XTS
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#define AES_FLAGS_MODE_MASK (AES_FLAGS_OPMODE_MASK | \
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AES_FLAGS_ENCRYPT | \
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@ -89,6 +91,7 @@ struct atmel_aes_caps {
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bool has_cfb64;
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bool has_ctr32;
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bool has_gcm;
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bool has_xts;
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u32 max_burst_size;
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};
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@ -135,6 +138,12 @@ struct atmel_aes_gcm_ctx {
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atmel_aes_fn_t ghash_resume;
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};
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struct atmel_aes_xts_ctx {
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struct atmel_aes_base_ctx base;
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u32 key2[AES_KEYSIZE_256 / sizeof(u32)];
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};
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struct atmel_aes_reqctx {
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unsigned long mode;
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};
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@ -282,6 +291,20 @@ static const char *atmel_aes_reg_name(u32 offset, char *tmp, size_t sz)
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snprintf(tmp, sz, "GCMHR[%u]", (offset - AES_GCMHR(0)) >> 2);
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break;
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case AES_TWR(0):
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case AES_TWR(1):
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case AES_TWR(2):
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case AES_TWR(3):
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snprintf(tmp, sz, "TWR[%u]", (offset - AES_TWR(0)) >> 2);
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break;
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case AES_ALPHAR(0):
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case AES_ALPHAR(1):
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case AES_ALPHAR(2):
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case AES_ALPHAR(3):
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snprintf(tmp, sz, "ALPHAR[%u]", (offset - AES_ALPHAR(0)) >> 2);
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break;
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default:
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snprintf(tmp, sz, "0x%02x", offset);
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break;
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@ -453,15 +476,15 @@ static inline int atmel_aes_complete(struct atmel_aes_dev *dd, int err)
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return err;
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}
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static void atmel_aes_write_ctrl(struct atmel_aes_dev *dd, bool use_dma,
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const u32 *iv)
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static void atmel_aes_write_ctrl_key(struct atmel_aes_dev *dd, bool use_dma,
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const u32 *iv, const u32 *key, int keylen)
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{
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u32 valmr = 0;
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/* MR register must be set before IV registers */
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if (dd->ctx->keylen == AES_KEYSIZE_128)
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if (keylen == AES_KEYSIZE_128)
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valmr |= AES_MR_KEYSIZE_128;
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else if (dd->ctx->keylen == AES_KEYSIZE_192)
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else if (keylen == AES_KEYSIZE_192)
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valmr |= AES_MR_KEYSIZE_192;
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else
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valmr |= AES_MR_KEYSIZE_256;
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@ -478,13 +501,19 @@ static void atmel_aes_write_ctrl(struct atmel_aes_dev *dd, bool use_dma,
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atmel_aes_write(dd, AES_MR, valmr);
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atmel_aes_write_n(dd, AES_KEYWR(0), dd->ctx->key,
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SIZE_IN_WORDS(dd->ctx->keylen));
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atmel_aes_write_n(dd, AES_KEYWR(0), key, SIZE_IN_WORDS(keylen));
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if (iv && (valmr & AES_MR_OPMOD_MASK) != AES_MR_OPMOD_ECB)
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atmel_aes_write_block(dd, AES_IVR(0), iv);
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}
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static inline void atmel_aes_write_ctrl(struct atmel_aes_dev *dd, bool use_dma,
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const u32 *iv)
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{
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atmel_aes_write_ctrl_key(dd, use_dma, iv,
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dd->ctx->key, dd->ctx->keylen);
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}
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/* CPU transfer */
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@ -1769,6 +1798,137 @@ static struct aead_alg aes_gcm_alg = {
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};
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/* xts functions */
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static inline struct atmel_aes_xts_ctx *
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atmel_aes_xts_ctx_cast(struct atmel_aes_base_ctx *ctx)
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{
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return container_of(ctx, struct atmel_aes_xts_ctx, base);
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}
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static int atmel_aes_xts_process_data(struct atmel_aes_dev *dd);
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static int atmel_aes_xts_start(struct atmel_aes_dev *dd)
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{
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struct atmel_aes_xts_ctx *ctx = atmel_aes_xts_ctx_cast(dd->ctx);
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struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
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struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
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unsigned long flags;
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int err;
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atmel_aes_set_mode(dd, rctx);
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err = atmel_aes_hw_init(dd);
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if (err)
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return atmel_aes_complete(dd, err);
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/* Compute the tweak value from req->info with ecb(aes). */
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flags = dd->flags;
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dd->flags &= ~AES_FLAGS_MODE_MASK;
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dd->flags |= (AES_FLAGS_ECB | AES_FLAGS_ENCRYPT);
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atmel_aes_write_ctrl_key(dd, false, NULL,
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ctx->key2, ctx->base.keylen);
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dd->flags = flags;
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atmel_aes_write_block(dd, AES_IDATAR(0), req->info);
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return atmel_aes_wait_for_data_ready(dd, atmel_aes_xts_process_data);
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}
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static int atmel_aes_xts_process_data(struct atmel_aes_dev *dd)
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{
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struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
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bool use_dma = (req->nbytes >= ATMEL_AES_DMA_THRESHOLD);
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u32 tweak[AES_BLOCK_SIZE / sizeof(u32)];
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static const u32 one[AES_BLOCK_SIZE / sizeof(u32)] = {cpu_to_le32(1), };
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u8 *tweak_bytes = (u8 *)tweak;
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int i;
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/* Read the computed ciphered tweak value. */
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atmel_aes_read_block(dd, AES_ODATAR(0), tweak);
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/*
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* Hardware quirk:
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* the order of the ciphered tweak bytes need to be reversed before
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* writing them into the ODATARx registers.
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*/
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for (i = 0; i < AES_BLOCK_SIZE/2; ++i) {
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u8 tmp = tweak_bytes[AES_BLOCK_SIZE - 1 - i];
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tweak_bytes[AES_BLOCK_SIZE - 1 - i] = tweak_bytes[i];
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tweak_bytes[i] = tmp;
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}
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/* Process the data. */
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atmel_aes_write_ctrl(dd, use_dma, NULL);
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atmel_aes_write_block(dd, AES_TWR(0), tweak);
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atmel_aes_write_block(dd, AES_ALPHAR(0), one);
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if (use_dma)
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return atmel_aes_dma_start(dd, req->src, req->dst, req->nbytes,
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atmel_aes_transfer_complete);
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return atmel_aes_cpu_start(dd, req->src, req->dst, req->nbytes,
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atmel_aes_transfer_complete);
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}
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static int atmel_aes_xts_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
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unsigned int keylen)
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{
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struct atmel_aes_xts_ctx *ctx = crypto_ablkcipher_ctx(tfm);
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int err;
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err = xts_check_key(crypto_ablkcipher_tfm(tfm), key, keylen);
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if (err)
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return err;
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memcpy(ctx->base.key, key, keylen/2);
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memcpy(ctx->key2, key + keylen/2, keylen/2);
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ctx->base.keylen = keylen/2;
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return 0;
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}
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static int atmel_aes_xts_encrypt(struct ablkcipher_request *req)
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{
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return atmel_aes_crypt(req, AES_FLAGS_XTS | AES_FLAGS_ENCRYPT);
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}
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static int atmel_aes_xts_decrypt(struct ablkcipher_request *req)
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{
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return atmel_aes_crypt(req, AES_FLAGS_XTS);
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}
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static int atmel_aes_xts_cra_init(struct crypto_tfm *tfm)
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{
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struct atmel_aes_xts_ctx *ctx = crypto_tfm_ctx(tfm);
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tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
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ctx->base.start = atmel_aes_xts_start;
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return 0;
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}
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static struct crypto_alg aes_xts_alg = {
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.cra_name = "xts(aes)",
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.cra_driver_name = "atmel-xts-aes",
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.cra_priority = ATMEL_AES_PRIORITY,
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.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
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.cra_blocksize = AES_BLOCK_SIZE,
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.cra_ctxsize = sizeof(struct atmel_aes_xts_ctx),
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.cra_alignmask = 0xf,
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.cra_type = &crypto_ablkcipher_type,
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.cra_module = THIS_MODULE,
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.cra_init = atmel_aes_xts_cra_init,
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.cra_exit = atmel_aes_cra_exit,
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.cra_u.ablkcipher = {
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.min_keysize = 2 * AES_MIN_KEY_SIZE,
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.max_keysize = 2 * AES_MAX_KEY_SIZE,
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.ivsize = AES_BLOCK_SIZE,
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.setkey = atmel_aes_xts_setkey,
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.encrypt = atmel_aes_xts_encrypt,
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.decrypt = atmel_aes_xts_decrypt,
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}
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};
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/* Probe functions */
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static int atmel_aes_buff_init(struct atmel_aes_dev *dd)
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@ -1877,6 +2037,9 @@ static void atmel_aes_unregister_algs(struct atmel_aes_dev *dd)
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{
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int i;
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if (dd->caps.has_xts)
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crypto_unregister_alg(&aes_xts_alg);
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if (dd->caps.has_gcm)
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crypto_unregister_aead(&aes_gcm_alg);
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@ -1909,8 +2072,16 @@ static int atmel_aes_register_algs(struct atmel_aes_dev *dd)
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goto err_aes_gcm_alg;
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}
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if (dd->caps.has_xts) {
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err = crypto_register_alg(&aes_xts_alg);
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if (err)
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goto err_aes_xts_alg;
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}
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return 0;
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err_aes_xts_alg:
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crypto_unregister_aead(&aes_gcm_alg);
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err_aes_gcm_alg:
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crypto_unregister_alg(&aes_cfb64_alg);
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err_aes_cfb64_alg:
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@ -1928,6 +2099,7 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
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dd->caps.has_cfb64 = 0;
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dd->caps.has_ctr32 = 0;
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dd->caps.has_gcm = 0;
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dd->caps.has_xts = 0;
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dd->caps.max_burst_size = 1;
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/* keep only major version number */
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@ -1937,6 +2109,7 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
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dd->caps.has_cfb64 = 1;
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dd->caps.has_ctr32 = 1;
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dd->caps.has_gcm = 1;
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dd->caps.has_xts = 1;
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dd->caps.max_burst_size = 4;
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break;
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case 0x200:
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